Ramaprasad is seeking a job as an ASIC verification engineer with over 3 years of experience in RTL verification. He has experience verifying IP blocks using SystemVerilog and UVM, including projects involving AOP SoC, MIPI-MPHY, CAN, SPI, AXI4, MIPI DSI, and router verification. He is proficient in SystemVerilog, UVM, QuestaSim, and has experience developing testbenches, writing directed and randomized tests, and achieving coverage closure. He holds a BE in electronics and communication engineering.