Hello Everyone, I am an ECE Trained Fresher and currently looking for opportunities in Design and Verification domain. I would be grateful if you could help me with the same. Please review my profile and my resume is attached herewith. Thanks and Regards Apoorva Tripathi {apoorvatripathi24@gmail.com}

1. Apoorva Tripathi
Bengaluru (Karnataka, INDIA) - 560083
Email-id : apoorvatripathi24@gmail.com
Contact No.: +917839357152
Linkedin ID: https://www.linkedin.com/in/apoorva-tripathi-71aaa4137/
Career Objective
• Aiming to learn new technologies and gain knowledge by working for a VLSI industry preferably in De-
sign and Verification domain with an opportunity of working with diverse group of people and acquire
proficiency. Take up new challenge and overcome hurdles by utilising my skills and abilities.
Summary of Qualification
• Good Understanding of ASIC and FPGA design flow.
• Extensive experience in writing RTL module using Verilog HDL.
• Good experience in writing Test benches using System Verilog and UVM.
• Good Knowledge in Verification methodologies.
• Experience in using industry standard EDA tools for the front-end and verification.
• Exposure in verification test plan, track debug in design units.
VLSI Domain Skills
• HDL: Verilog
• HVL : System Verilog
• Methodologies: Coverage Driven Verification Assertion Based Verification - SVA
• TB Methodology: UVM
• Protocols: AXI, AHB, UART, I2C, SPI
• EDA Tool: Questasim and ISE
• Domain: ASIC/FPGA front-end Design and Verification
• Knowledge: RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis,
Static Timing Analysis, ABV- SVA
Academic Credentials
Degree Domain Institute Year CPI/%
Bachelor of Technology Electronics and Communication
(Graduation) KIET, Ghaziabad,U.P. 2019 80
Class XII Maths
(CBSE) Vidyashram Public School Kota,Raj. 2014 75
Class X Science
(CBSE) KVS Azamgarh, U.P. 2012 9.2
Professional Qualification
• Maven Silicon Certified Advanced VLSI Design and Verification course from Maven Silicon VLSI Design
and Training Center, Bangalore July 2019 – Present

2. VLSI Project:
• Router 1x3 – RTL design and Verification
◦ HDL: Verilog
◦ HVL: System Verilog
◦ TB Methodology: UVM
◦ EDA Tools: Questasim and ISE
◦ Description: The router accepts data packets on a single 8-bit port and routes them to one of the three
output channels, channel0, channel1 and channel2. .
Responsibilities:
◦ Architected the design
◦ Implemented RTL using Verilog HDL.
◦ Architected the class based verification environment using system Verilog
◦ Verified the RTL model using System Verilog.
◦ Generated functional and code coverage for the RTL verification sign-off
◦ Synthesized the design
◦ Second sub item.
Internship:
• Organisation : Bharat Electronics Limited (BEL).
• Designation : Trainee
• Duration : 4 weeks
• Topic : Study of RADAR
Engineering Project:
• Major Project Title : Design of linear phase Second Order recursive Digital Integrators and Differentiators.
• Description : This includes the steps, taken for improving the efficiency of the digital differentiators. Addi-
tionally, the numerical techniques can be used for finding better solutions which can result in stable magni-
tude response and higher optimization value
Academic Achievement And Co-Curricular Activities:
• Participated in Quiz,Debate and MUN (Model United Nation).
• Student Placement Coordinator (SPC) of College (2018-19).
• ROBOWAR Technical Event : First Position.
• Part of Electric Vehicle Club (Developed Hybrid Electric Vehicle).
• Digital Champions Program at JIO Completed with Platinum Certification.
• Internshala Student Partner12 (ISP) at Internshala. .
Personal Details:
• Father’s Name : Prabha Shanker Tripathi
• Mother’s Name : Poonam Tripathi
• Date of Birth : 22-March-1997
• Lingustic Proficiency : English, Hindi.
• Hobbies : Cricket, Travelling.
Declaration
• I hear by declare that the information furnished above is true to best of my knowledge.
Date:
Place : Signature :