Yogananda Mesa is applying for an ASIC Verification Engineer role. He has 1 year of experience as a Verification Engineer using SystemVerilog and UVM methodologies. His experience includes RTL design and verification, IP verification, assertion-based verification, and coverage-driven verification. He is proficient in Verilog, SystemVerilog, UVM, C/C++, Java, and protocols like AMBA. His projects include verifying an APB protocol design, designing and verifying a dual-port RAM FIFO, and designing and verifying an arbiter. He completed an M.Tech in VLSI System Design.