Ravi D is a VLSI design expert with a strong foundation in digital electronics and hands-on experience in Verilog, System Verilog, and UVM. He holds an M.Tech in VLSI Design with a CGPA of 9.24 and has completed various projects, including RTL design and verification for multiple IP cores using various EDA tools. Ravi's skill set includes programming languages, HDL coding, and knowledge of several communication protocols, enhanced by internships and academic projects.

1. CURRICULAM VITAE
Ravi D
Room No:203, Mayuri PG,
Arekere Main Gate, Opposite Reliance Mart, Email: ravidora15@gmail.com
Bhannerghatta Road, Bangalore, Karnataka Mobile: 08884608550
CAREER OBJECTIVE:
To start my career in the field of VLSI entry and this will enhance my knowledge and skills apart from
working in a challenging environment.
SUMMARY:
 Good understanding of digital concepts.
 Good understanding of the ASIC & FPGA design flow.
 Proficient with hands on experience in Digital Design with Verilog,Development of Verification Environment &
Constraint Random Test Generation in System Verilog and UVM.
 Strong Knowledge on Digital Electronics, CMOS.
EDUCATIONAL QUALIFICATIONS:
Class/Course Institute/Organization Board/University
Percentage
(%)
Year of
Passing
M.Tech
(VLSI Design)
SVCET Engineering College JNTU-Anatapur (A.P) 9.24(CGPA) 2015
B.Tech (ECE) Vemu Institute of Technology JNTU-Anatapur (A.P) 71% 2013
Intermediate
(M.P.C)
S.V.S Junior College
Board of Intermediate
Education, (A.P)
77% 2009
S.S.L.C G.H.S.B.SCHOOL
Board of Secondary
Education (T.N)
70% 2007
VLSI DOMAIN SKILLS
Programming Languages : C, C++, OOPS.
HDLs : Verilog
HVL : System Verilog, UVM
EDA Tools : Xilinx ISE, Modelsim, Questasim-Verification Platform, Matlab
Keil.
Knowledge : RTL coding,FSM based design,Simulation,Code coverage,
Function Coverage,Synthesis,Static Timing Analysis.
Operating Systems : Windows XP, Windows 7, 8, Ubuntu, linux.
PROTOCALS KNOWNS:
 Router1x3, AHB-APB (AMBA protocols), UART, SPI.
INTERN EXPERIENCE:
I have 9 month experience in ASIC design &verification project intern at maven silicon soft tech pvt.ltd.

2. VLSI PROJECTS:
 ROUTER1X3-RTL DESIGN AND VERIFICATION
Duration: 1 month
HDL : Verilog HDL
HVL : System Verilog
TB Methodology : UVM
EDA Tools Used : Xilinx ISE & Questasim.
Description: The router accepts data packets on a single 8-bit port and routes them to one of
The three output channels, channel0, channel1 and channel2.
Responsibilities
Architected the design
Implemented RTL using Verilog HDL.
Architected the class based verification environment using system Verilog.
Verified the RTL model using System Verilog.
Generated functional and code coverage for the RTL verification sign-off.
Synthesized the design.
 UART- IP CORE VERIFICATION
HVL : System Verilog
TB Methodology : UVM
EDA Tools : Questasim
Description:The UART IPcore providesserial communicationcapabilities,whichallow communicationwith
Modemor otherexternal devices. UARTwill operate intwo differentmodes-Simplex mode,
Full Duplex mode.
Responsibilities
 Architected the class based verification environment in UVM
Verified the RTL module using System Verilog
Generated functional and code coverage for the RTL verification sign-off.
 DESIGN A AMBA AHB TO APB BRIDGE
HDL : Verilog
EDA Tools : Xilinx ISE
Description: : AHB to APB Bridge is required to communicate between a high frequency operating AHB
components and low frequency operating APB components. It supports both read and writes operations. AHB is
nearly 3 times faster than APB, to avoid the loss of data between these 2 components the bridge is designed on Pipe-
lining concept. This Bridge acts as master for APB components and as a slave for AHB components, it supports
single, burst and increment type of data transfer.
Responsibilities:
Architectedthe design
ImplementedandVerifiedRTLusingVerilogHDL
Synthesizedthe design.
 SPI CONTROLLER CORE - VERIFICATION
HVL : SystemVerilog
TB Methodology : UVM
EDA Tools : Questasim
Description: The SPI IP core provides serial communication capabilities with external device of variable
length of transfer word. This core can be configured to connect with 32 slaves.
Responsibilities:
Architected the class based verification environment in UVM
Verified the RTL module using System Verilog
Generated functional and code coverage for the RTL verification sign-off

3. ACADEMIC PROJECT:
 TITLE: A PARKING GUIDANCE AND INFORMATION SYSTEM BASED ON WIRELESS SENSOR
NETWORK
Duration : 3 Months kit used: 8051 micro controller kit
Description: Our aim of in this project is we can control the parking system through our PC by receiving parking slot
status from zigbee protocol communication. Here we place IR sensors, whenever vehicle present/leave IR activated
means slot full others wise slot empty.
TITLE: DESIGN AND IMPLEMENTATION OF PPA IN TERMS OF SPEED PERFORMANCE WITH
OPTIMIZED AREA, POWER AND DELAY
Duration : 8 Months
Software Used : Xilinx ISE 13.2
Description: In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay
performance. This paper investigates four types of PPA’s (Kogge Stone Adder (KSA), Spanning Tree Adder (STA),
Brent Kung Adder (BKA) and Sparse Kogge Stone Adder (SKA)). Additionally Ripple Carry Adder (RCA), Carry
Look ahead Adder (CLA) and Carry Skip Adder (CSA) are also investigated. Out of these kogge stone adder and
Brent kung adder has the better delay performance.
STRENGTHS:
 Quick Learner & Innovative Thinking.
 Problem Solving & Programming Skills.
 Ability to work as an individual & in a team.
 Good communication skills.
 Honest, Sincere and Humble.
 Adaptive to unfavorable situations
SPORTS & ACADEMIC ACHIEVEMENTS:
 I Participated Two day workshop on “FPGA Programming” in SVCET College.
 Participated in Kabaddi & won the cup & Cash prize in Vemu Institute Of Technology in 2013
 Participated in cricket & we got Runners in Zonal Level competition in Chittoor District in 2014.
 Submitted Technical paper on FPGA to SV-University Tirupathi. In 2014.
PERSONAL DETAILS:
Date of Birth : 04.06.1992
Passport No : M1074064
Nationality : Indian
Gender : Male
Linguistics : English, Tamil, Telugu,Hindi
Permanent Address : Ravi D, S/o Dorai Swamy G,
D.No: 3-27, Perumakuppam Village,
Yadhamari (Mandal), Chittoor (dist), A.P,517422
Hobbies : Playing and watching cricket, football and volleyball.
Keen to learn new technologies in fieldof VLSI.
DECLARATION:
I hereby declare that the above-mentioned information is correct up to my knowledge and I
Bear the responsibility for the correctness of the above-mentioned particulars.
Date:
Place: Bangalore (Ravi D)