Sanjay Kumar is seeking a position as a verification engineer to utilize his 4+ years of experience in verification of hardware modules. He has experience developing reusable verification environments in SystemVerilog and using the UVM methodology. He has worked on verifying IP blocks including DDR4, Ethernet, audio codecs, and imaging subsystem blocks. His skills include SystemVerilog, UVM, code and functional coverage, assertion-based verification, and using EDA tools from companies like Cadence, Synopsys, and Mentor Graphics. He has a Bachelor's degree in Electronics and Communication Engineering.

1. Sanjay Kumar
#53, Chandana Nilaya
7th
main, Hosapalya
Bangalore
Karnataka, India –560068 Email:Snjygreen12@gmail.com
Mobile: +919620251542
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Career Objective
Seeking a position to utilize my skills and abilities in the Industry, which I have developed in
providing quality solutions, which are requirement focused. At the same time I would like to update
my knowledge base, which would further help me in being more productive.
Summary
• Possess 4+years of Experience in Verification of Hardware Modules
• Design and development of re-usable verification environments(HVL based)
• Strong Knowledge of System Verilog, UVM Verification Methodology
• Good knowledge in creating verification components(Interface and Module UVCs)
• Knowledge of DDR4,ETHERNET,IDP,AHB,APB Protocol
• Knowledge of System verilog Assertions.
• Knowledge of Functional/Code coverage
• Mentoring the junior level engineers
• Knowledge of RTL verification/Gate Level Verification
• Knowledge on Co- Sim and Functional Vectors Generations ( ATE VECTORS)
• Knowledge on different levels of verification(Unit level, Subsystem level and System level)
• Knowlegde of Synthesis and STA
• Experience in using industry standard EDA tools for the front-end design and verification
Education:
Bachelor of Engineering, BTL institute of Technology,Bangalore
Visveswaraiah Technological University ,Karnataka, India
Discipline: Electronics & Communication Engineering
Percentage: 72% First Class with Distinction
Year: June 2011
Technical Skills:
HDLs Verilog,VHDL
HVLs System Verilog,
Methodology UVM,LUA
Development Tools Xilinx-ISE
Simulation Tools Cadence ( NCSIM,Vmanager) ,Mentor (QUESTA SIM, MODEL SIM)
,Synopsys (VCS, VERDI)
Bus Protocols DDR4,Ethernet,AHB,APB,IDP
Programming Language C,C++ ,OOPS concepts
Scripting Shell,Tcl
Operating System Linux and Windows
Version Control SVN

2. Professional Experience:
Feb 15 – On going Graphene Semiconductors Pvt Ltd, Bangalore
Designation MTS – Verification Engineer
Project I Verification of DDR4 RCD/DB Block – Gen II
Client Rambus Chip technologies India Pvt Ltd
Description The project involves development of IP level and System Level Verification
environment in SV- UVM methodology
 Creation of Verification Plan.
 Features Extraction and Coverage / TC identifications
 Development of Verification Environment and Stabilizing the same
 Development of UVC and BFM’s.
 Coding of SVA and checkers
 Development of Algorithm for DDR4 trainings ( Write Eye /Write
levelling / Host Write levelling / Read gate / Read Eye trainings )
 Gate level Simulation / Co-Simulation and closure
 Development of tests. Simulation and debugging.
 Regression & functional / Code coverage closure
 Development test vectors ( ATE) for power measurement and system checks
July 14 – Jan 15 Graphene Semiconductors Pvt Ltd, Bangalore
Designation MTS – Verification Engineer
Project II Verification of DDR4 RCD/DB Block – Gen I
Client Rambus Chip technologies India Pvt Ltd
Description The project involves development of IP level and System Level Verification
environment in SV- UVM methodology
 Creation of Verification Plan.
 Features Extraction and Coverage / TC identifications
 Development of Verification Environment and Stabilizing the same
 Development of UVC and BFM’s.
 Coding of SVA and checkers
 Development of Algorithm for DDR4 trainings
 Gate level Simulation / Co-Simulation and closure
 Development of tests. Simulation and debugging.
 Regression & functional / Code coverage closure
 Development test vectors ( ATE) for power measurement and system checks
Apr 14 – July 14 Sankalp & Kpit Semiconductors Pvt Ltd, Bangalore
Designation Design Engineer
Project III Verification of (Mixed signal block) – Audio Codec
Client Texas instruments India Pvt Ltd
Description The project involves development of IP level verification environment in SV
(Mixed signal verification )
 Creation of Verification Plan.
 Triggering the Analog Blocks for Digital updates.
 Development of Verification Environment
 Development of tests. Simulation and debugging.
 Regression & functional/Code coverage closure

3. Jan 14 – June 14 Sankalp & Kpit Semiconductors Pvt Ltd ,Bangalore
Designation Design Engineer
Project IV Verification of 1GBPS Ethernet MAC
Client Renesas UK
Description The project involves development of IP level verification environment in SV
UVM Environment
 Creation of Verification Plan.
 Development of Verification Environment
 Development of tests. Simulation and debugging.
 Regression & functional coverage closure.
Jun13 – Dec13 Sankalp & Kpit Semiconductors Pvt Ltd ,Bangalore
Designation Design Engineer
Project VI Verification of IP's and Video Stabilization Subsytem
Client KPIT Automotives India
Description The project involves IP & Sub System Level Verification in SV UVM
Environment
 Creation of Verification Plan.
 Development of Verification Environment
 Development of tests. Simulation and debugging.
 Regression & functional coverage closure.
 Verification of Video Stabilization Subsystem
Oct-12 – May 13 Sankalp & Kpit Semiconductors Pvt Ltd, Bangalore
Designation Design Engineer
Project VII Verification of IP and Subsytem for Imaging Soc
Client ST Microelectronics Pvt Ltd France ( Grenoble) / India
Description The project involves IP & Sub System Level Verification in SV UVM
Environment
 Creation of Verification Plan.
 Development of tests. Simulation and debugging.
 Writing Cover groups for IP'S
 Complete Verification of ISP Subsystem
 Verification of Subsystem and handling 72 instance of 24 IP’s spilt into 7
Engines.
 Supporting SOC verification team and helping them to identify scenario
for ISP subsystem.
 Regression & functional coverage closure of IP's

4. Aug12 – Sep 12 Sankalp & Kpit Cummins infosystems Ltd, Bangalore
Designation Design Engineer
Project IX Post layout STA of Pallazoa Subsystem
Client PMC Sierra India
Description The project involves meeting the timing requirements using Post Layout STA of
Subsystem
 Generating the Scripts and SDC required to perform STA
 Analysis of STA reports and informing Design Team
Academic Project:
Project I Intelligent Energy Hacking Street lights
Description This project involves the movement of Solar panels installed on Street lights
according to intensity of sunlight and storing accumulated energy and
utilizing effectively using IR sensors
Team Size 3
Ownership Architect, Design and Coding
Coding Language C, Assembly
Duration Jan 2011- May 2011
Hobbies:
Playing Football,Chess
Listening to Music
Dancing
Surfing
Travelling
Personal Profile:
Name: SANJAY KUMAR
Father name: Kari Gowda G
Date of Birth: 26-12-90
Gender: male
Marital Status: Unmarried
Languages Known: English,Kannada,Telugu and Hindi
Nationality: Indian
Permanent Address: #53, Chandana nilaya
7th
main Hosapalya
Bangalore
Karnataka, India 560068
E-mail: snjygreen12@gmail.com
Contact number: 9620251542
Declarations:
I here by declare that the information provided is true to the best of my knowledge.
Date:
Place: Bangalore Sanjay Kumar