Syed Maqsood Ali is seeking a position as a Design Verification Engineer. He has over 3 years of experience in verifying ASIC designs using SystemVerilog, UVM, and gate-level simulation. His experience includes verifying IPs such as LDO voltage regulators, USBPHY 2.0, AXI, DDRPHY, Ethernet, and switches. He is currently working on a project called Europa for Imagination Technologies.

1. Syed Maqsood Ali
H.No:6-1-74, Bhagya Laxmi Colony Email: sdmaqsood@gmail.com
Manikonda, RR District, Hyderabad-89 Mobile: +91-7411769223
Career Objective
With hands on experience in verification of integrated circuits and in developing scripts, looking
for a responsible position as a Design Verification Engineer with a view to utilize and
enhance my skills and expertise as a member of an organization.
Profile
• Working as an ASIC Verification Engineer in Test and Verification Solutions Pvt Ltd
from October 2015 till date.
• 3.4 years of experience in verification of ASIC designs.
• Experience in SV-UVM verification, Gate-level Simulation and XA-VCS co-simulation
(mixed signal simulation).
• Proficient in developing environment, test-cases, Systemverilog Assertions (SVA).
• Knowledge of Test planning and Coverage Analysis.
• Experience in writing scripts using Perl.
• Experience in verification of IPs like LDO voltage regulator, USBPHY2.0, AXI,
DDRPHY, Ethernet, and Switch.
Technical Skills
• HDL : Verilog
• HVL : Systemverilog
• Scripting : Perl, Shell
• EDA Tools : Synopsys VCS
• Programming Language : C, C++
Projects
1. Project : Europa for Imagination Technologies, Hyderabad
Environment : Systemverilog, UVM
Duration : October 2015 to Present
Responsibility :
• Running test cases for different modes of operations.
• Writing coverage, execution and debug.
2. Project : LDO Voltage Regulator for AMD Bangalore
Environment : XA-VCS Co-simulation, Perl Script, Systemverilog, UVM, VCS
Duration : March 2015 to August 2015
Responsibility :

2. • Setting up co-simulation environment for the LDO netlist.
• Writing test cases, checkers, execution and debug.
3. Project : DDRPHY for AMD Bangalore
Environment : Perl Script, System Verilog, VCS
Duration : August 2014 to February 2015.
Responsibility :
• Scripts for automation of jobs.
• Debugging of the SV-OVM environment.
4. Project : USBPHY 2.0 for AMD Bangalore
Environment : Systemverilog, UVM, VCS.
Duration : November 2013 to May 2014.
Responsibility :
• Development of tests, simulation and debug.
• Development of Systemverilog Assertion based protocol checkers.
• Gate level Simulation setup and debug.
• XA-VCS co-simulation.
5. Project : AMBA AXI Verification IP
Environment : Systemverilog, UVM, Cadence ncsim
Duration : May 2013 to July 2013.
Responsibility :
• Development of UVM based verification components drivers, monitor sand
sequencers for AXI Slave.
• Development of configurable verification environment.
• Development of tests. Simulation and debug.
• Development of Systemverilog assertion based protocol checkers.
6. Project : Ethernet
Environment : Systemverilog, UVM, Cadence ncsim
Duration : January 2013 to March 2013.
Responsibility :
• Creation of Verification plan.
• Development of verification environment.
• Development of tests. Simulation and debug.
• Development of checkers for the signal transitions using Systemverilog
assertions.
• Functional and code coverage.
Academic Qualifications
• B.E in Electronics and Communication Engineering from Muffakham Jah College of
Engineering and Technology (Affiliated to Osmania University) with 87% in the year
2012