In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information – a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs.

1. PRESENTATION ON FLIP-FLOP
Course Code: EEE-3309
Course Tittle: VLSI Circuits
Group:05
North Western University, Khulna
Submitted By:
Name: SABUJ SAHA
ID:20172027021
Name: MD.SHOHANUR RAHMAN
ID:20172028021
Name: NASRIN JAHAN
ID:20172029021
Name: DEBBROTA KUMAR GHUHA
ID:20172030021
Name: MST. HABIBA YASMIN
ID:20172035021
3 rd Year, 3rd Semester (Spring- 2020)
Submitted To:
Name: PRIYANKAR BISWAS
Lecturer of Electrical & Electronics
Engineering Department
North Western University, Khulna
Date of Submission: 20-08-2020

2. FLIP-FLOP

3. Contents
 introduction
 Types of flip-flop
 The Used of flip-flop
 Conclusion
 References.

4. INTRODUCTION
What is Flip-Flop
 In digital circuits, the flip-flop, is a kind of bi-
stable multivibrator.
 It is a Sequential Circuits / an electronic circuit
which has two stable states and thereby is capable
of serving as one bit of memory , bit 1 or bit 0

5. Types Of Flip Flop
There are basically four different types of flip flops and these are:
1. Set-Reset (SR) flip-flop or Latch
2. JK flip-flop
3. D (Data or Delay) flip-flop
4. T (Toggle) flip-flop
1. SR Flip Flop (Latch)
a. SR Flip Flop Active Low = NAND gates
b. SR Flip Flop Active High = NOR gates
c. SR AND –OR latch
2. JK flip-flop (Latch)
a. JK latch
5. Clocked SR Flip Flop
6. Master-Slave Edge-Triggered Flip-Flop

6. Set-Reset flip flop

7. JK Flip Flop
The JK Flip Flop is the most widely used flip flop. It is
considered to be a universal flip-flop circuit. The
sequential operation of the JK Flip Flop is same as for the
RS flip-flop with the same SET and RESET input. The
difference is that the JK Flip Flop does not the invalid
input states of the RS Latch (when S and R are both
1).The JK Flip Flop name has been kept on the inventor
name of the circuit known as Jack Kilby. The
basic symbol of the JK Flip Flop is shown below

8. D Flip Flop

9. We can design the T flip – flop by making simple
modifications to the JK flip – flop. The T flip – flop is
a single input device and hence by connecting J and
K inputs together and giving them with single input
called T we can convert a JK flip – flop into T flip –
flop. So a T flip – flop is sometimes called as single
input JK flip – flop.
The logic symbol of T flip – flop is shown below. It
has one Toggle input (T) & one clock signal input
(CLK).
T Flip Flop

10. T Flip Flop
We can construct a T flip – flop by connecting AND gates as
input to the NOR gate SR latch. And these AND gate inputs are
fed back with the present state output Q and its complement Q’
to each AND gate. A toggle input (T) is connected in common
to both the AND gates as an input. The AND gates are also
connected with common Clock (CLK) signal. In the T flip –
flop, a pulse train of narrow triggers are provided as input (T)
which will cause the change in output state of flip – flop. So
these flip – flops are also called Toggle flip – flops. The circuit
diagram of a T flip – flop constructed from SR latch is shown
below.
T flip – flop is an edge triggered device i.e. the low to high or
high to low transitions on a clock signal of narrow triggers that
is provided as input will cause the change in output state of flip
– flop.

11. Clocked SR Flip Flop
A simple clocked SR flipflop built from AND-gates in front of a
basic SR flipflop with NOR-gates.
Obviously, the values at the R and S inputs are gated with
the clock signal C. Therefore, as long as the C signal stays at 0
value, the flipflop stores its value. On the other hand, the
flipflop behaves like the standard SR flipflop while C is 1.
Because the behavior is controlled by the static level of the
clock signal, such flipflops are called level-sensitive or latches.
(Implementation note: in order to avoid flipflop oscillations due
to the discrete-event based simulation model when the
'forbidden' input values (111) are selected, the gate-delays of the
first-level AND gates are set to different values. Due to this
choice, the reset state is preferred. The real flipflop would enter
a random state based on the current operating parameters like
temperature, etc. )

12. SR Flip Flop - NAND GATE LATCH
The circuit shown below is a basic NAND latch. The inputs are
generally designated S and R for Set and Reset respectively.
Because the NAND inputs must normally be logic 1 to avoid
affecting the latching action, the inputs are considered to be
inverted in this circuit (or active low).
The circuit uses feedback to "remember" and retain its logical
state even after the controlling input signals have changed.
When the S and R inputs are both high, feedback maintains the
Q outputs to the previous state.

13. SR Flip Flop - NOR GATE LATCH
While the R and S inputs are both
low, feedback maintains the Q and Q outputs in a constant
state, with Q the complement of Q. If S (Set) is pulsed
high while R (Reset) is held low, then the Q output is
forced high, and stays high when S returns to low;
similarly, if R is pulsed high while S is held low, then the
Q output is forced low, and stays low when R returns to
low.

14. SR AND-ORlatch
From a teaching point of view, SR latches
drawn as a pair of cross-coupled components
(transistors, gates, tubes, etc.) are often hard to
understand for beginners. A didactically easier
to understand way is to draw the latch as a
single feedback loop instead of the cross-
coupling. The following is an SR latch built
with an AND gate with one inverted input and
an OR gate. Note that the inverter is not needed
for the latch functionality, but rather to make
both inputs High-active.

15. JKlatch
The JK latch is much less frequently used than the JK flip-flop. The JK latch follows the following state table:
Hence, the JK latch is an SR latch that is made to toggle its output (oscillate between 0 and 1) when passed the
input combination of 11.Unlike the JK flip-flop, the 11 input combination for the JK latch is not very useful
because there is no clock that directs toggling.

16. Master-Slave Edge-Triggered Flip-Flop
The flipflop circuits discussed above are level-triggered,
i.e., the circuit is always active when the clock signal is
high, and consequently unpredictable output may result.
For example, during this active clock period, the output of
a T-FF may toggle continuously. The output at the end of
the active period is therefore unpredictable. To overcome
this problem, edge-triggered circuits can be used whose
output is determined by the edge, instead of the level, of
the clock signal, for example, the rising (or trailing) edge.

17. The Used of Flip Flop
 For Memory circuits
 For Logic Control Devices
 For Counter Devices
 For Register Devices

18. ConclusioN
1.Flip-flops can be used as a memory element and also as a delay element.
2.Flip-flops are also used in the making of counter/timers.
3.Using Flip-flops,We can eliminate keyboard debounce.
4.In various type of registers also we use flip-flops.

19. References
1. https://en.wikipedia.org/wiki/Flip-flop_(electronics)
2. www.slideshare.net
3. https://www.electronicshub.org/t-flip-flop/
4. http://fourier.eng.hmc.edu/e85_old/lectures/digital_logi
c/node17.html

20. THANK YOU