B sc3 unit 5 sequencial lc

KUD BSc 3rd SEM : ELECTRONICS : OPTO AND DIGITAL ELECTRONICS
BY : MAHIBOOB ALI K MULLA MSc , Mphil.
Asst.Prof.in electronics , SSGFG COLLEGE NARAGUND

E3 UNIT-5:OPTO&DIGITAL
SEQUENTIAL LOGIC CIRCUITS

Sequential Logic Circuits:
Sequential Logic Circuits use flip-flops as memory elements
and in which their output is dependent on the input state

SR Flip-Flop: The SR flip-flop, also known as a SR Latch, can be considered as
one of the most basic sequential logic circuit possible. This simple flip-flop is
basically a one-bit memory bistable device that has two inputs, one which will
“SET” the device (meaning the output = “1”), and is labelled S and one which
will “RESET” the device (meaning the output = “0”), labelled R.
Then the SR description stands for “Set-Reset”. The reset input resets the flip-
flop back to its original state with an output Q that will be either at a logic level
“1” or logic “0” depending upon this set/reset condition.
A basic NAND gate SR flip-flop circuit provides feedback from both of its
outputs back to its opposing inputs and is commonly used in memory circuits
to store a single data bit. Then the SR flip-flop actually has three inputs, Set,
Reset and its current output Q relating to it’s current state or history. The term
“Flip-flop” relates to the actual operation of the device, as it can be “flipped”
into one logic Set state or “flopped” back into the opposing logic Reset state.

Latches in Digital Logic : Latches are basic storage
elements that operate with signal levels (rather than
signal transitions). Latches controlled by a clock
transition are flip-flops. Latches are level-sensitive
devices. Latches are useful for the design of the
asynchronous sequential circuit.
SR (Set-Reset) Latch – SR Latch is a circuit with:
(i) 2 cross-coupled NOR gate or 2 cross-coupled NAND
gate.
(ii) 2 input S for SET and R for RESET.
(iii) 2 output Q, Q’.

RS-LATCH: A bistable multivibrator has two stable states, as
indicated by the prefix bi in its name. Typically, one state is referred
to as set and the other as reset. The simplest bistable device,
therefore, is known as a set-reset, or S-R, latch
S-R, latch

Types of Triggering
Following are the two possible types of triggering that are used in
sequential circuits.
Level triggering
Edge triggering
Level triggering
There are two levels, namely logic High and logic Low in clock signal.
Following are the two types of level triggering.
Positive level triggering
Negative level triggering
If the sequential circuit is operated with the clock signal when it is in
Logic High, then that type of triggering is known as Positive level
triggering. It is highlighted in below figure.

If the sequential circuit is operated with the clock signal when it is in
Logic Low, then that type of triggering is known as Negative level
triggering. It is highlighted in the following figure.
Edge triggering
There are two types of transitions that occur in clock signal. That
means, the clock signal transitions either from Logic Low to Logic High
or Logic High to Logic Low.

Following are the two types of edge triggering based on the
transitions of clock signal.
Positive edge triggering
Negative edge triggering
If the sequential circuit is operated with the clock signal that is
transitioning from Logic Low to Logic High, then that type of triggering
is known as Positive edge triggering. It is also called as rising edge
triggering. It is shown in the following figure.

If the sequential circuit is operated with the clock signal that is
transitioning from Logic High to Logic Low, then that type of triggering
is known as Negative edge triggering. It is also called as falling edge
triggering. It is shown in the following figure.
In coming chapters, we will discuss about various sequential circuits
based on the type of triggering that can be used in it.
Latches operate with enable signal, which is level sensitive.
Whereas, flip-flops are edge sensitive.

SR NAND latch : When using static gates as building blocks, the most
fundamental latch is the simple SR latch, where S and R stand for set
and reset. It can be constructed from a pair of cross-coupled NOR or
NAND logic gates. The stored bit is present on the output marked Q.
The circuit shown below is a basic NAND latch. The inputs are
generally designated S and R for Set and Reset respectively. Because
the NAND inputs must normally be logic 1 to avoid affecting the
latching action, the inputs are considered to be inverted in this
circuit (or active low).
The circuit uses feedback to "remember" and retain its logical state
even after the controlling input signals have changed. When the S
and R inputs are both high, feedback maintains the Q outputs to the
previous state.

SR Latch: SR Latch is also called as Set Reset Latch. This
latch affects the outputs as long as the enable, E is maintained
at ‘1’. The circuit diagram of SR Latch is shown in the following
figure.

This circuit has two inputs S & R and two outputs Qt & Qt’. The upper NOR gate
has two inputs R & complement of present state, Qt’ and produces next state,
Qt+1 when enable, E is ‘1’.
Similarly, the lower NOR gate has two inputs S & present state, Qt and produces
complement of next state, Qt+1’ when enable, E is ‘1’.
We know that a 2-input NOR gate produces an output, which is the complement
of another input when one of the input is ‘0’. Similarly, it produces ‘0’ output,
when one of the input is ‘1’.
If S = 1, then next state Qt+1 will be equal to ‘1’ irrespective of present state, Qt
values.
If R = 1, then next state Qt+1 will be equal to ‘0’ irrespective of present state, Qt
values.
At any time, only of those two inputs should be ‘1’. If both inputs are ‘1’, then
the next state Qt+1 value is undefined.
The following table shows the state table of SR latch.

The following table shows the state table of SR latch.
S R Qt+1
0 0 Qt (NC)
0 1 0 RESET
1 0 1 SET
1 1 - INHIBIT
Therefore, SR Latch performs three types of functions such as
Hold, Set & Reset based on the input conditions.

While the R and S inputs are both low, feedback maintains the Q and
Q outputs in a constant state, with Q the complement of Q. If S (Set) is
pulsed high while R (Reset) is held low, then the Q output is forced
high, and stays high when S returns to low; similarly, if R is pulsed high
while S is held low, then the Q output is forced low, and stays low
when R returns to low.
The R = S = 1 combination is called a restricted combination or a
forbidden state because, as both NOR gates then output zeros, it
breaks the logical equation Q = not Q. The combination is also
inappropriate in circuits where both inputs may go low
simultaneously (i.e. a transition from restricted to keep). The output
would lock at either 1 or 0 depending on the propagation time
relations between the gates (a race condition).

The circuit shown below is a basic NAND latch. The
inputs are generally designated S and R for Set and
Reset respectively. Because the NAND inputs must
normally be logic 1 to avoid affecting the latching
action, the inputs are considered to be inverted in this
circuit (or active low).
The circuit uses feedback to "remember" and retain its
logical state even after the controlling input signals have
changed. When the S and R inputs are both high,
feedback maintains the Q outputs to the previous state.

Latches are the basic building blocks of flip-flops. We can implement
flip-flops in two methods.
In first method, cascade two latches in such a way that the first latch is
enabled for every positive clock pulse and second latch is enabled for
every negative clock pulse. So that the combination of these two
latches become a flip-flop.
In second method, we can directly implement the flip-flop, which is
edge sensitive. In this chapter, let us discuss the following flip-flops
using second method.
SR Flip-Flop , D Flip-Flop , JK Flip-Flop , T Flip-Flop
SR Flip-Flop : SR flip-flop operates with only positive clock transitions
or negative clock transitions. Whereas, SR latch operates with enable
signal. The circuit diagram of SR-FF is shown in the following figure.

This circuit has two inputs S & R and two outputs Qt & Qt’. The
operation of SR flip flop is similar to SR Latch. But, this flip-flop
affects the outputs only when positive transition of the clock signal is
applied instead of active enable.

The following table shows the state table of SR flip-flop.
S R Qt+1
0 0 Qt
0 1 0
1 0 1
1 1 -
Here, Qt & Qt+1 are present state & next state respectively.
So, SR flip-flop can be used for one of these three functions
such as Hold, Reset & Set based on the input conditions,
when positive transition of clock signal is applied. The
following table shows the characteristic table of SR flip-flop.

Present Inputs Present State Next State
S R Qt Qt+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 x
1 1 1 x
By using three variable K-Map, we can get the simplified expression
for next state, Qt+1. The three variable K-Map for next state, Qt+1 is
shown in the following figure.

The maximum possible groupings of adjacent ones are already shown in the
figure. Therefore, the simplified expression for next state Qt+1 is
Q(t+1)=S+R′Q(t)
D Flip-Flop :
D flip-flop operates with only positive clock transitions or negative clock
transitions. Whereas, D latch operates with enable signal. That means, the
output of D flip-flop is insensitive to the changes in the input, D except for
active transition of the clock signal. The circuit diagram of D flip-flop is shown
in the following figure.

This circuit has single input D and two outputs Qt & Qt’. The operation of D flip-
flop is similar to D Latch. But, this flip-flop affects the outputs only when
positive transition of the clock signal is applied instead of active enable.
The following table shows the state table of D flip-flop.
D Qt + 1t + 1
0 0
1 1

Therefore, D flip-flop always Hold the information, which is available
on data input, D of earlier positive transition of clock signal. From the
above state table, we can directly write the next state equation as
Qt+1 = D
Next state of D flip-flop is always equal to data input, D for every
positive transition of the clock signal. Hence, D flip-flops can be used
in registers, shift registers and some of the counters.
Ripple Through: Fig. a possible problem with the level triggered D
type flip-flop; if there are changes in the data during period when the
clock pulse is at its high level, the logic state at Q changes in
sympathy with D, and only ‘remembers’ the last input state that
occurred during the clock pulse, (period RT in Fig.).

This effect is called ‘Ripple Through’, and although this allows the level
triggered D Type flip-flop to be used as a data switch, only allowing
data through from D to Q as long as CK is held at logic 1, this may not
be a desirable property in many types of circuit.

JK Flip-Flop: JK flip-flop is the modified version of SR flip-flop. It
operates with only positive clock transitions or negative clock
transitions. The circuit diagram of JK flip-flop is shown in the
following figure.

This circuit has two inputs J & K and two outputs Qt & Qt’. The operation of JK
flip-flop is similar to SR flip-flop. Here, we considered the inputs of SR flip-flop as
S = J Qt’ and R = KQt in order to utilize the modified SR flip-flop for 4
combinations of inputs.
The following table shows the state table of JK flip-flop.
J K Qt+1
0 0 Qt
0 1 0
1 0 1
1 1 Qt'
Here, Qt & Qt+1 are present state & next state respectively. So, JK flip-flop can
be used for one of these four functions such as Hold, Reset, Set & Complement
of present state based on the input conditions, when positive transition of clock
signal is applied. The following table shows the characteristic table of JK flip-
flop.

Present Inputs Present State Next State
J K Qt Qt+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
By using three variable K-Map, we can get the simplified expression
for next state, Qt+1. Three variable K-Map for next state, Qt+1 is
shown in the following figure.

The maximum possible groupings of adjacent ones are already
shown in the figure. Therefore, the simplified expression for next
state Qt+1 is
Q(t+1)=JQ(t)′+K′Q(t)

T Flip-Flop: T flip-flop is the simplified version of JK flip-flop. It is
obtained by connecting the same input ‘T’ to both inputs of JK flip-
flop. It operates with only positive clock transitions or negative clock
transitions. The circuit diagram of T flip-flop is shown in the following
figure.

This circuit has single input T and two outputs Qt & Qt’. The operation of T flip-
flop is same as that of JK flip-flop. Here, we considered the inputs of JK flip-flop
as J = T and K = T in order to utilize the modified JK flip-flop for 2 combinations
of inputs. So, we eliminated the other two combinations of J & K, for which
those two values are complement to each other in T flip-flop.
The following table shows the state table of T flip-flop.
D Qt+1
0 Qt
1 Qt’
Here, Qt & Qt+1 are present state & next state respectively. So, T flip-flop can
be used for one of these two functions such as Hold, & Complement of present
state based on the input conditions, when positive transition of clock signal is
applied. The following table shows the characteristic table of T flip-flop.

Input Present State Next State
T Qt Qt+1
0 0 0
0 1 1
1 0 1
1 1 0
From the above characteristic table, we can directly write the next state
equation as
Q(t+1)=T′Q(t)+TQ(t)′
⇒Q(t+1)=T⊕Q(t)
The output of T flip-flop always toggles for every positive transition of the clock
signal, when input T remains at logic High 1. Hence, T flip-flop can be used in
counters. In this chapter, we implemented various flip-flops by providing the
cross coupling between NOR gates. Similarly, you can implement these flip-
flops by using NAND gates.

Master Slave JK Flip Flop: Master slave JK FF is a cascade of two S-R FF
with feedback from the output of second to input of first. Master is a
positive level triggered. But due to the presence of the inverter in the
clock line, the slave will respond to the negative level. Hence when
the clock = 1 (positive level) the master is active and the slave is
inactive. Whereas when clock = 0 (low level) the slave is active and
master is inactive.
Circuit Diagram

Operation
S.N. Condition Operation
1 J = K = 0 (No change)
When clock = 0, the slave becomes active and master is inactive. But since the S
and R inputs have not changed, the slave outputs will also remain unchanged.
Therefore outputs will not change if J = K =0.
2 J = 0 and K = 1 (Reset)
Clock = 1 − Master active, slave inactive. Therefore outputs of the master
become Q1 = 0 and Q1 bar = 1. That means S = 0 and R =1.
Clock = 0 − Slave active, master inactive. Therefore outputs of the slave become
Q = 0 and Q bar = 1. Again clock = 1 − Master active, slave inactive. Therefore
even with the changed outputs Q = 0 and Q bar = 1 fed back to master, its
output will be Q1 = 0 and Q1 bar = 1. That means S = 0 and R = 1. Hence with
clock = 0 and slave becoming active the outputs of slave will remain Q = 0 and Q
bar = 1. Thus we get a stable output from the Master slave.

3 J = 1 and K = 0 (Set)
Clock = 1 − Master active, slave inactive. Therefore outputs of the master
become Q1 = 1 and Q1 bar = 0. That means S = 1 and R =0.
Clock = 0 − Slave active, master inactive. Therefore outputs of the slave become
Q = 1 and Q bar = 0.
Again clock = 1 − then it can be shown that the outputs of the slave are
stabilized to Q = 1 and Q bar = 0.
4 J = K = 1 (Toggle)
Clock = 1 − Master active, slave inactive. Outputs of master will toggle. So S and
R also will be inverted.
Clock = 0 − Slave active, master inactive. Outputs of slave will toggle.
These changed output are returned back to the master inputs. But since clock =
0, the master is still inactive. So it does not respond to these changed outputs.
This avoids the multiple toggling which leads to the race around condition. The
master slave flip flop will avoid the race around condition.

Timing Diagram of a Master flip flop –
When the Clock pulse is high the output of master is high and remains
high till the clock is low because the state is stored.

Now the output of master becomes low when the clock pulse
becomes high again and remains low until the clock becomes high
again. Thus toggling takes place for a clock cycle.
When the clock pulse is high, the master is operational but not the
slave thus the output of the slave remains low till the clock remains
high.
When the clock is low, the slave becomes operational and remains
high until the clock again becomes low.
Toggling takes place during the whole process since the output is
changing once in a cycle.
This makes the Master-Slave J-K flip flop a Synchronous device as it
only passes data with the timing of the clock signal.

Sometimes one need to RESET or SET the flip-flop instantly and by
using the
synchronized inputs it is not possible as they are dependent of clock
pulse. Most integrated circuit flip-flops have asynchronous inputs.
Asynchronous inputs are the one which changes the flip-flop output
immediately without even bothering about the clock pulse, so these
inputs affect the state of the flip-flop independent of the clock. They
are labeled as PRESET
(PR) and CLEAR (CLR) in many digital systems. An active PRESET will
SET the flip-flop and an active CLEAR will reset the flip-flop
irrespective of the clock input. Figure 16 shows the D flip-flop where
both inputs are included.

Figure : Circuit diagram of D flip-flop with asynchronous inputs
The circuit diagram of D flip-flop is exactly the same as given in figure
6 except the inclusion of two OR gates with PRESET and CLEAR
inputs. It can be clearly verified that a high PRESET will set the flip-
flop and forces the output Q=1 and high CLEAR will reset the flip-flop
which forces the output Q=0 irrespective of the clock input or even
the data input. Figure shows the logic symbol of D flip-flop with
PRESET and CLEAR inputs when active high and figure shows the
logic symbol of D flip-flop with PRESET and CLEAR
inputs when active low. An active low level at the PRESET input will
SET the flip-flop and active low level at the CLEAR input will reset it.

Digital Registers : Flip-flop is a 1 bit memory cell which can be used
for storing the digital data. To increase the storage capacity in terms of
number of bits, we have to use a group of flip-flop. Such a group of
flip-flop is known as a Register. The n-bit register will consist of n
number of flip-flop and it is capable of storing an n-bit word.
The binary data in a register can be moved within the register from
one flip-flop to another. The registers that allow such data transfers
are called as shift registers. There are four mode of operations of a
Shift register. Serial Input Serial Output , Serial Input Parallel Output
Parallel Input Serial Output , Parallel Input Parallel Output
1.Serial Input Serial Output:
Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1
= Q0 = 0. If an entry of a four bit binary number 1 1 1 1 is made into

the register, this number should be applied to Din bit with the LSB bit
applied first. The D input of FF-3 i.e. D3 is connected to serial data
input Din. Output of FF-3 i.e. Q3 is connected to the input of the next
flip-flop i.e. D2 and so on.
Block Diagram

Operation : Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000
and apply LSB bit of the number to be entered to Din. So Din = D3 = 1.
Apply the clock. On the first falling edge of clock, the FF-3 is set, and
stored word in the register is Q3 Q2 Q1 Q0 = 1000.

Apply the next bit to Din. So Din = 1. As soon as the next negative edge
of the clock hits, FF-2 will set and the stored word change to Q3 Q2 Q1
Q0 = 1100.

Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As
soon as the third negative clock edge hits, FF-1 will be set and output
will be modified to Q3 Q2 Q1 Q0 = 1110.

Similarly with Din = 1 and with the fourth negative clock edge
arriving, the stored word in the register is Q3 Q2 Q1 Q0 = 1111.

2.Serial Input Parallel Output
In such types of operations, the data is entered serially and
taken out in parallel fashion.
Data is loaded bit by bit. The outputs are disabled as long as
the data is loading.
As soon as the data loading gets completed, all the flip-flops
contain their required data, the outputs are enabled so that
all the loaded data is made available over all the output lines
at the same time.
4 clock cycles are required to load a four bit word. Hence the
speed of operation of SIPO mode is same as that of SISO
mode.

3.Parallel Input Serial Output (PISO)
Data bits are entered in parallel fashion.
The circuit shown below is a four bit parallel input serial output
register.
Output of previous Flip Flop is connected to the input of the next one
via a combinational circuit.The binary input word B0, B1, B2, B3 is
applied though the same can work namely - shift mode or load mode.
Load mode
When the shift/load bar line is low (0), the AND gate 2, 4 and 6
become active they will pass B1, B2, B3 bits to the corresponding flip-
flops.

On the low going edge of clock, the binary input B0, B1,
B2, B3 will get loaded into the corresponding flip-flops.
Thus parallel loading takes place.
Shift mode
When the shift/load bar line is low (1), the AND gate 2, 4
and 6 become inactive. Hence the parallel loading of the
data becomes impossible. But the AND gate 1,3 and 5
become active. Therefore the shifting of data from left
to right bit by bit on application of clock pulses. Thus the
parallel in serial out operation takes place.

4.Parallel Input Parallel Output (PIPO): In this mode, the 4 bit binary input B0,
B1, B2, B3 is applied to the data inputs D0, D1, D2, D3 respectively of the four
flip-flops. As soon as a negative clock edge is applied, the input binary bits will be
loaded into the flip-flops simultaneously. The loaded bits will appear
simultaneously to the output side. Only clock pulse is essential to load all the
bits. Block Diagram

Bidirectional Shift Register: If a binary number is shifted left by one
position then it is equivalent to multiplying the original number by
2. Similarly if a binary number is shifted right by one position then it
is equivalent to dividing the original number by 2.
Hence if we want to use the shift register to multiply and divide the
given binary number, then we should be able to move the data in
either left or right direction.
Such a register is called bi-directional register. A four bit bi-
directional shift register is shown in fig.
There are two serial inputs namely the serial right shift data input
DR, and the serial left shift data input DL along with a mode select
input (M).

Operation
S.N. Condition Operation
1 With M = 1 − Shift right operation
If M = 1, then the AND gates 1, 3, 5 and 7 are enabled whereas the
remaining AND gates 2, 4, 6 and 8 will be disabled.
The data at DR is shifted to right bit by bit from FF-3 to FF-0 on the
application of clock pulses. Thus with M = 1 we get the serial right
shift operation.
2 With M = 0 − Shift left operation
When the mode control M is connected to 0 then the AND gates 2,
4, 6 and 8 are enabled while 1, 3, 5 and 7 are disabled.
The data at DL is shifted left bit by bit from FF-0 to FF-3 on the application of
clock pulses. Thus with M = 0 we get the serial right shift operation.

Following are the applications of shift registers.
Shift register is used as Parallel to serial converter, which converts
the parallel data into serial data. It is utilized at the transmitter
section after Analog to Digital Converter ADC block.
Shift register is used as Serial to parallel converter, which converts
the serial data into parallel data. It is utilized at the receiver section
before Digital to Analog Converter DAC block.
Shift register along with some additional gates generate the
sequence of zeros and ones. Hence, it is used as sequence generator.
Shift registers are also used as counters. There are two types of
counters based on the type of output from right most D flip-flop is
connected to the serial input. Those are Ring counter and Johnson
Ring counter.

Ring Counter: In previous chapter, we discussed the operation
of Serial In - Parallel Out SIPO shift register. It accepts the data
from outside in serial form and it requires ‘N’ clock pulses in
order to shift ‘N’ bit data.
Similarly, ‘N’ bit Ring counter performs the similar operation.
But, the only difference is that the output of rightmost D flip-
flop is given as input of leftmost D flip-flop instead of applying
data from outside. Therefore, Ring counter produces a
sequence of states pattern of zeros and ones and it repeats for
every ‘N’ clock cycles.
The block diagram of 3-bit Ring counter is shown in the
following figure.

Timing diagram of Ring Counter
The timing diagram of the Ring counter will explain that the clock signal
changes the output of every stage of the counter, so that CLK signal will help
the data to circulate from one flip flop to another.

The 3-bit Ring counter contains only a 3-bit SIPO shift register. The
output of rightmost D flip-flop is connected to serial input of left most
D flip-flop.
Assume, initial status of the D flip-flops from leftmost to rightmost is
Q2Q1Q0=001. Here, Q2 & Q0 are MSB & LSB respectively. We can
understand the working of Ring counter from the following table.

The initial status of the D flip-flops in the absence of clock signal is
Q2Q1Q0=001. This status repeats for every three positive edge
transitions of clock signal. Therefore, the following operations take
place for every positive edge of clock signal.Serial input of first D flip-
flop gets the previous output of third flip-flop. So, the present output
of first D flip-flop is equal to the previous output of third flip-flop. The
previous outputs of first and second D flip-flops are right shifted by
one bit. That means, the present outputs of second and third D flip-
flops are equal to the previous outputs of first and second D flip-
flops.
Johnson Ring Counter: The operation of Johnson Ring counter is
similar to that of Ring counter. But, the only difference is that the
complemented output of rightmost D flip-flop is given as input of
leftmost D flip-flop instead of normal output.

Therefore, ‘N’ bit Johnson Ring counter produces a sequence of states
pattern of zeros and ones and it repeats for every ‘2N’ clock cycles.
Johnson Ring counter is also called as Twisted Ring counter and
switch tail Ring counter. The block diagram of 3-bit Johnson Ring
counter is shown in the following figure.

The 3-bit Johnson Ring counter also contains only a 3-
bit SIPO shift register. The complemented output of
rightmost D flip-flop is connected to serial input of left
most D flip-flop.
Assume, initially all the D flip-flops are cleared. So,
Q2Q1Q0=000. Here, Q2 & Q0 are MSB & LSB
respectively. We can understand the working of
Johnson Ring counter from the following table.

The initial status of the D flip-flops in the absence of clock signal is
Q2Q1Q0=000. This status repeats for every six positive edge
transitions of clock signal.
Therefore, the following operations take place for every positive
edge of clock signal.
Serial input of first D flip-flop gets the previous complemented
output of third flip-flop. So, the present output of first D flip-flop is
equal to the previous complemented output of third flip-flop.
The previous outputs of first and second D flip-flops are right
shifted by one bit. That means, the present outputs of second and
third D flip-flops are equal to the previous outputs of first and
second D flip-flops.

Timing diagram of johnson counter
The timing diagram of the johnson counter will explain that the clock signal
changes the output of every stage of the counter, so that CLK signal will help
the data to circulate from one flip flop to another.

Applications of Ring counters
Ring counters are used to count the data in a continuous loop.
They are also used to detect the various numbers values or various patterns
within a set of information, by connecting AND & OR logic gates to the ring
counter circuits.
2 stage, 3 stage and 4 stage ring counters are used in frequency divider circuits
as divide by 2 and divide by 3 and divide by 4 circuits, respectively.
The 3 stage Johnson counter is used as a 3 phase square wave generator which
produces 1200 phase shift.
The 5 stage Johnson counter circuit is generally used as synchronous decade
(BCD) counter and also as divider circuit.
The 2 stage Johnson counters are also known as “Quadrature oscillator” which
is used to produce 4 level individual outputs which are out of phase with 900
with each other. This quadrature generator is used to produce 4 phase timing
signal.

Synchronous Counters:
If all the flip-flops receive the same clock signal, then that
counter is called as Synchronous counter. Hence, the outputs
of all flip-flops change affect at the same time.
Now, let us discuss the following two counters one by one.
Synchronous Binary up counter
Synchronous Binary down counter
Synchronous Binary Up Counter
An ‘N’ bit Synchronous binary up counter consists of ‘N’ T flip-
flops. It counts from 0 to 2𝑁 − 1. The block diagram of 3-bit

Synchronous binary up counter is shown in the following figure.

The 3-bit Synchronous binary up counter contains three T
flip-flops & one 2-input AND gate. All these flip-flops are
negative edge triggered and the outputs of flip-flops change
affect synchronously. The T inputs of first, second and third
flip-flops are 1, Q0 & Q1Q0 respectively.
The output of first T flip-flop toggles for every negative edge
of clock signal. The output of second T flip-flop toggles for
every negative edge of clock signal if Q0 is 1. The output of
third T flip-flop toggles for every negative edge of clock signal
if both Q0 & Q1 are 1.

Synchronous Binary Down Counter:
An ‘N’ bit Synchronous binary down counter consists of ‘N’ T flip-
flops. It counts from 2˄𝑁 − 1 to 0. The block diagram of 3-bit
Synchronous binary down counter is shown in the following figure.

The 3-bit Synchronous binary down counter contains three
T flip-flops & one 2-input AND gate. All these flip-flops are
negative edge triggered and the outputs of flip-flops change
affect synchronously. The T inputs of first, second and third
flip-flops are 1, Q0′ &' Q1′Q0′ respectively.
The output of first T flip-flop toggles for every negative edge
of clock signal. The output of second T flip-flop toggles for
every negative edge of clock signal if Q0′ is 1. The output of
third T flip-flop toggles for every negative edge of clock
signal if both Q1′ & Q0′ are 1.

Bidirectional Counter
Both Synchronous and Asynchronous counters are capable of
counting “Up” or counting “Down”, but their is another more
“Universal” type of counter that can count in both directions
either Up or Down depending on the state of their input
control pin and these are known as Bidirectional Counters.
Bidirectional counters, also known as Up/Down counters, are
capable of counting in either direction through any given
count sequence and they can be reversed at any point within
their count sequence by using an additional control input as
shown below.
Synchronous 3-bit Up/Down Counter

Synchronous 3-bit Up/Down Counter

The circuit above is of a simple 3-bit Up/Down synchronous counter using JK
flip-flops configured to operate as toggle or T-type flip-flops giving a maximum
count of zero (000) to seven (111) and back to zero again. Then the 3-Bit
counter advances upward in sequence (0,1,2,3,4,5,6,7) or downwards in
reverse sequence (7,6,5,4,3,2,1,0).Generally most bidirectional counter chips
can be made to change their count direction either up or down at any point
within their counting sequence. This is achieved by using an additional input
pin which determines the direction of the count, either Up or Down and the
timing diagram gives an example of the counters operation as this Up/Down
input changes state.Nowadays, both up and down counters are incorporated
into single IC that is fully programmable to count in both an “Up” and a
“Down” direction from any preset value producing a complete Bidirectional
Counter chip. Common chips available are the 74HC190 4-bit BCD decade
Up/Down counter, the 74F569 is a fully synchronous Up/Down binary counter
and the CMOS 4029 4-bit Synchronous Up/Down counter.

APLICATIONS OF SYNCHRONOUS COUNTERS :
Alarm Clock, Set AC Timer, Set time in camera to take the picture, flashing
light indicator in automobiles, car parking control etc.
Counting the time allotted for special process or event by the scheduler.
The UP/DOWN counter can be used as a self-reversing counter.
It is also used as clock divider circuit.
The parallel load feature can be used to preset the counter for some initial
count.
Commons used in home appliances like washing machine, microwave own,
Time schedule led indicator, key board controller etc.
They are also used in machine moving control.
Mostly used in digital clocks and multiplexing circuits.
They are used to generate saw-tooth waveform (Stair case voltage)
It is also used in digital to analog converters.

Asynchronous Counters:
Asynchronous counters are those whose output is free from the clock signal.
Because the flip flops in asynchronous counters are supplied with different
clock signals, there may be delay in producing output.
The required number of logic gates to design asynchronous counters is very
less. So they are simple in design. Another name for Asynchronous counters is
“Ripple counters”.
The number of flip flops used in a ripple counter is depends up on the number
of states of counter (ex: Mod 4, Mod 2 etc). The number of output states of
counter is called “Modulus” or “MOD” of the counter. The maximum number of
states that a counter can have is 2n where n represents the number of flip flops
used in counter.
For example, if we have 2 flip flops, the maximum number of outputs of the
counter is 4 i.e. 22. So it is called as “MOD-4 counter” or “Modulus 4 counter”.

What is clock ripple?
The sum of time delay of individual clock pulses, that drive the circuit is
called “Clock ripple”. The below figure explains how the logic gates will
create propagation delay, in each flip flop.
The propagation delays of logic gates are represented by blue lines. Each of
them will add to the delay of next flip flop and the sum of all these
individual flip flops is known as the propagation delay of circuit.
As the outputs of all flip-flops change at different time intervals and for
every different inputs at clock signal, a new value occurs at output each
time. For example, at clock pulse 8, the output should change from 11102
(710) to 00012 (810), in some time delay of 400 to 700 ns (Nano Seconds).
For clock pulses other than 8, the sequence will change.
Although this problem prevents the circuit being used as a reliable counter,
it is still valuable as a simple and effective frequency divider, where a high
frequency oscillator provides the input and each flip-flop in the chain
divides the frequency by two. This is all about clock ripple.

Different types of Asynchronous counters
4 bit synchronous UP counter
4 bit synchronous DOWN counter
4 bit synchronous UP / DOWN counter
Asynchronous 3-bit binery ripple counter (Using JK FF )

In the circuit shown in above figure, Q0(LSB) will toggle for every clock
pulse because JK flip-flop works in toggle mode when both J and K are
applied 1, 1 or high input. The following counter will toggle when the
previous one changes from 1 to 0
Truth Table –

The 3-bit ripple counter used in the circuit above has eight different
states, each one of which represents a count value. Similarly, a counter
having n flip-flops can have a maximum of 2 to the power n states. The
number of states that a counter owns is known as its mod (modulo)
number. Hence a 3-bit counter is a mod-8 counter.
A mod-n counter may also be described as a divide-by-n counter. This is
because the most significant flip-flop (the furthest flip-flop from the
original clock pulse) produces one pulse for every n pulses at the clock
input of the least significant flip-flop (the one triggers by the clock
pulse). Thus, the above counter is an example of a divide-by-4 counter.
Timing diagram – Let us assume that the clock is negative edge triggered
so above counter will act as an up counter because the clock is negative
edge triggered and output is taken from Q.

Counters are used very frequently to divide clock frequencies and
their uses mainly involve in digital clocks and in multiplexing. The
widely known example of the counter is parallel to serial data
conversion logic.

3- Bits Asynchronous up-down counter: As we know that in the up-counter
each flip-flop is triggered by the normal output of the preceding flip-flop (from
output Q of first flip-flop to clock of next flip-flop); whereas in a down-counter,
each flip-flop is triggered by the complement output of the preceding flip-flop
(from output Q^ of first flip-flop to clock of next flip-flop).

The operation of such a counter is controlled by the up-down control
input. Now question is in which sequence it will count see below the
table for the counting sequence of the it in the two modes of
counting.

As I discussed earlier that for up down counting operation
preceding flip-flop sometime it need input from output from output
Q of first flip-flop to clock of next flip-flop for up-counting and
sometimes from output Q^ of first flip-flop to clock of next flip-flop
for down-counting. So in above circuit diagram it is shown clearly.
As we know a flip-flop can hold single bit so for 3 bit operation it
need three flip-flops. An inverter has been inserted in between the
count-up control line and the count-down control line to ensure
that the count-up and count-down cannot be simultaneously in the
HIGH state.
When the count-up/down line is held HIGH, the lower AND gates
will be disabled and their outputs will be zero. So they will not
affect the outputs of the OR gates. At the same time the

upper AND gates will be enabled. Hence, QA will pass through
the OR gate and into the clock input of the B flip-flop.
Similarly, QB will be gated into the clock input of the C flip-
flop. Thus, as the input pulses are applied, it will count up and
follow a natural binary counting sequence from 000 to 111.
Similarly, with count-up/down line being logic 0, the upper
AND gates will become disabled and the lower AND gates are
enabled, allowing Q′A and Q′B to pass through the clock
inputs of the following flip-flops. Hence, in this condition the
counter will count in down mode, as the input pulses are
applied.

3 bit asynchronous Down counter

Modified asynchronous counters
Modulo 16 asynchronous counter can be modified using additional
logic gates and can be used in a way that the output will give a decade
(divided by 10) counter output, which is useful in counting standard
decimal numbers or in arithmetic circuits. This type of counters called as
Decade Counters.
BCD or Decade Counter Circuit
A binary coded decimal (BCD) is a serial digital counter that counts
ten digits .And it resets for every new clock input. As it can go through
10 unique combinations of output, it is also called as “Decade
counter”. A BCD counter can count 0000, 0001, 0010, 1000, 1001,
1010, 1011, 1110, 1111, 0000, and 0001 and so on.

A 4 bit binary counter will act as decade counter by skipping any six
outputs out of the 16 (24) outputs. There are some available ICs for
decade counters which we can readily use in our circuit, like 74LS90. It
is an asynchronous decade counter.

The above figure shows a decade counter constructed with JK flip flop. The J
output and K outputs are connected to logic 1. The clock input of every flip flop
is connected to the output of next flip flop, except the last one.
The output of the NAND gate is connected in parallel to the clear input ‘CLR’ to
all the flip flops. This ripple counter can count up to 16 i.e. 24.
Decade Counter Operation
When the Decade counter is at REST, the count is equal to 0000. This is first
stage of the counter cycle. When we connect a clock signal input to the counter
circuit, then the circuit will count the binary sequence. The first clock pulse can
make the circuit to count up to 9 (1001). The next clock pulse advances to count
10 (1010).
Then the ports X1 and X3 will be high. As we know that for high inputs, the
NAND gate output will be low. The NAND gate output is connected to clear
input, so it resets all the flip flop stages in decade counter. This means the pulse
after count 9 will again start the count from count 0.

The above table describes the counting operation of Decade counter.
It represents the count of circuit for decimal count of input pulses.
The NAND gate output is zero when the count reaches 10 (1010).
The count is decoded by the inputs of NAND gate X1 and X3. After
count 10, the logic gate NAND will trigger its output from 1 to 0, and it
resets all flip flops.
The state diagram of Decade counter is given below.
The count starts from 0000 (zero) to 1001 (9) and then the NAND gate will reset the circuit.

A Modulo-5 Counter: Suppose we want to design a MOD-5 counter, how could
we do that. First we know that “m = 5”, so 2n must be greater than 5. As 2˄1 = 2,
22 = 4, 23 = 8, and 8 is greater than 5, then we need a counter with three flip-
flops (N = 3) giving us a natural count of 000 to 111 in binary (0 to 7 decimal).
Taking the MOD-8 counter above, the truth table for the natural count is given as:
MOD-8 Counter and Truth Table

As we are constructing a MOD-5 counter, we want the counter to
reset back to zero after a count of 5. However, we can see from the
attached truth table that the count of six gives us the output
condition of: QA = 0, QB = 1, and QC = 1.
We can decode this output state of 110 (6) to give us a signal to clear
(Clr) the counter back to zero with the help of a 3-input AND gate (TTL
74LS11) and an inverter or NOT gate, (TTL 74LS04).
The inputs of the combinational logic
circuit of the inverter and AND gate are
connected to QA, QB, and QC respectively
with the output of the AND gate at logic
level “0” (LOW) for any combinations of
the input other than the one we want.

In binary code, the output sequence count will look like
this: 000, 001, 010, 011, 100, 101. But when it reaches
the state of 110 (6), the combinational logic circuit will
detect this 110 state and produce an output at logic
level “1” (HIGH).
We can then use the resulting HIGH output from the
AND gate to reset the counter back to zero after its
output of 5 (decimal) count giving us the required MOD-
5 counter. When the output from the combinational
circuit is LOW it has no effect on the counting sequence.

Then we can use combinational logic decoding circuits around a basic
counter, either synchronous or asynchronous to produce any type of MOD
Counter we require as each of the counters unique output states can be
decoded to reset the counter at the desired count.
In our simple example above, we have used a 3-input AND gate to decode
the 110 state, but the first time that QB and QC are both at logic 1 is is when
the count reaches six, so a 2-input AND gate connected to QB and QC could
be used without the complication of the third input and the inverter.
However, one of the disadvantages of using asynchronous counters for
producing a MOD counter of a desired count is that undesired effects called
“glitches” can occur when the counter reaches its reset condition. During this
brief time the outputs of the counter may take on an incorrect value, so it is
sometimes better to use synchronous counters as modulo-m counters as all
the flip-flops are clocked by the same clock signal so change state at the
same time.

Modulus 10 Counter: A good example of a modulo-m counter circuit
which uses external combinational circuits to produce a counter with a
modulus of 10 is the Decade Counter. Decade (divide-by-10) counters such as
the TTL 74LS90, have 10 states in its counting sequence making it suitable for
human interfacing where a digital display is required.
The decade counter has four outputs producing a 4-bit binary number and by
using external AND and OR gates we can detect the occurrence of the 9th
counting state to reset the counter back to zero. As with other mod counters, it
receives an input clock pulse, one by one, and counts up from 0 to 9
repeatedly.
Once it reaches the count 9 (1001 in binary), the counter goes back to 0000
instead of continuing on to 1010. The basic circuit of a decade counter can be
made from JK flip-flops (TTL 74LS73) that switch state on the negative trailing-
edge of the clock signal as shown.

Advantages: It can be easily designed by D-flip flop or T-flip flop.
It can be used in low speed circuits.
It is used as Divide by-n counters.
They are also used as Truncated counters. (to design any mod number
counters, i.e. Mod 4, Mod 3).
Disadvantages: For Re synchronization, extra flip flop are needed.
Additional feedback logic is needed to count the sequence of
truncated counters (keep in mind that mod is not equal to 2n).
The propagation delay of asynchronous counters is very large, while
counting large number of bits.
Due to propagation delay, counting errors may occur for high clock
frequencies.
They are slower as compared to synchronous counters.

Applications of Asynchronous Counters:
They are used as frequency dividers, as divide by “N” counters.
They are used for low noise emission and low power applications
They are used in designing asynchronous decade counter.
It is also used in Ring counter and Johnson counter.
Asynchronous counters are used in Mod N ripple counters. i.e. Mod
3, Mod 4, Mod 8, Mod 14, Mod 10 etc.
THANK YOU

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