This paper analyzes the reliability of MOSFETs that use indium-tin oxide as the gate oxide instead of silicon dioxide. Interface trap charges at the oxide-silicon interface can degrade MOSFET performance by changing the threshold voltage over time. The paper finds that MOSFETs using indium-tin oxide exhibit improved immunity to the effects of interface trap charges compared to those using silicon dioxide. Specifically, indium-tin oxide MOSFETs show enhanced static, linearity, and intermodulation performance metrics when subjected to both positive and negative interface trap charges. Thus, indium-tin oxide has potential to improve MOSFET reliability by reducing sensitivity to interface trap charge effects.

1. Presentation 1
Prof. MM TRIPATHI
and Mr. Ajay Kumar
Presented by:
HARSHIT SONI
Prof. MM TRIPATHI and Mr. Ajay Kumar
Presentation 1

2. Categories of Materials
2

3. Semiconductors
3
• While there are numerous semiconductor
materials available, by far the most popular
material is Silicon.
• GaAs, InP and SiGe are compound
semiconductors that are used in specialized
devices.
• The success of a semiconductor material depends
on how easy it is to process and how well it allows
reliable high-volume fabrication.

4. BASIC SEMICONDUCTOR THEORY
• HOW ENERGY BAND MODEL IS CREATED?
FIG 1
because of influence of electrons and nucleus of same atom
different energy is experienced by a group of electrons,
difference between them is so close that they appear as a
band normally and that’s why concept of energy band
came into picture
. Smaller the band gap, better is the conductivity of material.

5. USUALLY SEMICONDUCTORS ARE DEFINED AS
ELEMENTS WHOSE SPECIFIC CONDUCTIVITY LIES IN THE
RANGE OF 104 to 10-6 Ωm
 SILICON AND GERMANIUM ARE THE MOST USED
SEMICONDUCTORS BECAUSE OTHER COMPONENTS OF
GROUP, Pb AND Sn HAVE MORE METTALIC PROPERTIES
AND CARBON BEHAVES AS AN INSULATOR.
IN SI AND GE, SI IS MOSTLY USED BECAUSE:
• ABUNDANCE OF SILICON
• LOWER LEAKAGE CURRENT IN SILICON
FROBIDDEN GAP: GAP BETWEEN VALENCE BAND AND
CONDUCTION BAND AS SEEN IN FIG1

6. ABOUT SILICON:
4 VALENCE ELECTRONS, SP1 ORBITALS, TETRAHEDRAL
SHAPE, DIAMOND CUBIC CHRYSTAL STRUCTURE
• SEMICONDUCTORS CAN BE CLASSIFIED AS INTRINSIC
AND EXTRINSIC SEMICONDUCTORS
INTRISIC: BEHAVES AS INSULATOR AT 0K, BEHAVES AS
CONDUCTOR AT HIGH TEMP.
 FERMI LEVEL: LOCATION WHERE P(FINDING AN
OCCUPIED STATE)= 0.5
GIVEN BY F(E)= 1/{1+e(E-E
F
)/KT} ; as TEMPERATURE
INCREASES PROBABILITY OF FINDING AN ELECTRON
ABOVE FERMILEVEL INCREASES,

7. EXTRINSIC SEMICONDUCTOR: HERE DOPING IS
DONE IN SILICON SUBSTRATE , COMMON DOPANTS
ARE: B, P, AS
B-> ACCEPTOR ATOM : P TYPE
P, AS-> DONOR ATOMS : N TYPE
ACCEPTOR IMPURITY REDUCES THE ENERGY OF
VALENCE BAND
DONOR IMPURITY INCREASES THE ENERGY OF
CONDUCTION BAND.

8. GENERATION AND RECOMBINATION
GENERATION: ELECTRONS AND HOLES ARE
GENERATED BY GIVING ENERGY TO THE SYSTEM,
(OPTICAL OR ELECTRICAL)
RECOMBINATION: ELECTRONS AND HOLES ARE
ANNIHILATED AND CURRENT IS OBSERVED
TO INCREASE THE CONDUCTIVITY OF
SEMICONDUCTOR INDIRECT RECOMBINATION IS
EMPLOYED!
INDIRECT RECOMBINATION: GOLD IS USED AS A DEEP
LEVEL IMPURITY IN SI TO INCREASE
RECOMBINATION RATE AND TO INCREASE THE
CONDUCTIVITY OF SEMICONDUCTOR.

9. ELECTRICAL CONDUCTION CAN BE CLASSIFIED AS
DRIFT AND DIFFUSION,
DRIFT: BECAUSE OF ELECTRIC FIELD
DIFFUSION: BECAUSE OF CONCENTRATION GRADIENT
WE SHULD ALWAYS CONSIDER A FACT THAT MOBLITY
OF ELECTRONS IS ALWAYS HIGHER THAN THAT OF
HOLES THUS SEMICONDUCTORS HAVING MAJORTIY
CHARGE CARRIER AS ELECTRONS IS BETTER THAN
THAT OF HOLES IF CONDUCTIVITY IS THE REFRENCE.

10. AS ELECTRONS ACQUIRE ENERGY FROM ELECTRIC
FIELD AND THEN IT STARTS DRIFTING , BUT IF
ENERGY ACQUIRED IS MORE THAN ENERGY
SCATTERED THIS CAN LEAD TO IMPACT IONIZATION.

11. PN JUNCTION: 2 SEMICONDUCTORS P AND N TYPE ARE
MERGED USING EPITEXIAL TECHNOLOGY, PROVIDING A
DIFFERENT RESPONSE OF VOLTAGE WITH RESPECT TO
CURRENT
A SPACE CHARGE REGION IS FORMED IN A DIODE, WHERE
ONLY IONS AND COVALENT BOND EXISTS RESULTING IN
A BUILT IN POTENTIAL ACROSS THE JUNCTION, (Vbi)
Vbi = Vt ln[NAND/Ni
2]
i.e. Vbi IS STRONGLY DEPENDENT ON TEMPERATURE AND
DOPING CONCENTRAION.
HERE, Vt= KT/q;
K-> BOLTZAMAN CONSTANT
T-> TEMPERATURE
q-> CHARGE
• Vbi CANNOT BE MEASURED DIRECTLY
BY APPPLYING VOLTMETER!

12. DEPLETION WIDTH OF A PN JUNCTION DIODE ALSO
PLAYS AN IMPORTANT ROLE,
DEPLETION WIDTH HIGHLY DEPENDS ON DOPING
CONCENTRATION AND Vbi, ALSO DEPLETION
REGION EXPANDS MORE TO THE SIDE LESS DOPED
IN COMPARISION TO HEAVILY DOPED SIDE.
DIODE CURRENT CAN BE PROVIDED BY THE
FOLLOWING RELATION:
Id= Is[eVd/ῃvt -1] where ῃ is the utility factor.
ῃ =1, recombination current dominates,
ῃ=2, diffusion current dominates.

13. RESISTANCE OF A DIODE CAN BE ADDRESSED AS A
COMBINATION OF CONTACT RESISTANCE AND
INTERNAL RESISTANCE, AND CUMULATIVELY IT IS
REFFERRED AS A BULK RESISTANCE.
JUNCTION BREAKDOWN CAN BE BECAUSE OF:1
IMPACT IONIZATIONAVALANCHE BREAKDOWN
TUNNELLING EFFECTZENER BREAKDOWN

14. STORED CHARGES IN A DIODE CAN BE IN THE SPACE
CHARGE REGION AND IN THE BELT OTHER THAN
THE SPACE CHARGE REGION AND ARE DENOTED BY
Qdepletion, Qdiffusion respectively.
Giving rise to capacitances: Cdepletion, Cdiffusion
And NOW WE CAN COCLUDE THAT IN A SIMPLE PN
JUNCTION , COMMONLY KNOWN AS DIODE Vbi, CJ, IS
HIGHLY DEPENDS ON TEMPERATURE AND HENCE
THEIR PROPERTIES VARY AS TEMPERATURE IS
VARIED.

15. MOSFET Symbol Circuit

16. Schematic structure of MOSFET

17. MOSFET(METAL OXIDE SEMICONDUCTOR FIELD EFECT TRANSISTOR)
• MOSFET IS A 4 TERMINAL
DEVICE[DRAIN,SOURCE,GATE,SUBSTRATE]
• SOURCE AND DRAIN TO SUBSTRATE PN
JUNCTION ARE ALWAYS REVERESE BIASSED,

18. DRAIN AND SOURCE ARE DIRECTLY CONNENCTED TO
SUBSTRATE WHILE GATE IS INSULATED FROM
SUBSTRATE THROUGH A LAYER OF SILICON OXIDE.
WORKING OF MOSFET:
AS WE APPLY VG (+VE) TO NMOS, ELECTRONS ARE
ATTRACTED FROM THE SUBSTRATE AND PN
JUNCTIONS NEAR GATE LAYER, FORMING A
CHANNEL, WHICH WILL BE USED FOR FUTURE
CONDUCTION WHEN DRAIN VOLTAGE IS APPLIED.
HERE CHANNEL WIDTH IS DIRECTLY PROPORTIONAL
TO GATE VOLTAGE APPLIED!

19. AND CONDUCTIVITY WILL BE DIRECTLY
PROPORTIONAL TO CHANEEL WIDTH!
THRESHOLD VOLTAGE IS THE MINIMUM VOLTAGE
REQUIRED FOR THE INVERSION OF CHANNEL.
HENCE WE CAN CONCLUDE THAT MOSFET IS A GATE
VOLTAGE CONTROLLED SWITHING DEVICE,
MOSFET CAN BE CLASSIFIED AS:

20. OPERATION OF MOSFET IS DEALT AS:
LINEAR REGION(TRIODE)
SATURATION REGION
BREAKDOWN REGION
IN LINEAR REGION, CURRENT VARIES AS
Id= ʯn Cox (W/L)[VGS-Vth-0.5VDS]VDS
IN SATURATION REGION, CURRENT VARIES AS:
ID= ʯn Cox (W/2L)[VGS-Vth]2
IN BREAKDOWN REGION, HOT CARRIER EFFECT
HAPPENS DUE TO HIGH ELECTRIC FIELD AT DRAIN
END.

30. MOSFET
Fabrication

31. Lithography
• An IC consists of several
layers of material that are
manufactured in
successive steps.
• Lithography is used to
selectively process the
layers, where the 2-D
mask geometry is copied
on the surface.
3
1

32. Lithography
• The surface of the wafer is coated with a
photosensitive material, the photoresist. The mask
pattern is developed on the photoresist, with UV
light exposure.
• Depending on the type of the photoresist (negative or
positive), the exposed or unexposed parts of the
photoresist change their property and become resistant
to certain types of solvents.
• Subsequent processing steps remove the undeveloped
photoresist from the wafer. The developed pattern
(usually) protects the underlying layer from an etching
process.
• The photoresist is removed after patterning on the lower
layer is completed.

33. Etching
Once the desired shape is
patterned with
photoresist, the
unprotected areas are
etched away, using wet
or dry etch techniques
Etching patterns are
shown with the
ideal(desired) pattern:

34. Fabrication Process Flow:
Basic Steps
3
4
The simplified process sequence for the fabrication of
integrated circuits on a n-type silicon substrate is shown as :
Selecting single chrystal n type silicon wafer
Introducing SiO2 by heating wafer in presence of oxygen
Photolithography
Etching
Diffusion of n+ regions for source and drain
Oxidation
Metallization

35. Fabrication Process Flow:
Basic Steps
1
0
photolithography
oxidation

36. Fabrication Process Flow:
Basic Steps
JET
3
Softening of oxides by
UV light

37. Fabrication Process Flow:
Basic Steps
3
E
T
C
H
I
N
G

38. Fabrication
of n- MOS
Transistor
MR. HIMANSHU JET
3
P TYPE
P TYPE
P TYPE

39. Fabrication of n-MOS
Transistor
MR. HIMANSHU JET
3

40. Fabrication of n-MOS
Transistor
4
• Polysilicon is used both as gate electrode material for MOS
transistors and also as an interconnect medium in silicon
integrated circuits. Undoped polysilicon has relatively high
resistivity.
• The-resistivity of polysilicon can be reduced, however, by
doping it with impurity atoms.
• After deposition, the polysilicon layer is patterned and etched to
form the interconnects and the MOS transistor gates .
• The thin gate oxide not covered by polysilicon is also etched
away, which exposes the bare silicon surface on which the
source and drain junctions are to be formed

41. Fabrication of n-MOS
Transistor
MR. HIMANSHU JET
4
• The entire silicon surface is then doped with a
high concentration of impurities, either through
diffusion or ion implantation (in this case with
donor atoms to produce n-type doping).
• The doping penetrates the exposed areas on the
silicon surface, ultimately creating two n-type
regions (source and drain junctions) in the p-type
substrate.

42. Fabrication of n-MOS
Transistor
MR. HIMANSHU JET
4
OXIDATION

43. Fabrication
of n-
MOS
Transistor
MR. HIMANSHU JET
2
0
ION
IMPLANTATION
METALLIZATION

44. Fabrication of n-MOS
Transistor
4
P TYPE

45. Fabrication of NMOS
n-MOS
MR. HIMANSHU JET
4

46. Paper 1
SiO2 layer is used as an electrical isolation between the
gate and the channel through which major conduction
will take place. Its function is to avoid direct charge flow
from the gate to the channel and vice-versa. The gate
potential causes charge build up at the bottom of the
SiO2 layer thereby aiding in turning ON of the device.
But there are interface trap charges introduced in SiO2
which are responsible for undesirable change in Vth and
to avoid this different oxides are tested to avoid this
problem of trap charges and on the other hand to
enhance the basic properties of MOSFEt.

47. In this paper, reliability issues of In2O5Sn(indium–tin oxide) MOSFET
has been analyzed by considering the effect of interface trap charges
(both positive and negative) present at the Si/SiO2 interface. Device
characteristics are studied in terms of static, linearity, and
intermodulation figure of merits. It is found that with the amalgamation
of the indium tin oxide on conventional recesses channel
(CRC)MOSFET,
it exhibits improved immunity against interface trap charges in
comparison to CRC-MOSFET. This paper demonstrates that TGRC
MOSFET can act as a promising candidate for low-power linear analog
applications, where low temperature is required.