MCP2515: Stand-Alone CAN Controller
•
5 likes•2,661 views
The document provides an overview of the MCP2515 stand-alone CAN controller, including its features such as three transmit buffers, two receive buffers, and six 29-bit filters. It also outlines the target applications for the controller and describes its basic architecture, layers of the CAN protocol, message frames, bit timing, and operating modes. The controller implements the CAN 2.0B standard at 1 Mb/s and interfaces with a microcontroller through a high-speed SPI interface.
![MCP2515: Stand-Alone CAN Controller ,[object Object]](https://image.slidesharecdn.com/microchipmcp2515stand-alonecancontroller-110314213040-phpapp02/85/MCP2515-Stand-Alone-CAN-Controller-1-320.jpg)
![Introduction ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
More Related Content
What's hot
What's hot (20)
Similar to MCP2515: Stand-Alone CAN Controller
Similar to MCP2515: Stand-Alone CAN Controller (20)
More from Premier Farnell
More from Premier Farnell (20)
Recently uploaded
Recently uploaded (20)
MCP2515: Stand-Alone CAN Controller
- 8. CAN Buffers And Protocol Engine Block Diagram
- 12. Receive Buffer Block Diagram
Editor's Notes
- Welcome to the training module on MCP2515 Stand-alone CAN controller. In this training module, we will discuss the basic features, layers, operation and applications of this device.
- CAN stands for Controller Area Network. Microchip Technology’s MCP2515 is a stand-alone CAN controller that implements the CAN specification, version 2.0B. It is capable of transmitting and receiving both standard & extended data as well as remote frames. The MCP2515 has 2 acceptance masks and 6 acceptance filters that are used to filter out unwanted messages, thereby reducing the host MCU’s overhead. This device interfaces with microcontrollers via an industry standard Serial Peripheral Interface or SPI for short.
- CAN is being designed into a wide range of applications that use command and control networks. Some of these applications include: industrial control, maritime electronics, avionics & aerospace electronics, UPS’s, heavy machinery and earth moving equipment. Others include: factory automation, medical equipment, exercise equipment, elevator control and automotives just to mention a few. The CAN serial bus protocol is a high-speed, reliable communication protocol for applications requiring robust communications at bit rates reaching 1 Mbps
- This is the block diagram of the CAN controller. The CAN module handles all functions for receiving and transmitting messages on the CAN bus. Messages are transmitted by first loading the appropriate message buffer and control registers. Transmission is initiated by using control register-bits via the SPI interface or by using the transmit-enable pins. The control logic block, controls the setup and operation of the MCP2515 by interfacing to the other blocks in order to pass information and control. Interrupt pins are provided, to allow greater system flexibility. The MCU interfaces to the device via the SPI interface. Writing to, and reading from all registers is accomplished using standard SPI read & write commands, in addition to specialized SPI commands.
- Connectivity within a vehicle is dominated today by two main network protocols: CAN or Controller Area Network is one and the other is LIN or Local Interconnect Network. CAN utilizes a robust, high-speed protocol, usually linking major nodes or subsystems within the vehicle, such as ABS, airbag, power-train and suspension control modules. LIN is a low speed, single-wire network, that usually links nodes within a vehicle’s subsystem, such as body electronics, headlight controls and occupant detection.
- Most network applications follow a layered approach to system implementation. As a result a standard was created. This standard is known as the ISO Open Systems Interconnection or OSI Network Layering Reference Model. The CAN protocol itself, implements most of the lower two layers of this reference model. This enabled system designers to adapt and optimize the communication protocol on multiple media for maximum flexibility.
- The MCP2515 has three transmit and two receive buffers, two acceptance masks; one for each receive buffer, and a total of 6 acceptance filters. The heart of the engine is the Finite State Machine or FSM. The FSM is a sequencer that controls the sequential data stream between the Tx Rx shift register, the CRC register and the bus line. The FSM also controls the Error Management Logic or EML and the parallel data stream between the Tx Rx shift registers and the buffers. The Cyclic Redundancy Check or CRC register generates the Cyclic Redundancy Check code, which is transmitted after either the Control Field or the Data Field, and is used to check the CRC field of incoming messages.
- The MCP2515 supports standard data frames, extended data frames and remote frames), as defined in the CAN 2.0B specification. A message in the standard format begins with the start bit ”start of frame”. This is followed by the ”arbitration field”, which contains the identifier and the ”RTR” or remote transmission request-bit, which indicates whether it is a data frame or a request frame without any data bytes. The ”control field” contains the IDE or identifier extension-bit, which indicates either standard format or extended format. The ”data field” ranges from 0 to 8 bytes in length and is followed by the ”CRC field”, which is used as a frame security check for detecting bit-errors. The ”ACK field”, comprises the ACK slot (1 bit) and the ACK de-limiter.
- In the extended CAN data frame, the SOF bit is followed by the arbitration field, which consists of 32 bits. The first 11 bits are the Most Significant bits of the 29-bit identifier. These 11 bits are followed by the Substitute Remote Request or SRR bit, which is defined to be recessive. The SRR bit is followed by the l-D-E bit, which is recessive to denote an extended CAN frame. The SRR bit in an extended CAN frame must be recessive to allow the assertion of a dominant RTR bit by a node that is sending a standard CAN remote frame. The SRR and l-D-E bits are followed by the remaining 18 bits of the identifier and the remote transmission request bit.
- The CAN protocol does not use acknowledgement messages but instead signals any errors that occur. For error detection, the CAN protocol implements three mechanisms at the message level. They are Cyclic Redundancy Check, Frame check and ACK errors. The CAN protocol also implements two mechanisms for error detection at the bit level. They are Monitoring and Bit Stuffing.
- The device also includes two full receive buffers with multiple acceptance filters for each. There is also a separate Message Assembly Buffer or MAB that acts as a third receive buffer. The MAB is always committed to receiving the next message from the bus. The MAB assembles all messages received. The remaining two receive buffers, called Rx B0 and Rx B1, can receive a complete message from the protocol engine via the MAB. The MCU can access one buffer, while the other buffer is available for message reception, or for holding a previously received message.
- The CAN protocol uses Non Return to Zero (NRZ) coding, which does not encode a clock within the data stream. Therefore, the receive clock must be recovered by the receiving nodes and synchronized to the transmitter’s clock. Each of the segments that make up a bit time are made up of integer units called Time Quanta or TQ. The length of each Time Quantum is based on the oscillator period (tOSC). The base TQ equals twice the oscillator period. The Synchronization Segment is the first segment in the NBT and is used to synchronize the nodes on the bus. This segment is fixed at 1 TQ. All devices on the CAN bus must use the same bit rate. For the different clock frequencies of the individual devices, the bit rate has to be adjusted by appropriately setting the baud rate pre-scaler and number of time quanta in each segment.
- The MCP2515 has eight sources of interrupts. The CAN INT E register contains the individual interrupt enable bits for each interrupt source. The CAN INT F register contains the corresponding interrupt flag bit for each interrupt source. When an interrupt occurs, the INT pin is driven low by the MCP2515 and will remain low until the interrupt is cleared by the MCU. An interrupt cannot be cleared if the respective condition still prevails. The CAN INT F flags are read/write and an interrupt can be generated by the MCU setting any of these bits, provided the associated CAN INT E bit is also set.
- The MCP2515 has 5 modes of operation. Configuration mode is automatically selected after power-up, a reset can be entered from any other mode by setting the CAN CONTROL REGISTER REQ-OP bits. When Configuration mode is entered, all error counters are cleared. Sleep mode is used to minimize the current consumption of the device. The SPI interface remains active for reading even when the MCP2515 is in Sleep mode, allowing access to all registers. Listen-only mode provides a means for the MCP2515 to receive all messages. This mode can be used for bus monitor applications or for detecting the baud rate in ‘hot plugging’ situations.
- Thank you for taking the time to view this presentation on “ MCP2515” . If you would like to learn more or go on to purchase some of these devices, you may either click on the part list link, or simply call our sales hotline. For more technical information you may either visit the Microchip Technology site, or if you would prefer to speak to someone live, please call our hotline number, or even use our ‘live chat’ online facility.