This document discusses clock gating of linear feedback shift registers (LFSRs) to reduce power consumption. Traditionally, an LFSR uses feedback to generate pseudo-random bit sequences by shifting bits and XORing outputs. The document proposes adding clock gating circuits that only toggle flip-flops when new data is available. This results in around a 10% reduction in power usage for the LFSR, though additional transistors are needed for the clock gating circuits.

1. CLOCK GATING
OF
LINEAR FEEDBACK SHIFT REGISTERS
RICHU JOSE CYRIAC
M120128EC
MICROELECTRONICS AND VLSI DESIGN

2. Traditional LFSR
• LFSR is used to pseudo random bit generator.
• It is usually a shift register with some flip-flop
outputs XOR ed and fed back into the first flip-
flop.
Simplified circuit of a generic n-bit LFSR[1]

3. Traditional LFSR…..(contd)
01 0 01 00111
1100, 1100, 1110, 1111, 0111, 1011, 0101, 1010,
1101, 0110, 0011,1001, 0100, 0010, 0001, 1000,1100…….

4. Gated clock design of LFSR

5. Gated clock design of LFSR…(contd)
XOR AND GATE[1]

6. CLOCK GATED OUTPUT

7. CONCLUSION
• Reduction in power is about 10% after applying
clock gating in LFSR.
• There is an overhead of 12 transistors per clock
gating circuit and it also dissipates power.

8. References
• Walter Aloisi and Rosario Mita, Member, IEEE,
“Gated clock design of Linear Feedback Shift
Register,” Ieee transactions on circuits and
systems—ii: express briefs, vol. 55, no. 6, JUNE
2008

9. THANK YOU