1. A shift register is a group of flip-flops arranged so that the binary numbers stored in the flip-flops are shifted from one flip-flop to the next for every clock pulse. There are several types including serial in/serial out, serial in/parallel out, parallel in/parallel out, and parallel in/serial out. 2. A serial in/parallel out shift register has a single data input and multiple parallel data outputs. It can be used to convert serial data to parallel form by loading data in one bit at a time over successive clock pulses until the full number is stored with its bits available at the outputs. 3. Shift registers can be used to delay a digital

1. 1

2. 2

3. 3

4. outinClock pulse
00
11
4

5. Shift Registers
A shift register is a group of FFs arranged so that the binary numbers stored in the FFs are
shifted from one FF to the next for every clock pulse.
Several types:
–Serial In/Serial Out
–Serial In/Parallel Out
–Parallel In/Parallel Out
–Parallel In/Serial Out
Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out
Parallel in/parallel outSerial in/parallel out Rotate right Rotate left
5

6. D3D2D1Clock
pulse
000-
001
010
100
Number of JK – FF =n
2^n = number of state
6

7. Serial In/Serial Out Shift Registers
A serial in/serial out shift register will have data loaded into it one bit at a
Time.
Example, The 74HC166 (and also the 74ALS166) can be used as a serial-in/serial-
out register. It is an eight-bit shift register.
7

8. Example:
Draw the output
of each stage.
8

9. Serial In/Parallel Out Registers
9
has a single data input and some number of parallel data outputs, as shown below.

10.  Conversion of serial data to parallel form.
For example, assume the binary number 1011 is loaded sequentially, one bit
at each clock pulse.
C
FF0
CLK
C
FF1
C
FF2
D0 D1 D2
Serial
data
input
C
FF3
D3Q0 Q1 Q2 Q3
1
C
FF0
CLK
C
FF1
C
FF2
D0 D1 D2
Serial
data
input
C
FF3
D3Q0 Q1 Q2 Q3
0 1
C
FF0
CLK
C
FF1
C
FF2
D0 D1 D2
Serial
data
input
C
FF3
D3Q0 Q1 Q2 Q3
1 0 1
C
FF0
CLK
C
FF1
C
FF2
D0 D1 D2
Serial
data
input
C
FF3
D3Q0 Q1 Q2 Q3
1 1 0 1
C
FF0
CLK
C
FF1
C
FF2
D0 D1 D2
Serial
data
input
C
FF3
D3Q0 Q1 Q2 Q3
1X 1 0 1
C
FF0
CLK
C
FF1
C
FF2
D0 D1 D2
Serial
data
input
C
FF3
D3Q0 Q1 Q2 Q3
1X 1 0 1
CLKCLKCLKCLK
After 4 clock pulses, the data is available at the parallel output.
Shift Register Applications
10

11. Example: the 74ALS164 is an eight-bit serial in/parallel out shift register
with each FF output externally accessible.
2^n = 8
n = 3
11

12. 12

13. 13

14. Shift Register Applications
 Delay a digital signal
Shift registers can be used to delay a digital signal by a predetermined amount.
Q7
Q7
A
B
Data out
CLK
40 MHz
Data in
CLK
Data in
Data out
td
C
SRG 8
EXAMPLE:
An 8-bit serial in/serial out shift register has a 40 MHz clock. What is the total delay through
the register?
The delay for each clock is
1/40 MHz = 25 ns
The total delay is 8 x
25 ns = 200 ns
14

15. 15

16. - An 8-bit serial in/serial out shift register has a 60 MHz clock.
What is the total delay through the register?
The delay for each clock is
1/60 MHz = 10 ns.
The total delay is 8 x
10 ns = 80 ns
16

17. 17

18. 18