Emitter Coupled Logic (ECL) was invented in 1956 and used transistors operating in an unsaturated mode. ECL uses current switching where the input voltage controls the current flowing through transistor legs. When the input voltage is low or high, one transistor is cut off while the other is active, starving the cut off transistor. ECL provides very fast operation of less than 1 nanosecond but has high power consumption and low noise immunity.

1. Emitter Coupled
Logic
PRESENTED BY
BY: SOMBARAN GUPTA

2. Table of contents
 Overview
 What is ECL..?
 Operation
 Characteristics
 Advantages and disadvantages

3. ECL was invented in August 1956 at IBM by Hannon S.
Yourke. Originally called current-steering logic, it was used in
the Stretch, IBM 7090, and IBM 7094 computers. The logic was also
called a current mode circuit.
Yourke's current switch, also known as ECL, and the input logic levels
were different from the output logic levels.

4. What is ECL..?
 ECL (Emitter-Coupled Logic)
 BJTs operating in unsaturated mode (i.e. emitter-follower mode)
 Principle: Current switching (ECL is also sometimes called Current-
Mode-Logic CML

5. OPERATION

6.  The ECL circuit operation is considered below with assumption that
the input voltage is applied to T1 base, while T2 input is unused or a
logical "0" is applied.
 During the transition, the emitter-coupled pair (T1 and T3) – acts as
a differential amplifier with single-ended input. The "long-tail"
current source (RE) sets the total current flowing through the two
legs of the pair. The input voltage controls the current flowing
through the transistors by sharing it between the two legs, steering it
all to one side when not near the switching point. The gain is higher
than at the end states and the circuit switches quick

7. At low input voltage (logical "0") or at high input voltage (logical "1")
the differential amplifier is overdriven. The one transistor (T1 or T3) is
cut-off and the other (T3 or T1) is in active linear region acting as
a common-emitter stage with emitter takes all the current, starving the
other cut-off transistor.
The active transistor is loaded with the relatively high emitter
resistance RE that introduces a significant negative feedback (emitter
degeneration). To prevent saturation of the active transistor so that the
diffusion time that slows the recovery from saturation will not be
involved in the logic delay, the emitter and collector resistances are
chosen such that at maximum input voltage some voltage is left across
the transistor

8. The circuit is insensitive to the input voltage variations and the
transistor stays firmly in active linear region. The input resistance is
high because of the series negative feedback.
The cut-off transistor breaks the connection between its input and
output. As a result, its input voltage does not affect the output voltage.
The input resistance is high again since the base-emitter junction is cut-
off.

9. Logic Families
 We have seen that different devices use different voltages
ranges for their logic levels
 They also differ in other characteristics
 In order to assure correct operation when gates are
interconnected they are normally produced in families
 The most widely used families are:
 complementary metal oxide semiconductor (CMOS)
 transistor-transistor logic (TTL)
 emitter-coupled logic (ECL)

10. Logic Family Characteristics
 Complementary metal oxide semiconductor (CMOS)
 most widely used family for large-scale devices
 combines high speed with low power consumption
 usually operates from a single supply of 5 – 15 V
 excellent noise immunity of about 30% of supply voltage
 can be connected to a large number of gates (about 50)
 power consumption depends on speed (perhaps 1 Mw)

11.  Transistor-transistor logic (TTL)
 based on bipolar transistors
 one of the most widely used families for small- and medium-scale
devices – rarely used for VLSI
 typically operated from 5V supply
 typical noise immunity about 1 – 1.6 V
 many forms, some optimised for speed, power, etc.
 high speed versions comparable to CMOS (~ 1.5 ns)
 low-power versions down to about 1 Mw/gate

12.  Emitter-coupled logic (ECL)
 based on bipolar transistors, but removes problems of storage time by
preventing the transistors from saturating
 very fast operation - propagation delays of 1ns or less
 high power consumption, perhaps 60 Mw/gate
 low noise immunity of about 0.2-0.25 V
 used in some high speed specialist applications, but now largely
replaced by high speed CMOS

13. CHARACTERISTICS
 Other noteworthy characteristics of the ECL family include the fact
that the large current requirement is approximately constant, and
does not depend significantly on the state of the circuit. This means
that ECL circuits generate relatively little power noise, unlike many
other logic types which typically draw far more current when
switching than quiescent, for which power noise can become
problematic. In cryptographic applications, ECL circuits are also less
susceptible to side channel attacks such as differential power
analysis.
 The propagation time for this arrangement can be less than a
nanosecond, making it for many years the fastest logic family

14. ADVANTAGES DISADVANTAGES OF
ECL
Advantages of ECL
 fastest logic family available
Disadvantages of ECL
 negative supply
 high static power dissipation
 limited choice of manufacturers and devices
 low noise margin

15. THANKYOU