The document discusses various clock systems, interrupts, and operating modes for microcontrollers: - It describes clock sources like crystal oscillators and a digitally controlled oscillator that provides the main system clock. - When an interrupt occurs, the program counter and status register are pushed to the stack before jumping to the interrupt service routine, which must end with a reti instruction. - Low power modes like LPM3 disable parts of the clock system to reduce power consumption while still allowing interrupts to wake the device. - Other topics covered include watchdog timers, interrupt prioritization, and entering/waking from low power modes.

1. Clock System,
Interrupts and
Operating Modes
MODULE 3

2. Clock System, Interrupts and Operating
Modes
• Clock System
• Interrupts,
• What happens when an interrupted is requested,
• Interrupt Service Routines,
• Low Power Modes of Operation,
• WatchdogTimer,
• BasicTimer1,
• RealTime Clock,
• Timer-A:Timer Block,
• Capture/Compare Channels,
• Interrupts fromTimer-A.

3. Clock system:
• All microcontrollers contain a clock module to drive the
CPU and peripherals.
• The conflicting requirements for clocks in high-
performance, low-power microcontrollers.
• Recall that the clock module provides three outputs:
• Master clock, MCLK is used by the CPU and a few
peripherals.
• Sub-system master clock, SMCLK is distributed to
peripherals.
• Auxiliary clock, ACLK is also distributed to peripherals.

4. Clock system:
• Most peripherals can choose either SMCLK, which is often
the same as MCLK and in the megahertz range, or ACLK,
which is typically much slower and usually 32 KHz.
• A few peripherals, such as analog-to-digital converters, can
also use MCLK and some timers, have their own clock
inputs.
• The frequencies of all three clocks can be divided in the
BCM+ as shown in fig.

5. Clock model:

6. Clock system:
• For example, you might wish to run the CPU at 8 MHz for
rapid execution of code and therefore choose
fMCLK = fDCOCLK = 8 MHz.
• On the other hand, it may be more convenient if the
peripherals run from a slower clock, in which case you
might configure the divider for SMCLK with DIVSx to give
fSMCLK = fDCOCLK/8 = 1 MHz.

7. Clock sources:
• Up to four sources are available for the clock, depending on the family and
variant:
• Low- or high-frequency crystal oscillator, LFXT1: Available in all devices.
It is usually used with a low-frequency watch crystal (32 KHz) but can also
run with a high-frequency crystal (typically a few MHz) in most devices. An
external clock signal can be used instead of a crystal if it is important to
synchronize the MSP430 with other devices in the system.
• High-frequency crystal oscillator, XT2: Similar to LFXT1 except that it is
restricted to high frequencies. It is available in only a few devices and
LFXT1 (orVLO) is used instead if XT2 is missing.
• Internal very low-power, low-frequency oscillator,VLO: Available in only
the more recent MSP430F2xx devices. It provides an alternative to LFXT1
when the accuracy of a crystal is not needed.
• Digitally controlled oscillator, DCO: Available in all devices and one of the
highlights of the MSP430. It is basically a highly controllable RC oscillator
that starts in less than 1 ms in newer devices.

8. Crystal Oscillators, LFXT1 and XT2
• Crystals are used when an accurate, stable frequency is needed:
• Accurate means that the frequency is close to what it says on the package,
typically within 1 part in 105.
• Stable means that does not change significantly with time or temperature.
• Crystals are cut from carefully grown, high-quality quartz with specific
orientations to give them high stability.
• Traditional crystals oscillated at frequencies of a few MHz but most small
microcontrollers use low-frequency watch crystals with a frequency of 32
KHz.These are machined into complicated tuning fork shapes to give the low
frequency.
• A disadvantage is that their frequency is more sensitive to temperature than
high-frequency crystals, but they are designed to be most stable near 25◦C.

9. LFXT1 and XT2
• Oscillator circuits are integrated into the MSP430 and the crystal
should be connected to pins XIN and XOUT.
• The circuit is known as a Pierce oscillator and also requires a
capacitance to ground from each pin.
• The oscillator is designed to run at low power and this renders it
susceptible to electromagnetic interference.
• It is also possible to use high-frequency crystals (above 400 KHz) with
LFXT1 in most devices and some have a second oscillator XT2, which
works only at high frequencies.
• External capacitors must be used with high-frequency crystals and
the module must be configured for a suitable range of frequencies.
The module also accepts an external clock signal on XIN.

10. LFXT1 and XT2
• The stability of crystals is reflected electrically in their high Q factor.
• This means that they oscillate for a long time after being excited, like
the ringing tone from a wine glass after it has been tapped.
• The disadvantage of this is that the oscillator takes an equally long
time to reach a stable state, typically around 105 cycles.

11. Internal Low-Power, Low-Frequency Oscillator,
VLO
• TheVLO is an internal RC oscillator that runs at around 12 KHz and can be
used instead of LFXT1 in some newer devices.
• It saves the cost and space required for a crystal and reduces the current
drawn.
• The data sheet for the F2013 shows that LFXT1 draws about 0.8 mA,
which falls to 0.5 mA with theVLO.
• Of course this comes at a cost: accuracy and stability. The same data
sheet quotes a range of frequency for fVLO from 4 to 20 KHz.
• This looks terrible at first sight but closer reading shows that it covers the
full operating range of the device in voltage and temperature.
• A variation of 10◦C changes the frequency by about 5% instead of 5 ppm
for a crystal. Clearly you would not use theVLO for serious timing.

12. Digitally Controlled Oscillator, DCO
• One of the aims of the original design of the MSP430 was that it
should be able to start rapidly at full speed from a low-power mode,
without waiting a long time for the clock to settle.
• Early versions of the DCO started in 6 ms, which has been reduced to
1–2 ms in the MSP430F2xx family.
• There are no erratic pulses:The output from the DCO starts cleanly
after this delay.
• The frequency can be controlled through sets of bits in the module’s
registers at three levels.

13. Digitally Controlled Oscillator, DCO
• The first two levels set the DCO to a constant frequency:
• RSELx: Selects one of 16 coarse ranges of frequency.The
frequencies in each range are larger than those in the one below by a
factor of 1.3–1.4.The overall range is about 0.09–20 MHz.
• DCOx: Selects one of eight steps within each range. Each step
increases the frequency by about 8%, giving a factor of 1.7 from
bottom to top of the range.Thus the ranges overlap slightly.
• Figure 5.9 shows the frequency of the DCO in the low part of its
range as a function of RSELx and DCOx.There is roughly a constant
ratio between values so a logarithmic scale would be needed to show
the full range clearly.

14. Digitally Controlled Oscillator, DCO

15. Digitally Controlled Oscillator, DCO
• Finer control of the average frequency is obtained by modulating the
frequency of the oscillator between the selected value of DCO and
the next step up (DCO + 1).
• This needs DCO < 7 of course. Each period of 32 clock cycles contains
MOD cycles with the higher frequency given by (DCO + 1) and (32 −
MOD) cycles with the lower frequency given by DCO.
• The average period over these 32 cycles is therefore

16. Digitally Controlled Oscillator, DCO
• The DCO does not simply produce MOD pulses of one frequency
followed by (32 − MOD) of the other, but mixes them thoroughly.
• For example, setting MOD = 16 gives an equal number of pulses of
the two frequencies and they alternate: Each period given by DCO
is followed by one given by (DCO + 1).
• The values of RSEL, DCO, and MOD can be changed at any time to
alter the frequency.
• Modulation can be turned off by setting MOD = 0 if a constant
period is more important than an accurate, average frequency.
• This is shown on the oscilloscope in Figure 5.10.

17. Digitally Controlled Oscillator, DCO

18. Control of the Clock Module through the Status
Register
• The clock module is controlled by 4 bits in the status register as well
as its own peripheral registers.
• This is because of the intimate connection between clocks and low-
power modes.
• It is rarely necessary to alter these bits directly because there are
intrinsic functions or predefined constants for each low-power mode.

19. Control of the Clock Module through the
Status Register
• All bits are clear in the full-power, active mode.This is the main effect
of setting each bit in the MSP430F2xx:
• CPUOFF disables MCLK, which stops the CPU and any peripherals
that use MCLK.
• SCG1 disables SMCLK and peripherals that use it.
• SCG0 disables the DC generator for the DCO (disables the FLL in the
MSP430x4xx family).
• OSCOFF disablesVLO and LFXT1.

20. Control of the Clock Module through the
Status Register
• bis .w # SCG1 +SCG0 , SR ; Stop DCO
• bis .b # SELM_3 + DIVM_3 ,& BCSCTL2 ; MCLK = LFXT1 /8

21. What Happens when an Interrupt Is
Requested?
Hardware then performs the following steps to launch the ISR:
• Any currently executing instruction is completed if the CPU was active when
the interrupt was requested. MCLK is started if the CPU was off.
• The PC, which points to the next instruction, is pushed onto the stack.
• The SR is pushed onto the stack.
• The interrupt with the highest priority is selected if multiple interrupts are
waiting for service.
• The interrupt request flag is cleared automatically for vectors that have a
single source. Flags remain set for servicing by software if the vector has
multiple sources.

22. What Happens when an Interrupt Is
Requested?
• The SR is cleared, which has two effects. First, further maskable
interrupts are disabled because the GIE bit is cleared; nonmaskable
interrupts remain active.
• The interrupt vector is loaded into the PC and the CPU starts to
execute the interrupt service routine at that address.
• This sequence takes six clock cycles in the MSP430 before the ISR
commences.The stack at this point is shown in Figure 6.5.

23. What Happens when an Interrupt Is
Requested?

24. What Happens when an Interrupt Is
Requested?
• An interrupt service routine must always finish with the
special return from interrupt instruction reti, which has the
following actions:
• The SR pops from the stack. All previous settings of GIE and
the mode control bits are now in effect, regardless of the
settings used during the interrupt service routine. In
particular, this reenables maskable interrupts and restores
the previous low-power mode of operation if there was one.
• The PC pops from the stack and execution resumes at the
point where it was interrupted. Alternatively, the CPU stops
and the device reverts to its low-power mode before the
interrupt.

25. Interrupt Service Routines
• Interrupt Service Routines in Assembly Language
• An ISR looks almost identical to a subroutine but with two
distinctions:
• The address of the subroutine, for which we can use its name
(a label on its first line), must be stored in the appropriate
interrupt vector.
• The routine must end with reti rather than ret so that the
correct sequence of actions takes place when it returns.

26. Interrupt Service Routines in C
• An interrupt service routine cannot be written entirely in standard C
because there is no way to identify it as an ISR rather than an ordinary
function.
• In fact it would appear that the function was dead code, meaning that
it could never be called, so the compiler would optimize it away.
• .Two additions are needed to the ISR. First is the #pragma line, which
associates the function with a particular interrupt vector.
• The second is the _ _interrupt keyword at the beginning of the line that
names the function.
• This ensures that the address of the function is stored in the vector and
that the function ends with reti rather than ret.

27. Nonmaskable Interrupts
• There are a few small differences in the handling of
nonmaskable interrupts compared with the maskable type.
• All the sources share a single vector, which has the highest
address and therefore the highest priority except for the reset
vector.
• Three modules can request a nonmaskable interrupt:
• Oscillator fault, OFIFG, Remember that this flag is set by a power-up
clear as a warning that the oscillator may not yet have stabilized. This
interrupt should therefore not be enabled until the oscillator is running
correctly.
• Access violation to flash memory,ACCVIFG.
• An active edge on the external RST/NMI pin if it has been configured for
interrupts rather than reset.

28. Low-Power Modes of Operation
• There are five in all but two are rarely employed in current
devices (they were useful with earlier versions of the DCO).
The most important modes are summarized here with
typical currents I for the F2013 taken from its data sheet.
• These are for VCC = 3V, the DCO running at 1 MHz, and
LFXT1 at 32 KHz from a crystal.The current in active mode
rises with frequency to about 4 mA at 16 MHz, although
this requires a higher supply voltage.

29. Low-Power Modes of Operation
• Active mode: CPU, all clocks, and enabled modules are
active, I ≈ 300 mA.The MSP430 starts up in this mode,
which must be used when the CPU is required.
• An interrupt automatically switches the device to active
mode.The current can be reduced by running the MSP430
at the lowest supply voltage consistent with the frequency
of MCLK; VCC can be lowered to 1.8V for fDCO = 1 MHz,
giving I ≈ 200 mA.

30. Low-Power Modes of Operation
• LPM0: CPU and MCLK are disabled, SMCLK and ACLK remain
active, I ≈ 85 mA. This is used when the CPU is not required but
some modules require a fast clock from SMCLK and the DCO.
• LPM3: CPU, MCLK, SMCLK, and DCO are disabled; only ACLK
remains active; I ≈ 1 mA.This is the standard low-power mode when
the device must wake itself at regular intervals and therefore needs
a (slow) clock. It is also required if the MSP430 must maintain a real-
time clock.The current can be reduced to about 0.5 mA by using the
VLO instead of an external crystal in a MSP430F2xx if fACLK need not
be accurate.
• LPM4: CPU and all clocks are disabled, I ≈ 0.1 mA.The device can be
wakened only by an external signal.This is also called RAM retention
mode.

31. Low-Power Modes of Operation
• The usual instructions in assembly language can be used to modify the bits
that control the low-power modes.
• bis .w # LPM3 , SR ; enter LPM3 but can we wake again ?
• The MSP430 can be awakened only by an interrupt so these must be enabled
by setting the GIE bit in SR if it has not been done already.The following line is
therefore much safer:
• bis .w # GIE | LPM3 , SR ; enter LPM3 with interruptsenabled
• This cannot be done in standard C, of course, and an intrinsic function is
required.The function that follows is taken from intrinsics.h and sets both the
low-power and GIE bits:
• l o w _ p o w e r _ m o d e _ 3 ();// enter LPM3 with interrupts enabled
• This simply calls another intrinsic function, _ _bis_SR_register(), with the same
set of bits as the assembly code.

32. Low-Power Modes of Operation
• It is common to describe a device as sleeping when it is in a low-power
mode, although this is a little vague in the MSP430 with its range of
modes.
• Similarly, waking means that the device returns to active mode.
• Many processors are put into low-power modes by issuing special sleep or
stop instructions but these are not required with the MSP430.
• Instead its operation is controlled through the four bits: SCG0, SCG1,
CPUOFF, and OSCOFF in the status register.All these are clear in active
mode and particular combinations are set for each low-power mode.
• For example, setting only CPUOFF disables the CPU and MCLK, putting
the MSP430 into LPM0.

33. Waking from a Low-Power Mode
• An interrupt is needed to awaken the MSP430.The
processor handles an interrupt from a low-power mode in
almost the same way as in active mode.
• The only difference is that MCLK must first be started so
that the CPU can handle the interrupt; this replaces the first
step when the CPU is active, which is to complete the
current instruction.
• MCLK is started automatically by the hardware for
servicing interrupts and requires no intervention from the
programmer.

34. Watchdog Timer
• The main purpose of the watchdog timer is to protect the system against
failure of the software, such as the program becoming trapped in an
unintended, infinite loop.
• Left to itself, the watchdog counts up and resets the MSP430 when it
reaches its limit.
• The code must therefore keep clearing the counter before the limit is
reached to prevent a reset.
• The operation of the watchdog is controlled by the 16-bit register WDTCTL.
• It is guarded against accidental writes by requiring the passwordWDTPW =
0x5A in the upper byte.
• A reset will occur if a value with an incorrect password is written to
WDTCTL.
• This can be done deliberately if you need to reset the chip from software.
• Reading WDTCTL returns 0x69 in the upper byte, so readingWDTCTL and
writing the value back violates the password and causes a reset.

35. WDTCTL
• The lower byte ofWDTCTL contains the bits that control the
operation of the watchdog timer, shown in Figure 8.1.

36. Watchdog Timer
• The watchdog counter is a 16-bit register WDTCNT, which is not
visible to the user.
• It is clocked from either SMCLK (default) orACLK, according to the
WDTSSEL bit.
• The reset output can be selected from bits 6, 9, 13, or 15 of the
counter.
• Thus the period is 26 = 64, 512, 8192, or 32,768 (default) times the
period of the clock.

37. Watchdog Timer
• The watchdog is always active after the MSP430 has been reset.
• By default the clock is SMCLK, which is in turn derived from the DCO at
about 1 MHz.The default period of the watchdog is the maximum value of
32,768 counts, which is therefore around 32 ms.
• You must clear, stop, or reconfigure the watchdog before this time has
elapsed.
• By setting the WDTHOLD bit.
• The reset caused by the watchdog can be a nuisance during development
because a PUC destroys much of the evidence that could help you to detect
a problem that caused the watchdog to time out.
• A solution might be to generate an interrupt rather than a reset by using the
watchdog as an interval timer.

38. Watchdog Timer
• The interrupt service routine could copy critical data to
somewhere safe, signal a problem by lighting an LED, or
simply cause execution to stop on a breakpoint.

39. Failsafe Clock Source for Watchdog Timer+
• Newer devices, including the MSP430F2xx family and recent
members of the MSP430x4xx, have the enhanced watchdog timer+
(WDT+).
• This includes fail-safe logic to preserve the watchdog’s clock.
Suppose that the watchdog is configured to use ACLK and the
program enters low-power mode 4 to wait for an external interrupt.
• The old watchdog (WDT) stops during LPM4 and resumes counting
when the device is awakened.
• In contrast,WDT+ does not let the device enter LPM4 because that
would disable its clock.
• Therefore it is not possible to use LPM4 with WDT+ active

40. Failsafe Clock Source for Watchdog Timer+
• The watchdog must first be stopped by setting WDTHOLD.
• Similarly, it is not possible to use LPM3 if WDT+ is active and gets its
clock from SMCLK.
• If its clock fails, WDT+ switches fromACLK or SMCLK to MCLK and
takes this from the DCO if an external crystal fails.

41. Watchdog as an Interval Timer
• The watchdog can be used as an interval timer if its protective
function is not desired.
• Set the WDTTMSEL bit inWDTCTL for interval timer mode.
• The periods are the same as before and againWDTIFG is set when the
timer reaches its limit, but no reset occurs.
• The counter rolls over and restarts from 0.
• An interrupt is requested if the WDTIE bit in the special function
register IE1 is set.
• This interrupt is maskable and as usual takes effect only if GIE is also
set.

42. Basic Timer1
• Basic Timer1 is present in all MSP430xF4xx devices and is
perhaps the most straight-forward module in the MSP430,
as you might guess from its name.
• It provides the clock for the LCD module and generates
periodic interrupts.
• A slightly simplified block diagram is shown in Figure 8.2.
Newer devices also contain a real-time clock driven by a
signal at 1 Hz from BasicTimer1.

43. Basic Timer1

44. BTCTL
• The register BTCTL shown in Figure 8.3 controls most of the functions
of BasicTimer1 but there are also bits in the special function registers
IFG2 and IE2 for interrupts.
• An unusual feature of this module is that BTCTL is not initialized by a
reset:This must be done by the user.
• It is not even specified whether the timer is running or not.
• The counters are not initialized either and this should be done before
the timer is started or the first interval will be incorrect.

45. Basic timer 1
• There are two 8-bit counters in Basic Timer1, which can
either be used independently or cascaded for longer
intervals:
• BTCNT1: Takes its input from ACLK and provides the clock
for the LCD module at frequency fLCD.
• The two BTFRFQx bits select the value of fLCD, which can
vary from fACLK/256 to fACLK/32 in powers of 2.
• It is assumed that fACLK = 32 KHz. This gives fLCD from 128 Hz
to 1 KHz, which should be suitable for the LCD.

46. Basic timer 1
• BTCNT2: Can be used independently of BTCNT1, in
which case the BTSSEL bit selects the clock from
ACLK or SMCLK.
• For longer intervals, BTCNT2 can be clocked from
the output of BTCNT1 at a frequency of fACLK/256.
Set the BTDIV bit to cascade the counters in this
way.
• Setting the BTHOLD bit stops BTCNT2, but stops
BTCNT1 only if BTDIV is also set.

47. Real-Time Clock
• A Real-Time Clock (RTC) module has been added to recent
devices in the MSP430xFxx family.
• It counts seconds, minutes, hours, days, months, and years.
Alternatively it can be used as a straightforward counter.
• Assume that it is configured in calendar mode by setting
RTCMODEx = 11 in the control register RTCCTL.
• The bits are shown in Figure 8.4.
• This register is initialized after a power-on reset, unlike BTCTL,
and the RTCHOLD bit is set so that the clock does not run by
default.

48. Real-Time Clock

49. Real-Time Clock
• The current time and date are held in a set of registers that contain the following
bytes:
• Second (RTCSEC).
• Minute (RTCMIN).
• Hour (RTCHOUR), which runs from 0–23 (24-hour format).
• Day of week (RTCDOW), which runs from 0–6.
• Day of month (RTCDAY)
• Month (RTCMON).
• Year (RTCYEARL), assuming BCD format.
• Century (RTCYEARH), assuming BCD format.
• The registers are arranged in pairs that can also be accessed as words. For
example, RTCYEAR = RTCYEARH:RTCYEARL and RTCTIM0 = RTCMIN:RTCSEC.
Their values can be stored either as normal binary numbers or as BCD.

50. Real-Time Clock
• The clock needs a 1 Hz input, which it takes from Basic
Timer1.
• The Real-Time Clock has an interrupt flag RTCFG and
corresponding enable bit RTCIE in RTCCTL.
• The flag is set every minute, every hour, daily at midnight,
or daily at noon depending on the RTCTEVx bits.
• The interrupt vector is shared with BasicTimer1. It is
maskable and can be used in two ways:

51. Real-Time Clock
1. Interrupts are generated by the Real-Time Clock module if
RTCIE is set.
• Both the BTIFG and RTCFG flags are set at an interrupt and
cleared automatically when it is serviced.The interval is
determined by RTCTEVx.
• Interrupts come from BasicTimer1 as described earlier if RTCIE is
clear.
2. The interval is determined by BTIPx.The Real-Time Clock
sets its RTCFG flag according to RTCTEVx but this does
not request an interrupt.
• A program can poll the flag to check whether an interval of time
has elapsed and must clear RTCFG in software.

52. Timer_A
• This is the most versatile, general-purpose timer in the MSP430
and is included in all devices.
• There are two main parts to the hardware:
• Timer block: The core, based on the 16-bit registerTAR.There is a
choice of sources for the clock, whose frequency can be divided
down (prescaled).The timer block has no output but a flagTAIFG is
raised when the counter returns to 0.
• Capture/compare channels: In which most events occur, each of
which is based on a registerTACCRn.They all work in the same
way with the important exception ofTACCR0. Each channel can

53. Timer_A
• Capture an input, which means recording the “time” (the value inTAR)
at which the input changes inTACCRn; the input can be either external
or internal from another peripheral or software.
• Compare the current value ofTAR with the value stored inTACCRn and
update an output when they match; the output can again be either
external or internal.
• Request an interrupt by setting its flagTACCRn CCIFG on either of
these events; this can be done even if no output signal is produced.
• Sample an input at a compare event; this special feature is particularly
useful if Timer_A is used for serial communication in a device that lacks
a dedicated interface.

54. Timer Block

55. Timer Block
• Remember that a timer is really no more than a counter and
has no direct concept of time (the Real-Time Clock is an
exception).
• It is the programmer’s job to establish a relation between
the value in the counter and real time.
• This depends essentially on the frequency of the clock for
the timer. It can be chosen from four sources by using the
TASSELx bits:
• SMCLK is internal and usually fast (megahertz).
• ACLK is internal and usually slow, typically 32 KHz from a watch crystal but
may be taken from theVLO in the MSP430F2xx family.
• TACLK is external.
• INCLK is also external, sometimes a separate pin but often it is connected through an
inverter to the pin forTACLK so that INCLK =TACLK.

56. Timer Block
• The frequency of the incoming clock can be divided down
by 2, 4, or 8 if desired by configuring the IDx bits.
• A slower clock reduces the resolution of the timer so that
events are timed less precisely.
• Against this, it increases the natural period of the timer
before it overflows, rolls over, and restarts from 0.
• It is not difficult to count the number of overflows for
intervals longer than the period but of course it is easier to
avoid it.
• The trade-off between resolution and period by choosing
different clocks is shown inTable 8.1.

57. Timer Block
• The period of the timer can range from 4 ms with the fastest SMCLK
to 16 s with a 32 KHzACLK and maximum division (even longer with
the 12 KHzVLO).
• I assume that SMCLK runs at the same frequency as MCLK but it can
also be divided in the MSP430x1xx and MSP430F2xx families, which
allows longer periods from SMCLK.

58. Timer modes
• These periods all apply to the Continuous mode, in whichTAR
cycles through its full range.
• The timer has four modes of operation, selected with the MCx
bits:
• Stop (MC= 0): The timer is halted. All registers, includingTAR,
retain their values so that the timer can be restarted later where
it left off.
• Continuous (2): The counter runs freely through its full range
from 0x0000 to 0xFFFF, at which point it overflows and rolls
over back to 0.The period is 2^16 =65,536 counts.This mode is
most convenient for capturing inputs and is also used when
channels provide outputs with different frequencies or that are
not periodic at all.

59. Timer modes
• Up (1): The counter counts from 0 up to the value in
TACCR0, the capture/compare register for channel 0. It
returns to 0 on the next clock transition.The period is
(TACCR0+1) counts. For example, ifTACCR0=4, the
sequence of counts is 0, 1, 2, 3, 4, 0, 1, ... with period 5. Up
mode is usually used when all channels provide outputs at
the same frequency, often for pulse-width modulation.
• Up/Down (3): The counter counts from 0 up toTACCR0,
then down again to 0 and repeats.The period is 2 xTACCR0
counts. For example, ifTACCR0=3, the sequence of counts is
0, 1, 2, 3, 2, 1, 0, 1, ... with period 6.This is a specialized
mode, typically used for centered pulse-width modulation.

60. Capture/Compare Channels
• Timer_A has three channels in most MSP430s although channel 0 is
lost to many applications because its registerTACCR0 is needed to
set the limit of counting in Up and Up/Down modes.
• Each channel is controlled by a registerTACCTLn, shown in Figure
8.6.

61. Capture/Compare Channels
• The central feature of each channel is its capture/compare register
TACCRn.
• In Capture mode this stores the “time”—the value inTAR—at which
an event occurs on the input; in Compare mode it specifies the time at
which the output should next be changed and an interrupt requested.
• The mode is selected with the CAP bit.This is cleared by default so
that the channel is in Compare mode.
• Any mixture of capture and compare channels can be used and the
mode can be switched freely from one to the other.

62. Capture Mode Hardware
• An event can be a rising edge, falling edge, or either edge on
the input according to the capture mode bits CMx.
• The CCISx bits inTACCTLn select the input to be captured.
• Two of these, CCInA and CCInB, come from outside the timer
module.They have many possible connections, set out in the
section onTimer_A in the data sheet for the particular device.
• Often CCInA is connected to external pinTAn while CCInB is
connected internally to another module. Here are the internal
connections for the F20x1 as an example:

63. Capture Mode Hardware
• CCI1B comes from CAOUT, the output of the comparator.
This allows precise timing of a measurement without the
overhead and delay that would arise if software were
needed to trigger a capture when CAOUT changed
• CCI0B is connected to ACLK, which allows the frequency of
SMCLK to be compared with ACLK.This enables a
frequency-locked loop to be completed in software to
synchronize the two clocks.

64. Compare Mode Hardware
• The purpose of Compare mode is to produce an output and
interrupt at the time stored inTACCRn.
• Several actions are triggered whenTAR counts to the value in
TACCRn:
•The internal signal EQUn is set.
•This in turn raises the CCIFGn flag and requests an interrupt if
enabled.
•The output signal OUTn is changed according to the mode set
by the OUTMODx bits inTACCTLn.
•The input signal to the capture hardware, CCI, is latched into
the SCCI bit.

65. Compare Mode Hardware
• The output modes are listed inTable 8.2.They are more complicated
than you might expect because changes in all channels can be
triggered by EQU0 as well as EQUn. I illustrate the operation in later
sections but here is a quick summary of their typical uses:

66. Compare Mode Hardware
• Output (mode 0): In which output is controlled directly by the OUT
bit inTACCTLn;TAR has no influence. It is as if the pin is used for
normal, digital output but operated viaTimer_A.This mode is used to
set up the initial state of the output before compare events take over.
For example, the first period of pulse-width modulation (PWM) may
be erratic if this is not done, but it often does not matter.
• Toggle (mode 4): Provides a simple way of switching a load on and
off for equal times (50% duty cycle) and can be used even with
channel 0 in Up and Up/Down modes.The disadvantage is that the
load is toggled only once per cycle of the timer and its frequency is
therefore halved (period doubled).
• Set (mode 1) and Reset (mode 5): Typically used for single changes
in the output, usually in the Continuous mode.

67. Compare Mode Hardware
• Reset/Set (mode 7) and Set/Reset (mode 3): Typically used for
periodic, edge- aligned PWM in Up mode of the counter. In this case
the first action takes place whenTAR matchesTACCRn and the
second action occurs whenTAR returns to 0, one count after the
match toTACCR0. (This is not made entirely clear in the user’s
guides.)
• Toggle/Reset (mode 2) andToggle/Set (mode 6): Typically used for
center-aligned PWM in Up/Down mode.The first action takes place
whenTAR matchesTACCRn and the second occurs whenTAR
matchesTACCR0.The second action is needed only once to fix the
sign of the waveform; all subsequent action is done by toggling at
matches ofTACCRn.

68. Interrupts from Timer_A
• Interrupts can be generated by the timer block itself (flagTAIFG) and
each capture/compare channel (flagTACCRn CCIFG or CCIFGn for short).
• TACCR0 is privileged and has its own interrupt vector,
TIMERA0_VECTOR. Its priority is higher than the other vector,
TIMERA1_VECTOR, which is shared by the remaining capture/compare
channels and the timer block.
• The CCIFG0 flag is cleared automatically when its interrupt is serviced
but this does not happen for the other interrupts because the interrupt
service routine (ISR) must first determine the source of the interrupt.
• The obvious way of doing this is to pollTAIFG and all the CCIFGn flags
to locate which is active, clear the flag, and service the interrupt.
• Unfortunately this is slow, which is particularly undesirable in an ISR.
The MSP430 therefore provides an interrupt vector register TAIV to
identify the source of the interrupt rapidly.

69. Interrupts from Timer_A
• When one or more of the shared and enabled interrupt flags is set,
TAIV is loaded with the value corresponding to the source with the
highest priority.The possible values inTAIV forTimer_A3 are listed in
Table 8.3