This document discusses library characterization, which involves characterizing standard cell libraries used in semiconductor design. It begins with an overview of why library characterization is an interesting career and then discusses fundamental terminology. It provides examples of characterizing an inverter and D flip-flop, covering timing analysis, power characterization, and more. Advanced topics discussed include state dependent delays, load capacitance characterization, and measuring tri-state delays. References are provided for further reading.

1. Library Characterization Its Impact on Semiconductor Industry & the flow Satish Kumar Grandhi (https://sites.google.com/site/satishkumargrandhi2/)

2. Let’s start off on a Funny Note Why Choose Library Characterization as a career ?? Very little manual effort, need only little extra intelligence Effort – 30% , Enjoyment – 70% ; No need to work over weekends  Only one issue : Convergence (Kills u big time) Double Edged Sword; Little Chance of firing . But, Very few players in this business, no great chances of jumping around . Most Important ; It keeps your options wide open Physical Design, STA EDA Tool Development Circuit Design

3. Acknowledgements Heart Felt Thanks to Masamb Electronics, Anupam Kumar Sinha in specific Naveen Kumar Kotha (LSI Bangalore), Rachit I. Kushalappa (TI, Bangalore) & Naresh ANNE (AMD USA) Wiki, EDABoard & LTSPICE yahoo group NANGATE for providing open source 45nm STD cell library package All prof’s with US universities (You guys don’t hide your work in the internal repositories, hats off to you) Collegues @ NXP, Cypress & ST MicroElectronics Check out my weblink on Library Characterization for latest updated version of these slides & for more info Speaker guarantees no originality in this work ; It is a mix of material accumulated from various sources We are as dwarfs sitting on the shoulders of giants -- Sir Issac Newton

4. Contents Necessity & the Impact Fundamental Terminology Glancing Through .LIB Characterization Methodology Case Studies : Inverter & D-Flop Advanced Topics References

5. Two Great Laws Moore’s LawOn April 19, 1965 Moore predicted the most important law ever proposed in Semiconductors. Amdahl's law states that the performance improvement to be gained from using some faster mode of execution is limited by the fraction of the time the faster mode can be used Missing 3rd law, the NLDM law  How are these related ??

6. How to Implement them ?

7. Two Generic Flows Reference : Allen Holberg, Gatech and Laker, Upenn Class Room Lectures

8. INTEL Processor’s Growth * All the predictions are based on wiki…could be approximate

9. Characterization Terminology

10. Input Slew & Output Load Slew rate : Represents the maximum rate of change of signal Output Load : Total amount of capacitance at the output node

11. Timing - Combinational Transition Delay Time a system needs to switch between two different stable states, when responding to a stable input signal Propagation Delays Time it takes for the output signal to switch after the input signal has been applied.

12. Timing – Sequential 1 Setup & Hold Minimum time the data signal has to be present at the input pin of a memory cell before/after the write signal arrives. General Methodology employed : Binary Chop

13. Timing - Sequential 2 Recovery / Removal Minimum time delay that has to maintained between an asynchronous clear/set signal and before/after the clock of the cell is triggered. Method Used : Binary Chop

14. Timing – Sequential 3 Minimum Pulse WidthMinimum width of control signal in order for the cell to detect it. If the clock signal active period is smaller than this minimum time, you cannot be sure that the cell will have stored the input’s value properly.

15. Timing Unateness Positive Unate Negative Unate Non Unate

16. Power – Short circuit If a path exists from power supply to ground, it results in continuous flow of current and results in static power dissipation CMOS Technology has neglible static power consumption (biggest advantage and reason as to why CMOS is so very popular).

17. Power - Dynamic Power dissipated during the charging and discharging of the output Load capacitance. Pdyn = CL * Vdd2 * f

18. Power - Leakage The power consumed by the sub threshold currents and by reverse biased diodes in a CMOS transistor Major Sources : Sub threshold condition Gate Leakage current * Check out Reference6

19. Wire Load Models /* Wire load table */ wire_load("ABC") { capacitance : 1.774000e-04; resistance : 3.571429e-03; area : 7.559700e-02; slope : 5.000000; fanout_length( 1, 1.3207 ); fanout_length( 2, 2.9813 ); fanout_length( 3, 5.1135 ); fanout_length( 4, 7.6639 ); fanout_length( 5, 10.0334 ); fanout_length( 6, 12.2296 ); fanout_length( 8, 19.3185 ); } No info on interconnect parasitic before Physical Design Attempts to predict the capacitance and resistance of nets in the absence of placement and routing information Excellent Paper : Steve Golson, "Resistance is Futile! Building Better Wireload Models" (Link)

20. Library Characterization Flow

21. Methodology * Prototype Copied from Liberty NCX manual

22. Sensitization Set of logic conditions leading to transition; This logic condition setup process is called sensitization. In other words, it generates the stimulus at the cell input pins necessary to produce a simulation measurement of the desired characteristic, such as delay or slew. No simulations performed, analytically derives the functionality of the cell from Boolean expressions, truth tables, state tables, and flip-flop latch groups defined in the input library or template files.

23. Load Sharing Facility (LSF) Goal : Give many users processes "fair share" of resources (CPU, memory , ….) Commands : bjobs, bqueues, bhist, bkill, bswitch, bpause, bresume

24. How Simulator Works ?? Input Setup Sanity Check Generate .LIB (final masala) Arc List for each Cell Fetch the Results Develop Sensitization Vector’s Launch Them on LSF Create Spice Deck for each case

25. Capacitance Characterization Buffer comparison methodcalculates by comparing the output slope of three identical reference buffers. Charge calculation method monitors the total current (charge) flowing through each input pin and integrates it over a period of time

26. Power Characterization Calculates the current consumed and convert into power Find paths from input pins to outputs, look for every valid pin combination of the cell and simulate it. Plus, some input combinations don't change any output. But, results in power consumption For example: Clocks, sets, resets etc. that do not change the output because it already had the proper state Input changes without a clock change Also, Leakage power

27. Case Study: Inverter & D-Flop

28. .Measure (Spice Command) Prints the results of specific user defined analyses With this command you can measure rise and fall times, length of a pulse, delays, voltages, etc. ELDO - .extract Spectre – {export}???

29. CS 1 : Inverter ARCS : IN  OUT Measurements : Rise, Fall Sensitization Vectors IN : 01, 10 OUT : 10, 01

30. Cap Measurements Power Measurements

31. Timing Calculations

32. Technology Impact Simulated a 3 Input NAND gate (all inputs set to '1') using cadence GPDK180 & NANGATE's 45nm models With shrinking gate length, the leakage current increases Ref : ITRS Roadmap 2005

33. CS 2 : D Flip Flop Consider a Asynchronous flop with set & Reset pins. Possible arcs to be characterized : Clk -> Q (delay) D -> Clk (setup & Hold) Set/ Reset -> Clk (Recovery & Removal) Power & cap characterization (Each instance is a 3 input nand gate)

34. Various Arcs in Scan Flop ( Snapshot from Reference 3 )

35. Setup Analysis ** For Setup Time Analysis VIN2 D 0 pwl 0 0 4.99995n 0 5.99995n 1.8 11n 1.8 12n 0 24n 0 24.9995n 0 25.9995n 1.8 .MEASURE TRAN setup_time **** Constrained pin is falling + trig V(D) val = 0.9 rise= 1 **** Related pin is rising + targ V(CLK) val = 0.9 rise = 2 Setup time=1.955e-008 FROM 5.49995e-009 TO 2.505e-008

36. From STA Point of View --Very primitive, will improve in the days to come

37. CAP on a net Total o/p node cap = Sum of { all input caps of driven cells + wire Capacitance + O/p Node Capacitance }

38. Delay Calculation UINV0 (NET0, I2) UAND1 (O1, I1, NET0) UNOR2(O2, O1, NET0)

39. Advanced Topics

40. State Dependent Delays Timing arcs depend on the state of pins other than Input & Output Multiple timing models are used to describe ‘a’ arc Consider a 2 I/P XOR Gate timing () { related_pin : "A"; when : "B"; sdf_cond : "(B == 1'b1)"; timing_sense : negative_unate; cell_fall(Timing_data_X1) { values ("0.012959,0.015005,…….. …………………………………………… timing () { related_pin : "A"; when : "!B"; sdf_cond : "(B == 1'b0)"; timing_sense : positive_unate; cell_fall(Timing_data_X1) { values ("0.036818,0.038956, …….. ……………………………………………

41. Negative Delays A large input slope and a cell that reacts either very quickly

42. Load Cap Characterization When output slew transition = Max_Slew(max_tout), the output loading = Max_load

43. Tri State Delay Measurement Cannot be measured using conventional voltage levels Measured by looking at the current through the output pin. Test Equipment consists of Current detector on the output of the tristate cell Pull-up and pull-down resistors that can be switched on/off independently

44. Measuring Normal-tri state delays Switch on both pull-up and pull-down resistors; produce a short current flows at the output pin. When the cell enters tristate mode the output pin will be isolated from the rest of the cell, the path from supply to output cut, and current through the output pin will stop. Current monitoring device detects when the value goes below a certain threshold (pre-defined) which is the required delay.

45. Tri State to High state delays Activate only the pull-down resistor Switch off the pull-down resistor Push the Circuit into Tri State Mode Enable the cell so that output rise ‘s

46. References Sung Mo Kang and Yusuf Leblebici, "CMOS Digital Integrated Circuits-Analysis and Design", Tata McGraw Hill, Third Edition, New Delhi, 2003 J. Bhasker & RakeshChadha, “Static Timing Analysis for Nanometer Designs: A Practical Approach” Jan M. Rabaey, AnanthaChandrakasan, and BorivojeNikolic, “Digital Integrated Circuits: A Design Perspective” RACHITH I. KUSHALAPPA, "AutoLibGen : An open source tool for automation of Standard Cell Library characterization for VDSM designs", M.E Thesis, NITK Surathkal, 2008 NARESH ANNE, "Design and Characterization of a standard cell library for the freePDK 45 process ", M.S Thesis, Oklahoma State University, 2010 (link)

47. References…. HSpice Simulation and Analysis Users Guide, Version Y-2006.09, Sep 2006 Synopsys NCX User guide, Version B-2008.12, December 2008 An Excellent Lecture on Leakage power & possible reduction Techniques by R. Saleh, Uni of British Columbia (Link) Nangate 45nm Open Cell Library (link) Excellent Tutorial on HSPICE (Link) LTSPICE Yahoo Group (Link) Last, but not the least, extensive knowledge I gained by interacting with Library char teams @ NXP, Cypress & ST microelectronics which can’t be put in words