In this course, you
● Identify and apply timing arc information from a library, such as unateness, delays, and slew
● Identify cell delays from a library and calculate output slew degradation
● Use wire-load information to calculate net delays
● Identify the properties of a clock, including period, edges, and slew, and calculate the duty cycle
● Apply setup and hold checks to diagnose design violations
● Identify timing path types to calculate slack values
● Set environmental constraints, clocks constraints, and path exceptions
● Constrain a design using SDC
● Analyze reports to identify timing problems
Timing and Design Closure in Physical Design Flows Olivier Coudert
A physical design flow consists of producing a production-worthy layout from a gate-level netlist subject to a set of constraints. We focus on the problems imposed by shrinking process technologies. It exposes the problems of timing closure, signal integrity, design variable dependencies, clock and power/ground routing, and design signoff. It also surveys some physical design flows, and outlines a refinement-based flow.
A typical design flow follows the below structure and can be broken down into multiple steps. Some of these phases happen in parallel and some in sequentially.
Requirements
A customer of a semiconductor firm is typically some other company who plans to use the chip in its systems or end products. So, the customer's requirements also play an important role in deciding how the chip should be designed.
The first step is to collect the requirements, estimate the end product's market value, and evaluate the number of resources required to do the project.
Specifications
The next step is to collect specifications that describe the functionality, interface abstractly, and over all architecture of the chip to be designed. This can be something along the lines such as:
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Requires computational power to run imaging algorithms to support virtual reality.
Requires two ARM A53 processors with coherent interconnect and should run at 600 MHz.
Requires USB 3.0, Bluetooth, and PCIe 2nd gen interfaces.
It should support 1920x1080 pixel displays with an appropriate controller.
Digital Design
Because of the complex nature of modern chips, it's impossible to build something from scratch, and in many cases, many components will be reused.
For example, company A requires a FlexCAN module to interact with other modules in an automobile. They can either buy the FlexCAN design from another company to save time and effort or spend resources to build one.
It's not practical to design such a system from basic building blocks such as flip-flops and CMOS transistors.
Instead, a behavioral description is developed to analyze the design in terms of functionality, performance, and other high-level issues using a Hardware Description Language such as Verilog or VHDL.
This is usually done by a digital designer and is similar to a high-level computer programmer equipped with digital electronics skills.
Verification
Once the RTL design is ready, it needs to be verified for functional correctness.
For example, a DSP processor is expected to issue bus transactions with fetching instructions from memory and know that this will happen as expected.
The functional verification is required at this point, which is done with EDA simulators' help that can model the design and apply a different stimulus to it. This is the job of a pre-silicon verification engineer.
Logic Synthesis
Now we will convert this design into hardware schematic with real elements such as combinational gates and flip-flops. This step is called synthesis.
Logic synthesis tools enable the conversion of RTL description in HDL to a gate-level netlist. This netlist is a description of the circuit in terms of gates and connections between them.
Logic synthesis tools ensure that the netlist meets timing, area, and power specifications. Typically, they have access to different technology node
Placement is the process of determining the locations of circuit devices on a die surface. It is an important stage in the VLSI design flow, because it affects routabil- ity, performance, heat distribution, and to a less extent, power consumption of a design.
In semiconductor design, standard-cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard-cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate).
Cell-based methodology – the general class to which standard cells belong – makes it possible for one designer to focus on the high-level (logical function) aspect of digital design, while another designer focuses on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard-cell methodology has helped designers scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate system-on-a-chip (SoC) devices.
In electronics, crosstalk is any phenomenon by which a signal transmitted on one circuit or channel of a transmission system creates an undesired effect in another circuit or channel. Crosstalk is usually caused by undesired capacitive, inductive, or conductive coupling from one circuit or channel to another.
Crosstalk is a significant issue in structured cabling, audio electronics, integrated circuit design, wireless communication and other communications systems.
Before 2000 area, delay and performance were the most important parameters, if anyone design circuit the main focus was on how much less area is occupied by the circuit on the chip and what the speed is. Now situation is changed, the performance and speed is a secondary concern. In all nanometer (deep sub-micron) technology power becomes the most important parameter in the design. Almost all portable devices run on battery power. Power consumption is a very big challenge in modern-day VLSI design as technology is going to shrinks Because of
Increasing transistors count on small chip
Higher speed of operations
Greater device leakage currents
Timing and Design Closure in Physical Design Flows Olivier Coudert
A physical design flow consists of producing a production-worthy layout from a gate-level netlist subject to a set of constraints. We focus on the problems imposed by shrinking process technologies. It exposes the problems of timing closure, signal integrity, design variable dependencies, clock and power/ground routing, and design signoff. It also surveys some physical design flows, and outlines a refinement-based flow.
A typical design flow follows the below structure and can be broken down into multiple steps. Some of these phases happen in parallel and some in sequentially.
Requirements
A customer of a semiconductor firm is typically some other company who plans to use the chip in its systems or end products. So, the customer's requirements also play an important role in deciding how the chip should be designed.
The first step is to collect the requirements, estimate the end product's market value, and evaluate the number of resources required to do the project.
Specifications
The next step is to collect specifications that describe the functionality, interface abstractly, and over all architecture of the chip to be designed. This can be something along the lines such as:
Play
Next
Unmute
Current TimeÂ
0:00
/
DurationÂ
18:10
Â
Fullscreen
Backward Skip 10s
Play Video
Forward Skip 10s
Requires computational power to run imaging algorithms to support virtual reality.
Requires two ARM A53 processors with coherent interconnect and should run at 600 MHz.
Requires USB 3.0, Bluetooth, and PCIe 2nd gen interfaces.
It should support 1920x1080 pixel displays with an appropriate controller.
Digital Design
Because of the complex nature of modern chips, it's impossible to build something from scratch, and in many cases, many components will be reused.
For example, company A requires a FlexCAN module to interact with other modules in an automobile. They can either buy the FlexCAN design from another company to save time and effort or spend resources to build one.
It's not practical to design such a system from basic building blocks such as flip-flops and CMOS transistors.
Instead, a behavioral description is developed to analyze the design in terms of functionality, performance, and other high-level issues using a Hardware Description Language such as Verilog or VHDL.
This is usually done by a digital designer and is similar to a high-level computer programmer equipped with digital electronics skills.
Verification
Once the RTL design is ready, it needs to be verified for functional correctness.
For example, a DSP processor is expected to issue bus transactions with fetching instructions from memory and know that this will happen as expected.
The functional verification is required at this point, which is done with EDA simulators' help that can model the design and apply a different stimulus to it. This is the job of a pre-silicon verification engineer.
Logic Synthesis
Now we will convert this design into hardware schematic with real elements such as combinational gates and flip-flops. This step is called synthesis.
Logic synthesis tools enable the conversion of RTL description in HDL to a gate-level netlist. This netlist is a description of the circuit in terms of gates and connections between them.
Logic synthesis tools ensure that the netlist meets timing, area, and power specifications. Typically, they have access to different technology node
Placement is the process of determining the locations of circuit devices on a die surface. It is an important stage in the VLSI design flow, because it affects routabil- ity, performance, heat distribution, and to a less extent, power consumption of a design.
In semiconductor design, standard-cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard-cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate).
Cell-based methodology – the general class to which standard cells belong – makes it possible for one designer to focus on the high-level (logical function) aspect of digital design, while another designer focuses on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard-cell methodology has helped designers scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate system-on-a-chip (SoC) devices.
In electronics, crosstalk is any phenomenon by which a signal transmitted on one circuit or channel of a transmission system creates an undesired effect in another circuit or channel. Crosstalk is usually caused by undesired capacitive, inductive, or conductive coupling from one circuit or channel to another.
Crosstalk is a significant issue in structured cabling, audio electronics, integrated circuit design, wireless communication and other communications systems.
Before 2000 area, delay and performance were the most important parameters, if anyone design circuit the main focus was on how much less area is occupied by the circuit on the chip and what the speed is. Now situation is changed, the performance and speed is a secondary concern. In all nanometer (deep sub-micron) technology power becomes the most important parameter in the design. Almost all portable devices run on battery power. Power consumption is a very big challenge in modern-day VLSI design as technology is going to shrinks Because of
Increasing transistors count on small chip
Higher speed of operations
Greater device leakage currents
Equivalence checking is a portion of a larger discipline called formal verification. This technology uses mathematical modeling techniques to prove that two representations of design exhibit the same behavior. This approach should not be confused with functional verification, which uses exhaustive simulation to verify the correctness of a design.
Once a verified version of a design has been identified, equivalence checking can be used to determine if an alternate representation of the design behaves the same as the verified version. This technique does not use input vectors so it is more efficient.
Equivalence checking is useful to verify that a design’s function has not changed after an operation like synthesis, or after a functional ECO has been applied.
Formal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated circuits, to formally prove that two representations of a circuit design exhibit exactly the same behavior.
Routing is an important step in the design of integrated circuits. It involves generating metal wires to connect the pins of same signal while obeying manufacturing design rules. Before routing is performed on the design, cell placement has to be carried out wherein the cells used in the design are placed. But the connections between the pins of the cells pertaining to same signal need to be made. At the time of placement, there are only logical connections between these pins. The physical connections are made by routing. More generally speaking, routing is to locate a set of wires in routing space so as to connect all the nets in the netlist taking into consideration routing channels’ capacities, wire widths and crossings etc. The objective of routing is to minimize total wire length and number of vias and that each net meets its timing budget. The tools that perform routing are termed as routers. You typically provide them with a placed netlist along with list of timing critical nets. These tools, in turn, provide you with the geometry of all the nets in the design.
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
Today, ASIC design flow is a very mature process in silicon turnkey design. The ASIC design flow and its various steps in VLSI engineering that we describe below are based on best practices and proven methodologies in ASIC chip designs. This blog attempts to explain different steps in the ASIC design flow, starting from ASIC design concept and moving from specifications to benefits.
To ensure successful ASIC design, engineers must follow a proven ASIC design flow which is based on a good understanding of ASIC specifications, requirements, low power design and performance, with a focus on meeting the goal of right time to market. Every stage of ASIC design cycle has EDA tools that can help to implement ASIC design with ease.
In today’s world, there is an ever-increasing demand for SOC speed, performance, and features. To cater to all those needs, the industry is moving toward lower technology nodes. The current market has become more and more demanding, in turn forcing complex architectures and reduced time to market. The complex integrations and smaller design cycle emphasize the importance of floorplanning, i.e., the first step in netlist-to-GDSII design flow. Floorplanning not only captures designer’s intent, but also presents the challenges and opportunities that affect the entire design flow, from design to implementation and chip assembly.
A typical SOC can include many hard- and soft-IP macros, memories, analog blocks, and multiple power domains. Because of the increases in gate count, power domains, power modes, and special architectural requirements, most SOCs these days are hierarchical designs. The SOC interacts with the outside world through sensors, antennas, displays, and other elements, which introduce a lot of analog component in the chip. All of these limitations directly result in various challenges in floorplanning.
Floorplanning includes macro/block placement, design partitioning, pin placement, power planning, and power grid design. What make the job more important is that the decisions taken for macro/block placement, partitioning, I/O-pad placement, and power planning directly or indirectly impact the overall implementation cycle.
Lots of iterations happen to get an optimum floorplan. The designer takes care of the design parameters, such as power, area, timing, and performance during floorplanning. These estimations are repeatedly reviewed, based on the feedback of other stakeholders such as the implementation team, IP owners, and RTL designers. The outcome of floorplanning is a proper arrangement of macros/blocks, power grid, pin placement, and partitioned blocks that can be implemented in parallel.
In hierarchical designs, the quality of the floorplan is analyzed after the blocks are integrated at the top level. That can results in unnecessary iterative work, wasted resource hours, and longer cycle times, which could mean missed market opportunities. This underscores the importance of floorplanning.
In this paper, we will discuss some of the good practices, techniques, and complex cases that arise while floorplanning in an SOC.
The first rule of thumb for floorplanning is to arrange the hard macros and memories in such a manner that you end up with a core area (to be used for SOG placement) square in shape. This is always not possible, however, because of the large number of analog-IP blocks, memories, and various other requirements in design.
Clock Tree Synthesis is a technique for distributing the clock equally among all sequential parts of a VLSI design. The purpose of Clock Tree Synthesis is to reduce skew and delay. Clock Tree Synthesis is provided the placement data as well as the clock tree limitations as input. Clock Tree Synthesis (CTS) is the technique of balancing the clock delay to all clock inputs by inserting buffers/inverters along the clock routes of an ASIC design. As a result, CTS is used to balance the skew and reduce insertion latency. Before Clock Tree Synthesis, all clock pins were driven by a single clock source. Clock tree synthesis includes both clock tree construction and clock tree balance. Clock tree inverters may be used to create a clock tree that maintains the correct transition (duty cycle), and clock tree buffers (CTB) can balance the clock tree to fulfil the skew and latency requirements. To fulfil the space and power limits, fewer clock tree inverters and buffers should be employed.
In the world of Very Large Scale Integration (VLSI), the Physical Design process plays a crucial role in transforming a logical design into a physical layout that can be manufactured. Among the various steps involved in the Physical Design flow, Place and Route (PnR) stand out as a critical phase. PnR consists in placing the different components of a design on a chip and routing the connections between them. In this article, we will delve into the PnR flow, exploring its key steps, challenges, and the tools involved.
1. Partitioning:
Partitioning is a preliminary step in the PnR flow that divides the design into manageable blocks or modules based on functionality, hierarchy, or timing constraints. It enables parallel processing during subsequent steps and facilitates easier placement and routing. Partitioning algorithms aim to balance the workload across partitions and minimize inter-partition communication.
2. Floorplanning:
Floorplanning is a critical aspect of the placement process, defining the overall chip's top-level structure and organizing the different functional blocks. It involves allocating space for each block, determining their relative positions, and defining the placement regions. Effective floorplanning ensures proper utilization of available chip areas, reduces congestion, and facilitates efficient routing.
3. Power Planning:
Power planning focuses on distributing power supply and ensuring a stable power delivery network throughout the chip. It involves inserting power distribution networks, decoupling capacitors, and voltage regulators to minimize voltage drop, signal noise, and power supply fluctuations. Power planning techniques aim to optimize power grid layout, reduce IR drop, and mitigate electromigration issues.
4. Placement:
Placement is the first step in the PnR flow and involves determining the optimal location for each logic component on the chip. The primary objective of placement is to minimize wire length, power consumption, and timing delays while adhering to various constraints such as blockages, power grid, and signal integrity.
5. Clock Tree Synthesis (CTS):
Clock Tree Synthesis is a crucial step in PnR flow that ensures the efficient distribution of clock signals to all sequential elements of the design. CTS aims to minimize clock skew, and power dissipation, and provide a balanced clock network. CTS algorithms construct a tree-like structure by inserting buffers and optimizing wire length to achieve reliable clock distribution.
6. Routing:
6.1 Global Routing:
Once the placement is complete, the next step is global routing, which establishes the connections between the placed components. Global routing generates a coarse routing structure using minimum spanning trees, maze routing, or other algorithms. It focuses on achieving reasonable wirelength and reducing congestion without considering the precise details of the interconnects.
Fusion Compiler is the next-generation RTL-to-GDSII implementation system architected to address the complexities of advanced node designs and deliver up to 20% improved PPA while reducing Time To Results (TTR) by 2X.
Physical verification will verify that the post-layout netlist and the layout are equivalent. i.e. all connections specified in the netlist is present in the layout. This article explains physical verification.
https://www.udemy.com/vlsi-academy
Usually, while drawing any circuit on paper, we have only one 'vdd' at the top and one 'vss' at the bottom. But on a chip, it becomes necessary to have a grid structure of power, with more than one 'vdd' and 'vss'. The concept of power grid structure would be uploaded soon. It is actually the scaling trend that drives chip designers for power grid structure.
CMOS Analog IC design by Dr GS Javed - Refresher Course - Batch 1Javed G S, PhD
Topics covered in the course
1. DC Biasing of the circuits
2. Circuits for reference voltage and current generation
-Voltage Regulator
-BGR
-LDO
-V-to-I
3. Precision Current References
4. Opamp design for Analog to digital converters
- OTA
- Buffer
- Unity Feedback OTA
- Layout design strategies – 2stage opamp + CMFB
5. Sense and Return mechanisms in Feedback circuits
- Current and Voltage circuits
6. Sub-Threshold Conduction
- Low voltage Operation
7. ADC Design and Simulation
-Near Nyquist performance of Opamp for ADC Circuits
-Spectral Analysis and No. of FFT Points for simulation
-Simulation time for performance
-Resistors – their variation and Calibration
-Switch design for S/H
-CDAC
8. On-Chip Inductors
Visit https://www.vlsiuniverse.com/
https://www.vlsiuniverse.com/2020/05/complete-asic-design-flow.html
This is the standard VLSI design flow that every semiconductor company follows. The complete ASIC design flow is explained by considering each and every stage.
Equivalence checking is a portion of a larger discipline called formal verification. This technology uses mathematical modeling techniques to prove that two representations of design exhibit the same behavior. This approach should not be confused with functional verification, which uses exhaustive simulation to verify the correctness of a design.
Once a verified version of a design has been identified, equivalence checking can be used to determine if an alternate representation of the design behaves the same as the verified version. This technique does not use input vectors so it is more efficient.
Equivalence checking is useful to verify that a design’s function has not changed after an operation like synthesis, or after a functional ECO has been applied.
Formal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated circuits, to formally prove that two representations of a circuit design exhibit exactly the same behavior.
Routing is an important step in the design of integrated circuits. It involves generating metal wires to connect the pins of same signal while obeying manufacturing design rules. Before routing is performed on the design, cell placement has to be carried out wherein the cells used in the design are placed. But the connections between the pins of the cells pertaining to same signal need to be made. At the time of placement, there are only logical connections between these pins. The physical connections are made by routing. More generally speaking, routing is to locate a set of wires in routing space so as to connect all the nets in the netlist taking into consideration routing channels’ capacities, wire widths and crossings etc. The objective of routing is to minimize total wire length and number of vias and that each net meets its timing budget. The tools that perform routing are termed as routers. You typically provide them with a placed netlist along with list of timing critical nets. These tools, in turn, provide you with the geometry of all the nets in the design.
The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
Today, ASIC design flow is a very mature process in silicon turnkey design. The ASIC design flow and its various steps in VLSI engineering that we describe below are based on best practices and proven methodologies in ASIC chip designs. This blog attempts to explain different steps in the ASIC design flow, starting from ASIC design concept and moving from specifications to benefits.
To ensure successful ASIC design, engineers must follow a proven ASIC design flow which is based on a good understanding of ASIC specifications, requirements, low power design and performance, with a focus on meeting the goal of right time to market. Every stage of ASIC design cycle has EDA tools that can help to implement ASIC design with ease.
In today’s world, there is an ever-increasing demand for SOC speed, performance, and features. To cater to all those needs, the industry is moving toward lower technology nodes. The current market has become more and more demanding, in turn forcing complex architectures and reduced time to market. The complex integrations and smaller design cycle emphasize the importance of floorplanning, i.e., the first step in netlist-to-GDSII design flow. Floorplanning not only captures designer’s intent, but also presents the challenges and opportunities that affect the entire design flow, from design to implementation and chip assembly.
A typical SOC can include many hard- and soft-IP macros, memories, analog blocks, and multiple power domains. Because of the increases in gate count, power domains, power modes, and special architectural requirements, most SOCs these days are hierarchical designs. The SOC interacts with the outside world through sensors, antennas, displays, and other elements, which introduce a lot of analog component in the chip. All of these limitations directly result in various challenges in floorplanning.
Floorplanning includes macro/block placement, design partitioning, pin placement, power planning, and power grid design. What make the job more important is that the decisions taken for macro/block placement, partitioning, I/O-pad placement, and power planning directly or indirectly impact the overall implementation cycle.
Lots of iterations happen to get an optimum floorplan. The designer takes care of the design parameters, such as power, area, timing, and performance during floorplanning. These estimations are repeatedly reviewed, based on the feedback of other stakeholders such as the implementation team, IP owners, and RTL designers. The outcome of floorplanning is a proper arrangement of macros/blocks, power grid, pin placement, and partitioned blocks that can be implemented in parallel.
In hierarchical designs, the quality of the floorplan is analyzed after the blocks are integrated at the top level. That can results in unnecessary iterative work, wasted resource hours, and longer cycle times, which could mean missed market opportunities. This underscores the importance of floorplanning.
In this paper, we will discuss some of the good practices, techniques, and complex cases that arise while floorplanning in an SOC.
The first rule of thumb for floorplanning is to arrange the hard macros and memories in such a manner that you end up with a core area (to be used for SOG placement) square in shape. This is always not possible, however, because of the large number of analog-IP blocks, memories, and various other requirements in design.
Clock Tree Synthesis is a technique for distributing the clock equally among all sequential parts of a VLSI design. The purpose of Clock Tree Synthesis is to reduce skew and delay. Clock Tree Synthesis is provided the placement data as well as the clock tree limitations as input. Clock Tree Synthesis (CTS) is the technique of balancing the clock delay to all clock inputs by inserting buffers/inverters along the clock routes of an ASIC design. As a result, CTS is used to balance the skew and reduce insertion latency. Before Clock Tree Synthesis, all clock pins were driven by a single clock source. Clock tree synthesis includes both clock tree construction and clock tree balance. Clock tree inverters may be used to create a clock tree that maintains the correct transition (duty cycle), and clock tree buffers (CTB) can balance the clock tree to fulfil the skew and latency requirements. To fulfil the space and power limits, fewer clock tree inverters and buffers should be employed.
In the world of Very Large Scale Integration (VLSI), the Physical Design process plays a crucial role in transforming a logical design into a physical layout that can be manufactured. Among the various steps involved in the Physical Design flow, Place and Route (PnR) stand out as a critical phase. PnR consists in placing the different components of a design on a chip and routing the connections between them. In this article, we will delve into the PnR flow, exploring its key steps, challenges, and the tools involved.
1. Partitioning:
Partitioning is a preliminary step in the PnR flow that divides the design into manageable blocks or modules based on functionality, hierarchy, or timing constraints. It enables parallel processing during subsequent steps and facilitates easier placement and routing. Partitioning algorithms aim to balance the workload across partitions and minimize inter-partition communication.
2. Floorplanning:
Floorplanning is a critical aspect of the placement process, defining the overall chip's top-level structure and organizing the different functional blocks. It involves allocating space for each block, determining their relative positions, and defining the placement regions. Effective floorplanning ensures proper utilization of available chip areas, reduces congestion, and facilitates efficient routing.
3. Power Planning:
Power planning focuses on distributing power supply and ensuring a stable power delivery network throughout the chip. It involves inserting power distribution networks, decoupling capacitors, and voltage regulators to minimize voltage drop, signal noise, and power supply fluctuations. Power planning techniques aim to optimize power grid layout, reduce IR drop, and mitigate electromigration issues.
4. Placement:
Placement is the first step in the PnR flow and involves determining the optimal location for each logic component on the chip. The primary objective of placement is to minimize wire length, power consumption, and timing delays while adhering to various constraints such as blockages, power grid, and signal integrity.
5. Clock Tree Synthesis (CTS):
Clock Tree Synthesis is a crucial step in PnR flow that ensures the efficient distribution of clock signals to all sequential elements of the design. CTS aims to minimize clock skew, and power dissipation, and provide a balanced clock network. CTS algorithms construct a tree-like structure by inserting buffers and optimizing wire length to achieve reliable clock distribution.
6. Routing:
6.1 Global Routing:
Once the placement is complete, the next step is global routing, which establishes the connections between the placed components. Global routing generates a coarse routing structure using minimum spanning trees, maze routing, or other algorithms. It focuses on achieving reasonable wirelength and reducing congestion without considering the precise details of the interconnects.
Fusion Compiler is the next-generation RTL-to-GDSII implementation system architected to address the complexities of advanced node designs and deliver up to 20% improved PPA while reducing Time To Results (TTR) by 2X.
Physical verification will verify that the post-layout netlist and the layout are equivalent. i.e. all connections specified in the netlist is present in the layout. This article explains physical verification.
https://www.udemy.com/vlsi-academy
Usually, while drawing any circuit on paper, we have only one 'vdd' at the top and one 'vss' at the bottom. But on a chip, it becomes necessary to have a grid structure of power, with more than one 'vdd' and 'vss'. The concept of power grid structure would be uploaded soon. It is actually the scaling trend that drives chip designers for power grid structure.
CMOS Analog IC design by Dr GS Javed - Refresher Course - Batch 1Javed G S, PhD
Topics covered in the course
1. DC Biasing of the circuits
2. Circuits for reference voltage and current generation
-Voltage Regulator
-BGR
-LDO
-V-to-I
3. Precision Current References
4. Opamp design for Analog to digital converters
- OTA
- Buffer
- Unity Feedback OTA
- Layout design strategies – 2stage opamp + CMFB
5. Sense and Return mechanisms in Feedback circuits
- Current and Voltage circuits
6. Sub-Threshold Conduction
- Low voltage Operation
7. ADC Design and Simulation
-Near Nyquist performance of Opamp for ADC Circuits
-Spectral Analysis and No. of FFT Points for simulation
-Simulation time for performance
-Resistors – their variation and Calibration
-Switch design for S/H
-CDAC
8. On-Chip Inductors
Visit https://www.vlsiuniverse.com/
https://www.vlsiuniverse.com/2020/05/complete-asic-design-flow.html
This is the standard VLSI design flow that every semiconductor company follows. The complete ASIC design flow is explained by considering each and every stage.
Low Power VLSI design architecture for EDA (Electronic Design Automation) and Modern Power Estimation, Reduction and Fixing technologies including clock gating and power gating
AgileSwitch manufacturers SiC MOSFET Gate Drivers for leading SiC module manufacturers in the industry - Wolfspeed, Semikron, Rohm. Using patented technology AgileSwitch has built a driver with fault monitoring the prevent catastrophic conditions damaging your modules.
This chapter contains information for memory compilers available in STDL80 cell library. These are
complete compilers that consist of various generators to satisfy the requirements of the circuit at hand. Each
of the final building block, the physical layout, will be implemented as a stand-alone, densely packed,
pitch-matched array. Using this complex layout generator and adopting state-of-the-art logic and circuit
design technique, these memory cells can realize extreme density and performance. In each layout
generator, we added an option which makes the aspect ratio of the physical layout selectable so that the
ASIC designers can choose the aspect ratio according to the convenience of the chip level layout.
Sign off in VLSI is used to represent the completion of the design process. It is the final stage of the design cycle, in which all aspects of the chip are verified to make sure it meets the desired specifications. Sign off includes the physical verification of the design, the timing verification of the design, the power verification of the design, and the electrical verification of the design. Once all these verifications are completed and the chip is deemed to be functioning as expected, the design can be signed off
Routing in VLSI is making physical connections between signal pins using metal layers. Following Clock Tree Synthesis (CTS) and optimization, the routing step determines the exact pathways for interconnecting standard cells, macros, and I/O pins.
Global Routing
first partitions the routing region into tiles/rectangles called global routing cells (gcells) and decides tile-to-tile paths for all nets while attempting to optimize some given objective function (e.g., total wire length and circuit timing), but doesn’t make actual connections or assign nets to specific paths within the routing regions.
By default, the width of a gcells is same as the height of a standard cell and is aligned with the standard cell rows.
Every gcell having the a number of horizontal routing resources and vertical routing resources.
Global routing assigns nets (logical connectivity not metal connectivity) to specific metal layers and global routing cells.
Track Assignment
Track assignment is a stage wherein the routing tracks are assigned for each global routes. The tasks that are performed during this stage are as follows
Assigning tracks in horizontal and vertical partitions.
Rerouting all overlapped wires.
Track Assignment replaces all global routes with actual metal layers.
Although all nets are routed (not very carefully), there will be many DRC, SI and timing related violations, especially in regions where the routing connects the pins. These violations are fixed in the succeeding stages.
Detail Routing
The detailed router uses the routing plan laid by the router during the Global Routing and Track Assignment and lays actually metal to logically connect pins with nets and other pins in the design.
The violations that were created during the Track Assignment stage are fixed through multiple iterations in this stage.
The main goal of detailed routing is to complete all the required interconnect without leaving shorts or spacing violations.
The detailed routing starts with the router dividing the block into specific areas called switch boxes or Sbox, which are generally expressed in terms of gcells.
Clock tree synthesis (CTS) plays an important role in building well-balanced clock tree, fixing timing violations and reducing the extra unnecessary pessimism in the design. The goal during building a clock tree is to reduce the skew, maintain symmetrical clock tree structure and to cover all the registers in the design. We have captured some problematic scenarios and the problem solving approaches in this article.
Clock tree network enables in making design clean from a timing perspective. However, it is responsible for more than one third of the total power consumption of the chip. The impact of variations in the clock path is more than 2 times the other paths in the design. These variations in-turn affects the timing paths. Let us take an example; Due to the variation, if the clock path to the launching register is slowed down by 100ps and the clock path to the capturing register is fastened by 100ps then it impacts the setup constraint by adding 200ps more to it, this in-turn affects the timing path by making it more critical. Here we can see the importance of building a balanced clock tree. We will discuss on the timing improvements and methods to reduce the variations in the clock tree. The steps followed in building a customized clock tree and the steps followed to bring down the variations in the clock tree has been depicted in the following sections.
Placement is the process of determining the locations of circuit devices on a die
surface. It is an important stage in the VLSI design flow, because it affects routability, performance, heat distribution, and to a less extent, power consumption of a
design. Traditionally, it is applied after the logic synthesis stage and before the
routing stage. Since the advent of deep submicron process technology around
the mid-1990s, interconnect delay, which is largely determined by placement,
has become the dominating component of circuit delay. As a result, placement
information is essential, even in early design stages, to achieve better circuit performance. In recent years, placement techniques have been integrated into the
logic synthesis stage to perform physical synthesis and into the architecture
design stage to perform physical-aware architecture design
In the VLSI Physical Design Stage, Floorplanning is an essential step, as it is an effective means to manage circuit design complexity, which is increasing with the advancement in technology. Floorplanning involves determining the locations, shape, size of modules in a chip and as such it estimates the chip area, delay and the wiring congestion, thereby providing a ground work for layout. Computationally, it is a NP hard problem. So many researchers from time to time have suggested various heuristics and metaheuristic approaches for solving the VLSI Floorplan Problem. The Floorplan representation is another important aspect of the Floorplanning Stage. Representations have a great impact on the complexity of the Floorplan design. In this paper, we survey the VLSI Floorplanning problem which includes studying and comparing the different optimization algorithms and the representations involved in the VLSI Floorplanning problem. Additionally we suggest some of the new approaches for solving the floorplanning problem which has not yet been employed in this regard.
Physical design means --->> netlist (.v ) converted into GDSII form(layout form)
logical connectivity of cells converted into physical connectivity.
During physical design, all design components are instantiated with their geometric representations. In other words, all macros, cells, gates, transistors, etc., with fixed shapes and sizes per fabrication layer, are assigned spatial locations (placement) and have appropriate routing connections (routing) completed in metal layers.
Physical design directly impacts circuit performance, area, reliability, power, and manufacturing yield. Examples of these impacts are discussed below.
Performance: long routes have significantly longer signal delays.
Area: placing connected modules far apart results in larger and slower chips.
Reliability: A large number of vias can significantly reduce the reliability of the circuit.
Power: transistors with smaller gate lengths achieve greater switching speeds at the cost of higher leakage current and manufacturing variability; larger transistors and longer wires result in greater dynamic power dissipation.
Yield: wires routed too close together may decrease yield due to electrical shorts occurring during manufacturing, but spreading gates too far apart may also undermine yield due to longer wires and a higher probability of opens
What is the Difference Between the target_library and link_library Variables?Ahmed Abdelazeem
Design Compiler already has the set target_library my_lib.db command.
Why is it necessary to also use the set link_library "* my_lib.db"
command? Can you explain the difference?
Makefiles are used to help decide which parts of a large program need to be recompiled. In the vast majority of cases, C or C++ files are compiled. Other languages typically have their own tools that serve a similar purpose as Make. Make can also be used beyond compilation too, when you need a series of instructions to run depending on what files have changed. This tutorial will focus on the C/C++ compilation use case.
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits.
In VLSI design, Design for Testability (DFT) is an approach that aims to make digital circuits easier to test during the manufacturing and debugging process. DFT in VLSI design involves incorporating additional circuitry and design features such as scan chains, built-in self-test (BIST) circuits, and boundary scan cells into the chip design to facilitate testing. Design for testability in VLSI design is essential to ensure that the fabricated chips are free from any kind of manufacturing defects. It also reduces the overall test time and thereby the cost of testing, and debugging. By incorporating DFT techniques into the chip design, it becomes easier to test the structural correctness of the chip, leading to higher-quality products and faster time-to-market.
Synthesis in VLSI is the process of converting your code (program) into a circuit. In terms of logic gates, synthesis is the process of translating an abstract design into a properly implemented chip. Hardware Description Languages (HDLs) are specific programming languages that are used to explain the hardware of a circuit, and the computer subsequently builds the circuit depending on the programme you provided. A “Gate Level Netlist” is what you get once you finish synthesising. This is how your circuit will appear. It demonstrates how everything is interconnected. You can alter it if you like; the computer just synthesizes this netlist based on its best judgement. The synthesizer generates better netlists as the abilities improve and they become more proficient at creating HDL programmes.
As we push through lower technology nodes in the IC and chip design, the wire width goes thinner along with transistor size. This makes the wire resistance more dominant on 16nm and below technology nodes. This increasing resistance and the decreasing width of metal wires introduce many Electromigration and IR drop issues. These two issues play major roles in reducing the lifespan of an electronic device and are the causes of functionality failure in any electronic devices with lower technology nodes.
In this article, we will discuss the problems of electromigration and IR drop, and techniques to prevent the occurrence of these issues in electronic devices.
Electromigration is the gradual displacement of metal atoms in a semiconductor. It occurs when the current density is high enough to cause the drift of metal ions in the direction of the electron flow, and is characterized by the ion flux density. This density depends on the magnitude of forces that tend to hold the ions in place, i.e., the nature of the conductor, crystal size, interface and grain-boundary chemistry, and the magnitude of forces that tend to dislodge them, including the current density, temperature and mechanical stresses.
The Power supply in the chip is distributed uniformly through metal layers (Vdd & Vss) across the design. These metal layers have finite amount of resistance. When voltage is applied to this metal wires current starts flowing through the metal layers and some voltage is dropped due to that resistance of metal wires and current. this drop is called as IR drop.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
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Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
1. Intro Arcs& Unateness Setup& Hold Paths SDC Report
Static Time Analysis
How to verify your chip timing
Ahmed Abdelazeem
Faculty of Engineering
Zagazig University
RTL2GDSII Flow, March 2022
Ahmed Abdelazeem ASIC Design Flow
2. Intro Arcs& Unateness Setup& Hold Paths SDC Report
Table of Contents
1 Introduction
2 Timing arcs and unateness:
3 TRANSMISSION GATE, D-LATCH, DFF,SETUP &HOLD
4 Timing Paths
5 Introduction to SDC Constraints
6 Analyzing a Timing Report
Ahmed Abdelazeem ASIC Design Flow
3. Intro Arcs& Unateness Setup& Hold Paths SDC Report STA Path-Based Constraint Inputs and Outputs Timing
Table of Contents
1 Introduction
2 Timing arcs and unateness:
3 TRANSMISSION GATE, D-LATCH, DFF,SETUP &HOLD
4 Timing Paths
5 Introduction to SDC Constraints
6 Analyzing a Timing Report
Ahmed Abdelazeem ASIC Design Flow
4. Intro Arcs& Unateness Setup& Hold Paths SDC Report STA Path-Based Constraint Inputs and Outputs Timing
What is Static Timing Analysis (STA)?
Static Timing Analysis (STA) is a method for determining if
a circuit meets timing constraints without having to simulate.
Static timing analysis:
Verifies Timing
verifies timing between synchronous clocks
does not verify functionality
Ahmed Abdelazeem ASIC Design Flow
5. Intro Arcs& Unateness Setup& Hold Paths SDC Report STA Path-Based Constraint Inputs and Outputs Timing
What is Static Timing Analysis (STA)?
Static Timing Analysis (STA) is a method for determining if
a circuit meets timing constraints without having to simulate.
Static timing analysis:
Verifies Timing
verifies timing between synchronous clocks
does not verify functionality
Is Exhaustive
uses formal, mathematical techniques instead of vectors
does not use dynamic logic simulation
Ahmed Abdelazeem ASIC Design Flow
6. Intro Arcs& Unateness Setup& Hold Paths SDC Report STA Path-Based Constraint Inputs and Outputs Timing
What is Static Timing Analysis (STA)?
Static Timing Analysis (STA) is a method for determining if
a circuit meets timing constraints without having to simulate.
Static timing analysis:
Verifies Timing
verifies timing between synchronous clocks
does not verify functionality
Is Exhaustive
uses formal, mathematical techniques instead of vectors
does not use dynamic logic simulation
Is Fast
significantly faster than gate level simulation
orders of magnitude Faster than Tx level (spice) simulation
Ahmed Abdelazeem ASIC Design Flow
7. Intro Arcs& Unateness Setup& Hold Paths SDC Report STA Path-Based Constraint Inputs and Outputs Timing
STA is Path-Based
STA identifies timing paths within design for analysis
Ahmed Abdelazeem ASIC Design Flow
8. Intro Arcs& Unateness Setup& Hold Paths SDC Report STA Path-Based Constraint Inputs and Outputs Timing
STA is Path-Based
STA identifies timing paths within design for analysis
Timing arcs within each path are calculated
Ahmed Abdelazeem ASIC Design Flow
9. Intro Arcs& Unateness Setup& Hold Paths SDC Report STA Path-Based Constraint Inputs and Outputs Timing
STA is Constraint Driven
STA in PT is constraint driven
PT does not report a path, by default, that is not constrained
for timing
Incomplete or inaccurate constraints will lead to incorrect
analysis and wasted runtime
Ahmed Abdelazeem ASIC Design Flow
10. Intro Arcs& Unateness Setup& Hold Paths SDC Report STA Path-Based Constraint Inputs and Outputs Timing
PrimeTime Inputs and Outputs
Ahmed Abdelazeem ASIC Design Flow
11. Intro Arcs& Unateness Setup& Hold Paths SDC Report STA Path-Based Constraint Inputs and Outputs Timing
Timing Analysis
Ahmed Abdelazeem ASIC Design Flow
12. Intro Arcs& Unateness Setup& Hold Paths SDC Report Arcs Unateness
Table of Contents
1 Introduction
2 Timing arcs and unateness:
3 TRANSMISSION GATE, D-LATCH, DFF,SETUP &HOLD
4 Timing Paths
5 Introduction to SDC Constraints
6 Analyzing a Timing Report
Ahmed Abdelazeem ASIC Design Flow
13. Intro Arcs& Unateness Setup& Hold Paths SDC Report Arcs Unateness
Timing arcs
Timing arcs
means a path from each input to each output of the cell.
Ahmed Abdelazeem ASIC Design Flow
14. Intro Arcs& Unateness Setup& Hold Paths SDC Report Arcs Unateness
Timing arcs
Timing arcs
means a path from each input to each output of the cell.
Combinational Cells has Timing Arcs from each Input to each
Output of the cell
Ahmed Abdelazeem ASIC Design Flow
15. Intro Arcs& Unateness Setup& Hold Paths SDC Report Arcs Unateness
Timing arcs
Timing arcs
means a path from each input to each output of the cell.
Combinational Cells has Timing Arcs from each Input to each
Output of the cell
Flip-flops have Timing Arcs from the Clock Input pin to Data
Output Q pin (Propagation delay/ Delay Arc) and from Clock
Input pin to Data Input D pin (setup, hold checks/ Constraint
Arc)
Ahmed Abdelazeem ASIC Design Flow
16. Intro Arcs& Unateness Setup& Hold Paths SDC Report Arcs Unateness
Timing arcs
Timing arcs
means a path from each input to each output of the cell.
Combinational Cells has Timing Arcs from each Input to each
Output of the cell
Flip-flops have Timing Arcs from the Clock Input pin to Data
Output Q pin (Propagation delay/ Delay Arc) and from Clock
Input pin to Data Input D pin (setup, hold checks/ Constraint
Arc)
Latches have 2 timing arcs:
Clock pin to Output Q pin, when D is stable
Data D pin to Output Q pin when D changes (Latch is
transparent)
Ahmed Abdelazeem ASIC Design Flow
17. Intro Arcs& Unateness Setup& Hold Paths SDC Report Arcs Unateness
Timing Unate
Unateness
How Output changes for different types of transitions on Input
Ahmed Abdelazeem ASIC Design Flow
18. Intro Arcs& Unateness Setup& Hold Paths SDC Report Arcs Unateness
Timing Unate
Unateness
How Output changes for different types of transitions on Input
Positive Unate if Output Transition is same as Input
Transition
Ahmed Abdelazeem ASIC Design Flow
19. Intro Arcs& Unateness Setup& Hold Paths SDC Report Arcs Unateness
Timing Unate
Unateness
How Output changes for different types of transitions on Input
Positive Unate if Output Transition is same as Input
Transition
Negative Unate if Output Transition opposite to Input
Transition
Ahmed Abdelazeem ASIC Design Flow
20. Intro Arcs& Unateness Setup& Hold Paths SDC Report Arcs Unateness
Timing Unate
Unateness
How Output changes for different types of transitions on Input
Positive Unate if Output Transition is same as Input
Transition
Negative Unate if Output Transition opposite to Input
Transition
Non-Unate if the Output Transition cannot be determined
solely from the direction of change of an Input. It also
depends upon the state of the other Inputs
Ahmed Abdelazeem ASIC Design Flow
21. Intro Arcs& Unateness Setup& Hold Paths SDC Report Arcs Unateness
Positive unate
If a rising transition on the input gives the output to rise and
falling transition on the input gives the output to fall i.e.
there is no change in transition of input and output then that
timing arc is called positive unate.
Timing Arc AND falling edge Timing Arc AND rising edge
Ahmed Abdelazeem ASIC Design Flow
22. Intro Arcs& Unateness Setup& Hold Paths SDC Report Arcs Unateness
Negative unate
If a rising transition on the input gives the output to fall and
falling transition on the input gives the output to rise i.e.
there is a change in transition of input and output then that
timing arc is called negative unate.
Timing Arc NAND falling edge Timing Arc NAND rising edge
Ahmed Abdelazeem ASIC Design Flow
23. Intro Arcs& Unateness Setup& Hold Paths SDC Report Arcs Unateness
Non-unate
The output transition cannot be determined by not only the
direction of an input but also depends on the state of the
other inputs.
Timing Arc XOR falling edge Timing Arc XOR rising edge
Ahmed Abdelazeem ASIC Design Flow
24. Intro Arcs& Unateness Setup& Hold Paths SDC Report TG latch DFF Definitions setup Hold
Table of Contents
1 Introduction
2 Timing arcs and unateness:
3 TRANSMISSION GATE, D-LATCH, DFF,SETUP &HOLD
4 Timing Paths
5 Introduction to SDC Constraints
6 Analyzing a Timing Report
Ahmed Abdelazeem ASIC Design Flow
25. Intro Arcs& Unateness Setup& Hold Paths SDC Report TG latch DFF Definitions setup Hold
Transmission Gate
The transmission gate is consists of a parallel connection of
PMOS & NMOS.
Two gate voltage of PMOS and NMOS are the complement
of each other
The effective resistance of the transmission gate is almost
constant because of the parallel connection of PMOS and
NMOS.
It is a bidirectional circuit and it carries the current in either
direction.
Ahmed Abdelazeem ASIC Design Flow
26. Intro Arcs& Unateness Setup& Hold Paths SDC Report TG latch DFF Definitions setup Hold
D Latch
The latch is a level-sensitive device and it is transparent when
the clock is high if it is a positive level-sensitive latch and
when the clock is low it is called negative level-sensitive latch.
In latch the output (Q) is dependent only on the level of the
clock (Clk). In this latch D is control the output (Q)
Ahmed Abdelazeem ASIC Design Flow
27. Intro Arcs& Unateness Setup& Hold Paths SDC Report TG latch DFF Definitions setup Hold
Positive/Negative D latch using transmission Gate
It consists of two transmission gates and two inverters.
Positive D-Latch Negative D-Latch
Ahmed Abdelazeem ASIC Design Flow
28. Intro Arcs& Unateness Setup& Hold Paths SDC Report TG latch DFF Definitions setup Hold
D Flip flop:
A D flip flop is an edge-triggered device which means the
output (Q) follows the input (D) only at the active edge (for
positive rising edge) of the clock (for the positive
edge-triggered) and retain the same value until the next rising
edge i.e. output does not change between two rising edges, it
should be changed only at the rising edge.
Ahmed Abdelazeem ASIC Design Flow
29. Intro Arcs& Unateness Setup& Hold Paths SDC Report TG latch DFF Definitions setup Hold
D Flip flop using a transmission gate
It is a combination of negative level-sensitive latch and
positive level-sensitive latch that giving an edge-sensitive
device. Data is change only at the active edge of the clock.
Ahmed Abdelazeem ASIC Design Flow
30. Intro Arcs& Unateness Setup& Hold Paths SDC Report TG latch DFF Definitions setup Hold
Timing Parameters, tcq
tcq is the time from the clock edge until the data appears at
the output
The tcq for rising and falling outputs is different
Ahmed Abdelazeem ASIC Design Flow
31. Intro Arcs& Unateness Setup& Hold Paths SDC Report TG latch DFF Definitions setup Hold
Timing Parameters, tsetup
tsetup - Setup time is the time the data has to arrive before
the clock to ensure correct sampling.
Ahmed Abdelazeem ASIC Design Flow
32. Intro Arcs& Unateness Setup& Hold Paths SDC Report TG latch DFF Definitions setup Hold
Timing Parameters, thold
thold - Hold time is the time the data has to be stable after
the clock to ensure correct sampling.
Ahmed Abdelazeem ASIC Design Flow
33. Intro Arcs& Unateness Setup& Hold Paths SDC Report TG latch DFF Definitions setup Hold
Understanding Launch and Capture Clock Edges
The launch clock is the clock signal that triggers the data.
The launch edge is the edge of the launch clock, which
triggers the data into the initial flop.
The capture clock is the clock that captures the data.
The capture edge is the edge of the capture clock, which
allows the data to be stored in the receiving flop
Ahmed Abdelazeem ASIC Design Flow
34. Intro Arcs& Unateness Setup& Hold Paths SDC Report TG latch DFF Definitions setup Hold
Setup (Max) Constraint
Setup time is the duration of time that the synchronous input
data must be stable before the triggering-edge of the clock.
Tclk + Tskew ≥ Tc2q + Tcomb + Tsetup
Ahmed Abdelazeem ASIC Design Flow
35. Intro Arcs& Unateness Setup& Hold Paths SDC Report TG latch DFF Definitions setup Hold
Hold (Min) Constraint
Hold time is the duration that the synchronous input (D)
must be stable after the triggering edge of the clock.
Thold + Tskew ≤ Tc2q + Tcomb
Ahmed Abdelazeem ASIC Design Flow
36. Intro Arcs& Unateness Setup& Hold Paths SDC Report Paths R2R IN2R R2OUT IN2OUT
Table of Contents
1 Introduction
2 Timing arcs and unateness:
3 TRANSMISSION GATE, D-LATCH, DFF,SETUP &HOLD
4 Timing Paths
5 Introduction to SDC Constraints
6 Analyzing a Timing Report
Ahmed Abdelazeem ASIC Design Flow
37. Intro Arcs& Unateness Setup& Hold Paths SDC Report Paths R2R IN2R R2OUT IN2OUT
What Are Timing Paths?
Timing path
A timing path is a combination of all the timing arcs from a start
point to an end point. You can break down timing paths into four
simple types or categories.
Ahmed Abdelazeem ASIC Design Flow
38. Intro Arcs& Unateness Setup& Hold Paths SDC Report Paths R2R IN2R R2OUT IN2OUT
Start Points
There are two types of start points in a timing path:
The input port of a design (other than a clock port).
The clock pin of a sequential cell.
Ahmed Abdelazeem ASIC Design Flow
39. Intro Arcs& Unateness Setup& Hold Paths SDC Report Paths R2R IN2R R2OUT IN2OUT
End Points
There are two types of End points in a timing path:
The Output port of a design .
The Data pin of a sequential cell.
Ahmed Abdelazeem ASIC Design Flow
40. Intro Arcs& Unateness Setup& Hold Paths SDC Report Paths R2R IN2R R2OUT IN2OUT
What Is Slack?
Slack
Required time is defined by the timing constraints like your clock
period. Arrival time is when the signal actually arrives.
Slack is defined as the difference between the required time and
the arrival time of a signal at the endpoint
Slack = Required Time – Arrival Time (setup)
Slack = Arrival Time – Required Time (hold)
The synthesis engine uses the slack value to identify the paths for
further optimization to meet timing or to reduce area.
The calculating equation for slack is different for the different
types of paths.
Ahmed Abdelazeem ASIC Design Flow
41. Intro Arcs& Unateness Setup& Hold Paths SDC Report Paths R2R IN2R R2OUT IN2OUT
How Do You Time Timing Paths?
Delay
To calculate the delay of a path, simply add the delays of all the
timing arcs in the path.
Calculate all the cell delays.
Cell delay timing arcs are determined by the type of cell delay
model used in the technology library
Calculate all the net delays.
Net delay timing arcs are determined by the layout estimator
or the wire-load model selected
Add all the cell and net delays together to arrive at the path
delay.
Ahmed Abdelazeem ASIC Design Flow
42. Intro Arcs& Unateness Setup& Hold Paths SDC Report Paths R2R IN2R R2OUT IN2OUT
Register-to-Register Setup Requirement
The following equation is the setup requirement for the
register-to-register path:
Required time = Clock Period + Skew – Setup Time
Arrival time = tCK2Q + Combo delay
Slack = Required time – Arrival time
Ahmed Abdelazeem ASIC Design Flow
43. Intro Arcs& Unateness Setup& Hold Paths SDC Report Paths R2R IN2R R2OUT IN2OUT
Register-to-Register Hold Requirement
The following equation is the Hold requirement for the
register-to-register path:
Required time = Hold Time + Skew
Arrival time = tCK2Q + Combo delay
Slack = Arrival time – Required time
Ahmed Abdelazeem ASIC Design Flow
44. Intro Arcs& Unateness Setup& Hold Paths SDC Report Paths R2R IN2R R2OUT IN2OUT
Input-to-Register Setup Requirement
The following equation is the setup requirement for the
input-to-register path:
Required time = Clock Period + Skew – Setup Time of R2
Arrival time = tCK2Q + Combo Delay 1 + Combo delay 2
Input Delay = clk to q + combo1
Slack = Required time – Arrival time
Ahmed Abdelazeem ASIC Design Flow
45. Intro Arcs& Unateness Setup& Hold Paths SDC Report Paths R2R IN2R R2OUT IN2OUT
Input-to-Register Hold Requirement
The following equation is the Hold requirement for the
input-to-register path:
Required time = Hold Time of R2 + Skew
Arrival time = Input delay + Combo delay
Input Delay = clk to q + combo1
Slack = Arrival time – Required time
Ahmed Abdelazeem ASIC Design Flow
46. Intro Arcs& Unateness Setup& Hold Paths SDC Report Paths R2R IN2R R2OUT IN2OUT
Register-to-Output Setup Requirement
The following equation is the setup requirement for the
register-to-output path:
Required time = Clock Period + Skew – Output Delay
Output Delay = combo 2 delay + setupR2
Arrival time = tCK2Q + Combo Delay 1
Slack = Required time – Arrival time
Ahmed Abdelazeem ASIC Design Flow
47. Intro Arcs& Unateness Setup& Hold Paths SDC Report Paths R2R IN2R R2OUT IN2OUT
Register-to-Output Hold Requirement
The following equation is the Hold requirement for the
register-to-output path:
Required time = Output Delay + Skew
output delay2 = combo 2 delay - holdR2
Arrival time = tCK2Q + Combo delay 1
Slack = Arrival time – Required time
Ahmed Abdelazeem ASIC Design Flow
48. Intro Arcs& Unateness Setup& Hold Paths SDC Report Paths R2R IN2R R2OUT IN2OUT
Input to Output Path Timing Requirement
Combinational paths have no clock defined. Therefore, you
need to use either a virtual clock or set max/min.
If you define a virtual clock or a dummy clock, then slack is
calculated as:
Slack = Clock Period – Input Delay – Output Delay –
Combinational Delay
Remember that input delay and output delay are set with
respect to a clock.
You can also set max/min delays using the following syntax:
set max delay
set mix delay
Then the slacks for the input to output paths are calculated
as below.
Setup (late) slack = max delay – combo delay
Hold (early) slack = min delay – combo delay
Ahmed Abdelazeem ASIC Design Flow
49. Intro Arcs& Unateness Setup& Hold Paths SDC Report Paths R2R IN2R R2OUT IN2OUT
Activity: Timing Paths
Here are the parameters for this activity:
The clock-to-Q delay of each flop is 0.5 ns.
The setup of each flop is 0.5 ns.
All input and output delays are 0.5 ns.
The clock period of Clk is 4 ns.
What is the worst timing slack based on this illustration?
Ahmed Abdelazeem ASIC Design Flow
50. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Table of Contents
1 Introduction
2 Timing arcs and unateness:
3 TRANSMISSION GATE, D-LATCH, DFF,SETUP &HOLD
4 Timing Paths
5 Introduction to SDC Constraints
6 Analyzing a Timing Report
Ahmed Abdelazeem ASIC Design Flow
51. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
What Are Constraints?
Constraints provide specifications that the design must meet
through optimization.
Typical examples of constraints are:
1 Clock constraints
2 External constraints
3 Power constraints
4 Net Delay constraints
5 Environmental constraints
6 Design rules for manufacturing
Ahmed Abdelazeem ASIC Design Flow
52. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Common SDC Constraints
1 Timing
create clock
create generated clock
set clock latency
set clock transition
set clock uncertainty
set input delay
set output delay
2 Exceptions
set false path
set multicycle path
set max delay
set mmin delay
3 Power
set max dynamic power
set max leakage power
4 Operating conditions
set operating conditions
5 Wire-load models
set wire load mode
set wire load model
6 Environmental
set driving cell
set input transition
set load
set fanout load
7 Design rules
set max capacitance
set max fanout
set max transition
Ahmed Abdelazeem ASIC Design Flow
55. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Design Objects [for all Synopsys tools]
Design: A circuit description that performs some logical
function.
Cell(Instants): It is the instantiated name of the sub-design
in the design.
Reference(Module): The original design to which the cell or
instance refers.
Port: These are the primary inputs, outputs or IO’s of the
design.
Pin: Pins are the input and output of cells (such as gates and
flip-flops) within a design. The ports of a sub-design are pins
within the parent design.
Net: Nets are the wires that connect ports to pins and pins to
each other.
Clock: The port or pin that is identified as a clock source.
Ahmed Abdelazeem ASIC Design Flow
56. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Timing Goals: Synchronous Designs
1 Synchronous Designs:
Data arrives from a clocked device
Data goes to a clocked device
2 Objective:
Define the timing constraints for all paths within a design:
all input logic paths
the internal (register to register) paths, and
all output paths
Ahmed Abdelazeem ASIC Design Flow
57. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Timing Goals: Synchronous Designs (cont)
Question
What information must you provide to constrain all the
register-to-register paths in your design?
Does the duty cycle of your clock matter?
Ahmed Abdelazeem ASIC Design Flow
58. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Defining a Clock
User MUST Define:
Clock Source (port or
pin)
Clock Period
User may also define:
Duty Cycle
Clock Name
Offset/Skew
dc_shell>create_clock -name CLK -period 10 [get_ports Clk]
dc_shell>set_dont_touch_network [get_clocks Clk]
Ahmed Abdelazeem ASIC Design Flow
59. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Default Clock Behavior
Defining the clock in a single-clock design constrains all
timing paths between registers for single-cycle, setup time
By default the clock rises at 0ns and has a 50% duty cycle
By default DC will not “buffer up” the clock network, even
when connected to many clock/enable pins of
flip-flops/latches
The clock network is treated as “ideal” - infinite drive
capability
1 Zero rise/fall transition times
2 Zero skew
3 Zero insertion delay or latency
Estimated skew, latency and transition times can, and should
be modeled for a more accurate representation of clock
behavior
Ahmed Abdelazeem ASIC Design Flow
60. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Modeling Clock Trees
Design Compiler is NOT used for synthesis of the clock tree
Clock tree synthesis is usually done by PnR tool, based on
physical placement data
Question
What design considerations need to be taken into account by the
synthesis tool, prior to layout?
Ahmed Abdelazeem ASIC Design Flow
61. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Modeling Uncertainty on Clock Edges
To account for varying delays between the clock network
branches (commonly called clock skew):
dc_shell>set_clock_uncertainty -setup 0.65 [get_clocks Clk]
dc_shell>set_clock_uncertainty -hold 0.45 [get_clocks CLlk]
Ahmed Abdelazeem ASIC Design Flow
62. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
set clock uncertainty and Setup Timing
Example
dc_shell> create_clock -period 10 [get_ports CLK]
dc_shell> set_clock_uncertainty 0.5 [get_clocks CLK]
Ahmed Abdelazeem ASIC Design Flow
63. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Setting Clock Transition
Transition models the rise and fall times of the clock
waveform at the register clock pins:
dc_shell>set_clock_transition 0.38 -rise [get_clocks Clk]
dc_shell>set_clock_transition 0.25 -fall [get_clocks Clk]
Ahmed Abdelazeem ASIC Design Flow
64. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Modeling Latency or Insertion Delay
Network latency models the average ‘internal’ delay from
the create clock port or pin to the register clock pins
Source latency models the delay from the actual clock origin
to the create clock port or pin:
dc_shell>create_clock -period 10 [get_ports CLK]
dc_shell>set_clock_latency -source {max 3 [get_clocks CLK]
dc_shell>set_clock_latency {max 1 [get_clocks CLK]
Ahmed Abdelazeem ASIC Design Flow
65. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Pre/Post Layout Clock
Synthesis Constraints
Example
reset_design
....
Post-CTS STA Constraints
Example
reset_design
.....
Ahmed Abdelazeem ASIC Design Flow
67. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Constraining Input Paths
Question
What information must you provide to constrain the input paths?
Ahmed Abdelazeem ASIC Design Flow
68. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Constraining Input Paths in DC
dc_shell> set_input_delay -max 4 -clock Clk [get_ports A]
The set input delay command constrains input paths
You specify how much time is
used by external logic...
DC calculates how much time
is left for the internal logic
Ahmed Abdelazeem ASIC Design Flow
69. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Constraining Input Paths
Question
What information must you provide to constrain the output paths?
Ahmed Abdelazeem ASIC Design Flow
70. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Constraining Output Paths in DC
dc_shell>set_output_delay -max 5.4 -clock Clk [get_ports B]
The set output delay command constrains input paths
You specify how much time is
needed by external logic...
DC calculates how much time
is left for internal logic
Ahmed Abdelazeem ASIC Design Flow
71. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Factors Affecting Timing
create_clock -period 2 [get_ports Clk]
set_input_delay -max 0.6 -clock Clk [get_ports A]
set_output_delay -max 0.8 -clock Clk [get_ports B]
Note
The above constraints are required, but not sufficient for DC to
accurately model and optimize all logic path delays. Need to take
into account: Input drivers/transition times, Output loading, PVT
corners and parasitic RCs
Ahmed Abdelazeem ASIC Design Flow
73. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Effect of Output Capacitive Load
Note
Capacitive loading on an output port affects the transition
time, and thereby the cell delay, of the output driver.
By default DC assumes zero capacitive loading on outputs. It
is therefore important to accurately model capacitive loading
on all outputs.
Ahmed Abdelazeem ASIC Design Flow
74. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Modeling Output Capacitive Load: Example 1
Spec:
Chip-level: Maximum capacitive load on output port B =
30fF
set_load [expr 30.0/1000] [get_ports B]
Question
What if a specific capacitance value is not known, at ablock-level
output port for example?
Ahmed Abdelazeem ASIC Design Flow
75. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Modeling Output Capacitive Load: Example 2
Spec:
Block-level: Maximum load on output port B = 1
“AN2”gate load, or= 3 “inv1a0”gates
Answer
Use load oflib/cell/pinto place the load of a gate from the
technology library on the port:
set_load [load_ofmy_lib/AN2/A][get_ports OUT1]
set_load [expr[load_of my_lib/inv1a0/A] * 3]
[get_ports OUT1]
Ahmed Abdelazeem ASIC Design Flow
76. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Effect of Input Transition Time
Note
Rise and fall transition times on an input port affect the cell
delay of the input gate.
By default DC assumes zero transition times on inputs. It is
therefore important to accurately model transition times on all
inputs.
Ahmed Abdelazeem ASIC Design Flow
77. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Modeling Input Transition: Example 1
Spec:
Chip-level: Maximum rise/fall input transition on input port
A = 0.12ns
set_input_transition 0.12 [get_ports A]
Question
What if a specific transition time value is not known, at a
block-level input port for example?
Ahmed Abdelazeem ASIC Design Flow
78. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Modeling Input Transition: Example 2
Spec:
Block-level: Maximum load on output port B = 1
“AN2”gate load, or= 3 “inv1a0”gates
set_driving_cell -lib_cell and2a0 [get_ports IN1]
Ahmed Abdelazeem ASIC Design Flow
80. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Variations in Cell Delays
Library cells are usually characterized using “nominal”
voltage and temperature:
nominal
nom process : 1.0;
nom temperature : 25.0;
nom voltage : 1.8;
Question
What if the circuit is to operate at a voltage and/or temperature
OTHER than nominal?
Ahmed Abdelazeem ASIC Design Flow
81. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Operating Conditions
The timing analysis tool resets itself when you switch between
operating conditions, and creates different timing data based
on the new library information.
Operating conditions are applied at the design level.
Nowadays, the technology library is created for a specific set
of operating conditions. Thus, specifying the library is
probably sufficient.
ASIC vendors might deliver multiple technology libraries,
defining:
best-case and worst-case operating conditions
optimistic and pessimistic WLM
minimum and maximum timing delay
set_min_library ssc_core_slow
-min_version ssc_core_fast
set_operating_conditions -max slow_125_1.62
-min fast_0_1.98
Ahmed Abdelazeem ASIC Design Flow
82. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Net delays
Ahmed Abdelazeem ASIC Design Flow
83. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Path Delays are Based on Cell + Net Delays
Cell and net delays are both a function of parasitic RCs
Ahmed Abdelazeem ASIC Design Flow
84. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Modeling Net RCswith Wire Load Models
A wire load model is an estimate of a net’s RC parasitics
based on the net’s fanout:
Models for various design sizes are supplied by your vendor
R/C values are average estimates based on data extracted
from similar designs which were fabricated using this process
Ahmed Abdelazeem ASIC Design Flow
85. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Wire Load Model Examples
Ahmed Abdelazeem ASIC Design Flow
86. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Specifying Wire Loads
Manual model selection
set_wire_load_model -name 8000000
Automatic model selection selects an appropriate wireload
model during compile:
Ahmed Abdelazeem ASIC Design Flow
87. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Wireload Model Mode
Specifies wire load model to use for nets that cross
hierarchical boundaries.
Example
set_wire_load_mode enclosed
Ahmed Abdelazeem ASIC Design Flow
88. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Time Budgeting
Question
What if you don’t know the delays on your inputs or the setup
requirements of your outputs?
Answer
Create a Time Budget !
Ahmed Abdelazeem ASIC Design Flow
89. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Time Budgeting (cont)
Note
Better to budget conservatively than to compile with paths
unconstrained!
Ahmed Abdelazeem ASIC Design Flow
91. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Load Budgeting
Question
What if, prior to compiling, the cells driving your inputs, and the
loads on your outputs are not known?
Answer
Create a Load Budget!
Ahmed Abdelazeem ASIC Design Flow
92. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Load Budgeting (cont)
Assume a weak cell driving the inputs, to be conservative
Limit the input capacitance of each input port
Estimate the number of other major blocks your outputs may
have to drive
Question
How do we limit the input capacitance of an input port?
A: Place restrictive design rules on our input ports
Ahmed Abdelazeem ASIC Design Flow
93. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Load Budget Example
Example Specification:
Inputs of any block shall present no more than the load of 10
“AND2” gates to their driving block
Outputs of any blocks will only be allowed to connect to a
maximum of 3 other blocks
Ahmed Abdelazeem ASIC Design Flow
95. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Asynchronous Multiple Clock Designs
Question
What do you do if the design has asynchronous clock sources?
Ahmed Abdelazeem ASIC Design Flow
96. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Synthesizing with Asynchronous Clocks
It is your responsibility to account for the
Instantiate double-clocking, metastable-hard Flip-Flops
dual-port FIFO, etc
Create clocks to constrain the paths within each clock domain
You must also disable timing-based synthesis on any path
which crosses an asynchronous clock boundary:
This will prevent DC from wasting time trying to get the
asynchronous path to “meet timing”
Ahmed Abdelazeem ASIC Design Flow
98. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Multi-Cycle Behavior
Situation: Not all paths operate at the target frequency of
the design
Choose one of the following options:
1 Add pipeline stage(s) to divide the logic into single-cycle paths
2 Ease off the single-cycle requirement: allow more clock cycles
Ahmed Abdelazeem ASIC Design Flow
99. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Timing with Multi-cycle Constraints
create_clock -period 10 [get_ports CLK]
set_multicycle_path {setup 6 -to FF4/D[*]
DC assumes change could occur near any clock edge causing
metastability!
Ahmed Abdelazeem ASIC Design Flow
100. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Default Hold Check
Why is hold check performed at 50 ns?
Ahmed Abdelazeem ASIC Design Flow
101. Intro Arcs& Unateness Setup& Hold Paths SDC Report Constraints Objects Clock Environmental Budgeting Excep.
Set the Proper Hold Constraint
set_multicycle_path -setup 6 -to FF4/D[*]
set_multicycle_path -hold 5 -to FF4/D[*]
Ahmed Abdelazeem ASIC Design Flow
102. Intro Arcs& Unateness Setup& Hold Paths SDC Report Report
Table of Contents
1 Introduction
2 Timing arcs and unateness:
3 TRANSMISSION GATE, D-LATCH, DFF,SETUP &HOLD
4 Timing Paths
5 Introduction to SDC Constraints
6 Analyzing a Timing Report
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103. Intro Arcs& Unateness Setup& Hold Paths SDC Report Report
DesignCompier Timing Reports
Users will typically access DesignTime via the report timing
command
The report timing command
The design is broken down into individual timing paths
Each timing path is timed out twice;
1 once for a rising edge input, and
2 once with a falling edge input
The critical path (worst violator) for each clock group is found
A timing report for each clock group is echoed to the screen
A DesignCompiler timing report has four major sections
Ahmed Abdelazeem ASIC Design Flow
104. Intro Arcs& Unateness Setup& Hold Paths SDC Report Report
Timing Report: Path Information Section
Ahmed Abdelazeem ASIC Design Flow
105. Intro Arcs& Unateness Setup& Hold Paths SDC Report Report
Timing Report: Path Delay Section
Ahmed Abdelazeem ASIC Design Flow
106. Intro Arcs& Unateness Setup& Hold Paths SDC Report Report
Timing Report: Path Required Section
Ahmed Abdelazeem ASIC Design Flow
107. Intro Arcs& Unateness Setup& Hold Paths SDC Report Report
Timing Report: Summary Section
Ahmed Abdelazeem ASIC Design Flow
108. Intro Arcs& Unateness Setup& Hold Paths SDC Report Report
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Ahmed Abdelazeem ASIC Design Flow