Si Intro(100413)

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Introduction of signal integrity.

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Si Intro(100413)

  1. 1. 13 th .Apr. 2010 In-myoung Song Tel : 82)10-9034-8480 E-mail : imsong91@gmail.com Introduction of Signal Integrity
  2. 2. Agenda <ul><li>Before Start </li></ul><ul><li>What is the Signal Integrity ? </li></ul><ul><li>Why SI ? </li></ul><ul><li>Signal Integrity Analysis Method </li></ul><ul><li>Why Wave Equation ? </li></ul><ul><li>Reflection Example </li></ul><ul><li>Transmission Line </li></ul><ul><li>Power Plane Analysis </li></ul><ul><li>Electrical Design Setup Process </li></ul><ul><li>Characterization, Modeling and Simulation for System Design </li></ul><ul><li>System Design for Signal Integrity Verification </li></ul><ul><li>Measurement System Set-up </li></ul><ul><li>What you need for SI Analysis ? </li></ul><ul><li>What you need for PI Analysis ? </li></ul><ul><li>Think from example </li></ul><ul><li>ISI </li></ul><ul><li>Transmission Line Modeling </li></ul><ul><li>Different Edge rate w/ Same Frequency </li></ul><ul><li>Common Clock System </li></ul><ul><li>Power Integrity </li></ul><ul><li>SSN </li></ul><ul><li>Return path </li></ul><ul><li>Power Z vs. SSN </li></ul><ul><li>Further Study </li></ul><ul><li>Reference Book </li></ul>
  3. 3. Before Start Where is the signal path according to V(t) ? + V(t)
  4. 4. Before Start <ul><li>Knee Frequency (Cutoff Frequency)? </li></ul><ul><ul><li>In electronics, cutoff frequency ( f c ) is the frequency either above which or below which the power output of a circuit, such as a line, amplifier, or electronic filter is 1/2 the power of the passband, and since voltage V 2 is proportional to power P , V is 1/sqrt(2) of the V in the passband. This happens to be close to −3 decibels, and the cutoff frequency is frequently referred to as the −3 dB point. Also called the knee frequency, due to a frequency response curve's physical appearance. </li></ul></ul>
  5. 5. Before Start RC Single-pole pulse
  6. 6. What is the Signal Integrity ? <ul><li>Artwork/Layout </li></ul>Artwork Or Layout Same schematic? Same performance?
  7. 7. What is the Signal Integrity ? <ul><li>Hidden schematics ? </li></ul><ul><ul><li>What is the ideal wire? </li></ul></ul><ul><ul><ul><li>No delay : means the start and end point of wire are equipotential. </li></ul></ul></ul><ul><ul><ul><li>There are not any hidden schematics. </li></ul></ul></ul><ul><ul><ul><li>But in real world, this is a dream. </li></ul></ul></ul><ul><ul><li>In the real world. </li></ul></ul><ul><ul><ul><li>All metals have some delay, even if very small. </li></ul></ul></ul><ul><ul><ul><li>If the wavelength is short according to that delay, there are potential difference at every point in the wire. </li></ul></ul></ul><ul><ul><ul><li>So that we can feel the electric and magnetic field. </li></ul></ul></ul><ul><ul><ul><li>Ohm’s law is not accepted. </li></ul></ul></ul><ul><ul><ul><li>Use Transmission line theory. </li></ul></ul></ul>
  8. 8. Why SI ? <ul><li>Signal integrity and why you should care about it </li></ul><ul><ul><li>In the past, interconnect delays and ringing were ignored because there was plenty of time for reflections to settle out. </li></ul></ul><ul><ul><li>These day, system clock rates have steadily increased, this means signals have much faster edge rates and minimal settling time. </li></ul></ul><ul><ul><li>Reflections can be caused by many factors, including capacitive loading, impedance mismatching, stubs and improper terminations. </li></ul></ul><ul><ul><li>Crosstalk results from the coupling between traces and is a distinct problem in higher-density boards with faster edge rates. </li></ul></ul><ul><ul><li>Subnanosecond edges are composed of high frequency harmonics that can easily couple into an adjacent interconnect causing crosstalk. </li></ul></ul>
  9. 9. Signal Integrity Analysis Method <ul><li>Analytical Method </li></ul><ul><ul><li>Very Cheap </li></ul></ul><ul><ul><li>Very Fast </li></ul></ul><ul><ul><li>Not acceptable to all cases </li></ul></ul><ul><ul><li>Only used for the estimation of the simulation result </li></ul></ul><ul><li>Measurement Method </li></ul><ul><ul><li>Huge Expensive </li></ul></ul><ul><ul><li>Very Slow </li></ul></ul><ul><ul><li>Many measurement Techniques are needed </li></ul></ul><ul><ul><li>All debugging techniques are not available </li></ul></ul><ul><li>Simulation Method </li></ul><ul><ul><li>Somewhat Expensive </li></ul></ul><ul><ul><li>Middle speed </li></ul></ul><ul><ul><li>Many kinds of CAD tool are needed </li></ul></ul><ul><ul><ul><li>Single line w/ Ideal Plane </li></ul></ul></ul><ul><ul><ul><li>Multiple line w/ Ideal Plane </li></ul></ul></ul><ul><ul><ul><li>Multiple line w/ Non-Ideal Plane </li></ul></ul></ul>
  10. 10. Why wave equation ? <ul><li>Maxwell Equation </li></ul><ul><li>Telegrapher Equation </li></ul>
  11. 11. Reflection Example <ul><li>T r = 0. 1ns/0.6V, Rout = 25 Ohms </li></ul>
  12. 12. Reflection Example
  13. 13. Reflection Example <ul><li>When R2=25 Ohms? </li></ul><ul><li>For more exact value of R2, refer to Loadline Analysis </li></ul>
  14. 14. Reflection Example
  15. 15. Transmission line <ul><li>The wave velocity on PCB is slower than on AIR </li></ul><ul><li>There are many rule of thumb </li></ul><ul><ul><li>Trace Delay : TD </li></ul></ul><ul><ul><li>Rising/Falling Time : Tr/Tf </li></ul></ul><ul><ul><li>Treat the trace as Transmission line when (5~10) X TD > Tr/Tf </li></ul></ul><ul><li>Don’t forget using EFFECTIVE DIELECTRIC CONSTANT </li></ul><ul><ul><li>Micro-Strip (PSR or Non-PSR) </li></ul></ul><ul><ul><li>Strip (CCL or P.P) </li></ul></ul>Dielectric Constant is a function of frequency and dependant on manufacturing even if same material.
  16. 16. Transmission line <ul><li>Calculation of Signal Velocity in Dielectrics </li></ul><ul><li>If Length = 10mm, TD is about 70 ps. </li></ul><ul><li>If (5~10) X TD > Tr/Tf meets that is [Tr/Tf < (350 ps~700 ps)] </li></ul><ul><ul><li>This is a Transmission line, so we should do a Simulation </li></ul></ul>
  17. 17. Power Plane Analysis <ul><li>Power Ground Plane Resonance </li></ul><ul><li>Simultaneous Switching Noise </li></ul><ul><li>DC Drop </li></ul>
  18. 18. Electrical Design Setup Process <ul><li>Characterization </li></ul><ul><ul><li>Measurement of electrical/mechanical parameter. </li></ul></ul><ul><ul><li>Using VNA/TDR/TDT. </li></ul></ul><ul><ul><li>Need De-embedding technique. </li></ul></ul><ul><ul><li>It takes a lot of time to characterize. </li></ul></ul><ul><li>Modeling </li></ul><ul><ul><li>Good characterization makes good modeling correlation between CAD tool and measurement waveform. </li></ul></ul><ul><ul><li>Difficult to choose an appropriate CAD tool . </li></ul></ul><ul><ul><li>Lumped ? Or Distributed ? </li></ul></ul><ul><li>Simulation </li></ul><ul><ul><li>Performance estimation such as Signal Quality, Power Plane resonance, Plane Impedance Profile, SSN, Crosstalk, and etc. </li></ul></ul>
  19. 19. Characterization, Modeling, and Simulation for System Design * Ref : Gigalab Hanyang Univ. Parasitic RLC Power Integrity <ul><li>SSN (Delta-I Noise) </li></ul><ul><li>Resonance </li></ul>Signal Integrity <ul><li>Crosstalk </li></ul><ul><li>Timing </li></ul><ul><li>Waveform Distortion </li></ul><ul><li>Transmission Line Parameters </li></ul><ul><li>( RLCG, Propagation Constant, </li></ul><ul><li>Characteristic Impedance, etc ) </li></ul>< General SOP Package System > < Circuit Model for Design > Circuit Model Parameter Characterization Simulation Simulation Modeling !! Characterization !!
  20. 20. “ Electrical Design” means “Performance Estimation” based on Accurate Characterization, Modeling, and Simulation !! System Design for Signal Integrity Verification * Ref : Gigalab Hanyang Univ.
  21. 21. Impedance Analyzer RF Probe Station TDR/TDT VNA Network Analyzer - High-Freq. S-Parameter - Freq.-Variant Parameters - Signal Transient Char. Impedance Analyzer - Low-Freq. Impedance - Capacitance - Long Line Inductance TDR/TDT - Time-Domain Reflection - Time-Domain Trans. - Discontinuity Charac. Measurements System Set-Up * Ref : Gigalab Hanyang Univ.
  22. 22. What you need for SI analysis ? <ul><li>Modeling data </li></ul><ul><ul><li>Active IC component : IBIS/Spice Model </li></ul></ul><ul><ul><li>Passive component : Equivalent Circuit Model </li></ul></ul><ul><ul><li>Trace (copper) </li></ul></ul><ul><ul><ul><li>Transmission line model </li></ul></ul></ul><ul><ul><ul><ul><li>Time domain : T-element, W-element, U-element, FWS … </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Frequency domain : S-parameter </li></ul></ul></ul></ul><ul><ul><ul><li>Lumped line model </li></ul></ul></ul><ul><ul><ul><ul><li>Rule of thumb : electrical length < λ /10 </li></ul></ul></ul></ul><ul><ul><ul><ul><li>R, L, G, C </li></ul></ul></ul></ul><ul><ul><li>Electrical parameter : Dielectric Constant, Loss tangent, Conductivity </li></ul></ul><ul><ul><li>Mechanical parameter : Physical cross-section’s dimension </li></ul></ul><ul><li>CAD Tool </li></ul><ul><ul><li>2D, 2.5D, 3D field solver and IBIS or Spice Simulator </li></ul></ul><ul><li>Datasheet </li></ul><ul><ul><li>Find the DC/AC Spec. and calculate DC/AC Margin </li></ul></ul>
  23. 23. What you need for PI analysis ? <ul><li>Modeling data </li></ul><ul><ul><li>Active IC component : IBIS/Spice Model </li></ul></ul><ul><ul><li>Decoupling Capacitor : Equivalent Circuit Model </li></ul></ul><ul><ul><li>Plane pair Modeling (copper) : CAD Tool </li></ul></ul><ul><ul><li>Electrical parameter : Dielectric Constant, Loss tangent, Conductivity </li></ul></ul><ul><ul><li>Mechanical parameter : Physical cross-section’s dimension </li></ul></ul><ul><li>CAD Tool </li></ul><ul><ul><li>2D, 2.5D, 3D field solver and IBIS or Spice Simulator </li></ul></ul><ul><li>Datasheet or Spec. </li></ul><ul><ul><li>Find the DC/AC Spec. and calculate DC/AC Margin </li></ul></ul><ul><ul><li>Maximum dynamic current </li></ul></ul><ul><ul><li>Maximum voltage ripple Tolerance </li></ul></ul>
  24. 24. Think from example (Star) <ul><li>Case1 </li></ul><ul><li>Case2 </li></ul>Vt Rt TL0 DRV TL1 RCV A TL2 RCV B TL3 RCV C TL4 RCV D TL5 Item TL0 TL1 TL2 TL3 TL4 TL5 Vt Rt Z 0 ( Ω ) 51 50 50 50 50 50 0.75 16.66 Length (mm) 470 51 51 51 51 15 Item TL0 TL1 TL2 TL3 TL4 TL5 Vt Rt Z 0 ( Ω ) 51 50 50 50 50 50 0.75 16.66 Length (mm) 470 79 79 79 79 15
  25. 25. Think from example (Star) <ul><li>10 pulse of 1 and 0 (Frequency : 400Mhz) </li></ul>Blue? Low Overshoot?
  26. 26. Think from example (Star) <ul><li>1024 PRBS (Frequency : 400Mhz) </li></ul>
  27. 27. Think from example (H-Tree) Item TL0 TL1, TL2 TL3~TL6 Z 0 ( Ω ) 51 70 110 Length (mm) 470 30 26 TL0 DRV TL3 RCV A TL4 RCV B TL5 RCV C TL6 RCV D TL1 TL2
  28. 28. Think from example (H-Tree) <ul><li>1024 PRBS (Frequency : 400Mhz) </li></ul>
  29. 29. ISI <ul><li>Inter-Symbol Interference : Pattern dependent skew </li></ul><ul><li>30 bits ‘0’ and ‘1’,vs, only 16 th bit is ‘1’ </li></ul>
  30. 30. Transmission Line Modeling <ul><li>Distributed </li></ul><ul><ul><li>W-element </li></ul></ul><ul><ul><ul><li>Rs : the skin effect matrix </li></ul></ul></ul><ul><ul><ul><li>Gd : power loss due to the rotation of dipoles under the alternating field </li></ul></ul></ul><ul><ul><li>Field Solver Model </li></ul></ul><ul><ul><li>S Model </li></ul></ul><ul><ul><li>FWS (Full Wave Spice) Model </li></ul></ul>*SYSTEM_NAME : cond_sys * * Half Space, AIR * ------------------------------------ Z = 3.045200e-001 * AIR H = 3.000000e-001 * ------------------------------------ Z = 4.520000e-003 * al2o3 H = 4.500000e-003 * ------------------------------------ Z = 2.000000e-005 * //// Bottom Ground Plane /////////// * ------------------------------------ Z = 0 * L(H/m), C(F/m), Ro(Ohm/m), Go(S/m), Rs(Ohm/(m*sqrt(Hz)), Gd(S/(m*Hz)) .MODEL cond_sys W MODELTYPE=RLGC, N=1 + Lo = 1.081618e-006 + Co = 5.764322e-011 + Ro = 2.625003e+002 + Go = 0.000000e+000 + Rs = 1.226710e-002 + Gd = 2.414554e-014
  31. 31. Transmission Line Modeling <ul><li>Lumped Line Modeling </li></ul><ul><ul><li>T Line model vs L-C cascade network </li></ul></ul>
  32. 32. Transmission Line Modeling
  33. 33. Transmission Line Modeling
  34. 34. Different Edge rate w/ Same Frequency
  35. 35. Different Edge rate w/ Same Frequency
  36. 36. Common Clock System <ul><li>Clock Driver Timing Spec. </li></ul><ul><ul><li>T co_clkA , T co_clkB , Jitter </li></ul></ul><ul><li>Controller Timing Spec. </li></ul><ul><ul><li>T co_data_min , T co_data_max , T data_skew </li></ul></ul><ul><li>Memory Timing Spec. </li></ul><ul><ul><li>T su , T hd </li></ul></ul><ul><li>Interconnect Timing Spec. </li></ul><ul><ul><li>T flt_clkA , T flt_clkB , T flt_data </li></ul></ul>Clock Driver clkA T co_clkA clkB Clk_in T flt_clkA T flt_clkB T co_clkB D c T co_data Controller clkC clkM D m T flt_data Memory T co_min T co_max clkC D c T su T hd clkM D m
  37. 37. Common Clock System <ul><li>T flt_data < T cycle – T co_data_max – T su + T flt_clkA – T flt_clkB + (T co_clkA – T co_clkB ) – Jitter </li></ul><ul><li>T flt_data > T hd – T co_data_min + T flt_clkA – T flt_clkB + (T co_clkA – T co_clkB ) </li></ul><ul><li>Watch out! </li></ul><ul><ul><li>Flight time measurement </li></ul></ul><ul><ul><ul><li>Corner Case </li></ul></ul></ul><ul><ul><ul><ul><li>Fast, Slow </li></ul></ul></ul></ul><ul><ul><ul><li>Measurement Level </li></ul></ul></ul><ul><ul><ul><ul><li>Threshold level ( V meas or V il /V ih ) </li></ul></ul></ul></ul><ul><ul><ul><li>Flight Time Compensation </li></ul></ul></ul><ul><ul><ul><ul><li>Receiver – Test Load </li></ul></ul></ul></ul><ul><ul><li>Crosstalk Budget </li></ul></ul><ul><ul><ul><li>Even mode or Odd mode </li></ul></ul></ul><ul><ul><li>Power Noise Budget </li></ul></ul><ul><ul><li>ETC </li></ul></ul>
  38. 38. Power Integrity <ul><li>Target Impedance </li></ul><ul><ul><li>How can we measure it ? </li></ul></ul><ul><ul><ul><li>Dynamic Current </li></ul></ul></ul><ul><ul><ul><ul><li>Circuit Simulation </li></ul></ul></ul></ul><ul><ul><ul><ul><li>On DDR2/DDR3 : IDD7 – IDD2 </li></ul></ul></ul></ul><ul><ul><ul><li>Voltage Ripple Tolerance </li></ul></ul></ul><ul><ul><ul><ul><li>Datasheet : Supply voltage Typical, Min, Max </li></ul></ul></ul></ul><ul><ul><li>Which frequency ? </li></ul></ul><ul><ul><ul><li>Knee frequency : 0.5/T r or 0.35/T r </li></ul></ul></ul><ul><li>Decoupling Capacitor libraries </li></ul><ul><ul><li>Murata, TDK, SEMCO, AVX, and ETC </li></ul></ul><ul><li>Resonance and Anti-resonance </li></ul><ul><ul><li>Series Resonance / Parallel Resonance </li></ul></ul>IDD7 : The maximum current drawn by each chip IDD2 : The minimum current is associated with the idle current http://www.jedec.org/download/search/JESD79-2B.pdf
  39. 39. Power Integrity 10 x 10 2 pF = 1 nF 12 x 10 2 pF = 1.2 nF 10 x 10 3 pF = 10 nF 10 x 10 4 pF = 100 nF 10 x 10 5 pF = 1 uF 22 x 10 5 pF = 2.2 uF
  40. 40. Power Integrity (Example) <ul><li>DDR3 Module(4 Devices) </li></ul><ul><ul><li>IDD7 – IDD2 = 250 mA – 50mA = 200mA from Datasheet </li></ul></ul><ul><ul><li>Voltage Ripple = (Max/Min) – Typ = (1.575/1.425)-1.5 = ±0.075V </li></ul></ul><ul><ul><li>Z target = 0.075/(4*200m) = 93.75 m Ω </li></ul></ul><ul><ul><li>Rising Time : 230 psec from IBIS Model </li></ul></ul><ul><ul><li>Falling Time : 196 psec from IBIS Model </li></ul></ul><ul><ul><li>F knee = 0.35/min(t r ,t f ) = 1.79 GHz </li></ul></ul>
  41. 41. Power Integrity (Example) M O R E C A P.
  42. 42. SSN (Example) <ul><li>SSN : Simultaneous Switching Noise </li></ul><ul><ul><li>Dynamic Current </li></ul></ul><ul><ul><ul><li>Fast Transition of State between ‘0’ and ‘1’ </li></ul></ul></ul><ul><ul><li>Power Delivery Network (PDN) Inductance </li></ul></ul>
  43. 43. SSN (Example) 6 Bits Switching 3 Bits Switching 6 Bits Switching w/ 2 Dec_Cap
  44. 44. Return Path (Example) <ul><li>Return path discontinuity </li></ul>Plane has no gap Plane has a gap S21 Port1 Port2 Port14 Port15 Plane has no gap Plane has a gap S1514
  45. 45. Return Path (Example) <ul><li>Re-routing to avoid Impedance Mismatching </li></ul>Plane has no gap Plane has a gap S21 Rerouting
  46. 46. Power Z vs. SSN(Example) A1 – Blue A2 - Red
  47. 47. Power Z vs. SSN(Example) 400 Mhz (PRBS) : Power
  48. 48. Power Z vs. SSN(Example) 400 Mhz (PRBS) : Signal
  49. 49. Power Z vs. SSN(Example) 1000 Mhz (PRBS) : Power
  50. 50. Power Z vs. SSN(Example) 1000 Mhz (PRBS) : Signal
  51. 51. Power Z vs. SSN(Example) <ul><li>It is difficult to forecast the result of SSN based on Power Plane Impedance Profile. </li></ul><ul><li>Because there are many frequency components at digital signal, the Power Plane Impedance can’t tell many things to us. </li></ul><ul><li>To find the best design of Power Plane, we had better check the SSN result after optimizing Power Plane Impedance Profile. </li></ul>
  52. 52. Further Study <ul><li>IBIS Model validation </li></ul><ul><li>Noise Budget Determination </li></ul><ul><li>Timing Budget Determination </li></ul><ul><li>Crosstalk of offset timing </li></ul><ul><li>De-embedding Technique </li></ul><ul><li>IC + Package + Board Co-simulation </li></ul><ul><li>Harmonics when the duty cycle is not 50% </li></ul><ul><ul><li>Even/Odd harmonics </li></ul></ul><ul><li>Eye Opening Measurement by In-house Software </li></ul>
  53. 53. Reference Book <ul><li>Signal Integrity – Simplified by Eric Bogatin </li></ul><ul><li>Signal Integrity Issues and Printed Circuit Board Design by Douglas Brooks </li></ul><ul><li>Timing Analysis and Simulation for Signal Integrity Engineers by Greg Edlund </li></ul><ul><li>High Speed Digital Design by Howard Johnson and Martin Graham </li></ul><ul><li>Digital Signal Integrity : Modeling and Simulation with Interconnects and Packages by Brian Young </li></ul><ul><li>Power Integrity Modeling and Design for Semiconductor and Systems by Madhavan Saminathan and Ege Engin </li></ul><ul><li>High Speed Signal Propagation : Advanced Black Magic by Howard Johnson </li></ul><ul><li>Advanced Signal Integrity for High-speed Digital Designs by Stephan H. Hall and Howard L. Heck </li></ul><ul><li>High-Speed Circuit Board Signal Integrity by Stephen, C. Thierauf </li></ul><ul><li>Jitter, Noise, and Signal Integrity at High-speed by Mike Peng Li </li></ul><ul><li>Handbook of Digital Techniques for High-speed Design by tom Granberg </li></ul><ul><li>Semiconductor Modeling by Roy g. Leventhal, ….. </li></ul><ul><li>High-Speed Digital System Design by Stephen H. Hall, Garrett W. Hall, and James A. McCall </li></ul>
  54. 54. Q & A *** Thank you *** http://www.signalintegrity.co.kr Theory : Inductance, Capacitance, Loss, Energy, Digital Design, System operation, Spice, IBIS, Field Solving, 2D Modeling, 3D Modeling, 2.5D Modeling, CAD Tool, Maxwell Equation, Wave Velocity, TEM/TE/TM Mode, Quasi-static, Resonance, Coupling, Radiation, Common mode noise, Differential mode noise, Differential Signal, DDR, Common clock, Source-Sync. clock, Dielectric, Skin depth, Fringing effect, Artwork, PCB, Connector, Cable, Return path, FFT, Knee frequency, Network parameter, TDR/TDT, VNA, Transmission Line, Characteristic Impedance, Jitter, Skew, ISI, SSN, BER, Return path, Proximity effect, Threshold level, Dynamic current, Timing, Capacitive Coupling, Inductive Coupling, and etc

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