This document summarizes sequential circuits and finite state machines. It discusses: - Representing state using state equations, state tables, and state diagrams - Analyzing sequential circuits using D, JK, and T flip-flops - The difference between Mealy and Moore machines and examples of each - Design procedures for state machines including state diagrams, next state tables, excitation tables, K-maps, and circuit implementation

1. LECTURE 03:
SEQUENTIAL CIRCUITS
ANALYZING SEQUENTIAL CIRCUITS

2. Overview
• Understanding flip flop state:
– Stored values inside flip flops
• Clocked sequential circuits:
– Contain flip flops
• Representations of state:
– State equations
– State table
– State diagram
• Finite state machines
– Mealy machine
– Moore machine

3. State Table
• The time sequence of inputs, outputs, and flip flop
states can be enumerated in a state table
(transition table).
 The table consists of four sections
• Present state shows the states of the flip flops at time t
• Input gives input values for each possible present state
• Next state shows the states of the flip flops one cycle
later at t + 1
• Output gives the value of other outputs at time t for
each present state and input condition

4. Analysis of Clocked Sequential Circuits
• The behavior of a clocked sequential circuit is
determined from the inputs, the outputs, and the
state of its flip flops.
 The outputs and the next state are both a function of
the inputs and the present state.
• Analysis consists of obtaining a table or a diagram
for the time sequence of inputs, outputs, and internal
states.
• It is also possible to write Boolean expressions that
describe the behavior.

5. State Equations
• A state equation (transition equation) specifies the
next state as a function of the present state and
inputs.
 It is an algebraic equation that specifies the
condition for a flip flop state transition.
• With D type flip flops, the state equation is the
same as the input equation.
• With JK and T flip flops, it is necessary to refer to
the corresponding characteristic table or
characteristic equation to obtain the next state
values.

6. Example Sequential Circuit

7. State Equations for the previous figure
• Since the D input determines the next state, we
have:
 A(t + 1) = A(t)x(t) + B(t)x(t) = Ax + Bx
 B(t + 1) = A’(t)x(t) = A’x
 y(t) = [A(t) + B(t)]x’(t) = (A + B)x’

8. State Table
• The time sequence of inputs, outputs, and flip flop
states can be enumerated in a state table
(transition table).
 The table consists of four sections
• Present state shows the states of the flip flops at time t
• Input gives input values for each possible present state
• Next state shows the states of the flip flops one cycle
later at t + 1
• Output gives the value of other outputs at time t for
each present state and input condition

9. Our Example
• The derivation of a state table requires listing
all possible binary combinations of present
state and inputs.
 In our example, we have eight combinations
from 000 to 111.
• The next state values are then determined from
the logic diagram or from the state equations.

10. Example State Table
• 𝑨(𝒕 + 𝟏) = 𝑨𝒙 + 𝑩𝒙
• 𝑩(𝒕 + 𝟏) = 𝑨’𝒙
• 𝒚(𝒕) = (𝑨 + 𝑩)𝒙’

11. Alternative Table

12. State Diagram
• Information in a state table can be represented graphically in the
form of a state diagram.
• In a state diagram:
 a state is represented by a circle
 transitions between states are indicated by directed lines
connecting the circles
 Binary numbers inside the circles represent state of the flip
flops
 Directed lines are labeled with two binary numbers separated
by a slash
• The input value during the present state is labeled first
• The second number gives the output after the present
state with the given input

13. State Diagram
• Circles indicate current state
• Arrows point to next state
• For x/y, x is input and y is output

14. Analysis With D Flip Flops
• We start analysis with a given input equation:
 DA = A ⊕ x ⊕ y
• This implies a D flip flop with output A.
• x and y are inputs to the circuit
• No outputs are given so the output is implied to
come from the output of the flip flop.
• Figure is shown on the next slide.

15. Analysis With D Flip Flops
Identify flip flop input equations
Identify output equation
Note: this example
has no output

16. JK and T Flip Flop Analysis
• The next-state values of a sequential circuit that
uses flip flops such as JK or T type can be
derived using the following procedure:
 Determine the flip flop input equations in terms
of the present state and input variables
 List the binary values of each input equation
 Use the corresponding flip flop characteristic
table to determine the next state values in the
state table

17. JK Analysis Example
• JA = B
• JB = x’
• KA = Bx’
• KB = A’x + Ax’ = A ⊕ x

18. JK Analysis State Table

19. JK Analysis State Diagram

20. T Flip Flop Analysis
• Analysis of a sequential circuit with T flip
flops follows the same procedure outlined
for JK flip flops.
• The next state values in the state table can
be obtained either by using the
characteristic table or the characteristic
equation
 Q(t + 1) = T ⊕ Q = T’Q + TQ’

21. T Flip Flop Analysis Example

22. T Flip Flop Analysis State Table

23. Mealy and Moore Models
• The Mealy and Moore models differ in the
way the output is generated.
 In the Mealy model, the output is a
function of both the present state and
input, referred to as a Mealy finite state
machine (FSM) or Mealy machine.
 In the Moore model, the output is a
function of the present state only, referred
to as a Moore FSM or Moore machine.

24. Mealy versus Moore
Outputs
Output
Logic
Combina-
tional
Combina-
tional
Logic
Input
Memory
Element
Inputs
Mealy Model
Outputs
Output
Logic
Combina-
tional
Combina-
tional
Logic
Input
Memory
Element
Inputs
Moore Model

25. Example Mealy Model
• Output y is a function of both input x and
the present state of A and B.

26. Example Moore Model
• The output is a function of the present state only.

27. Notes on Mealy and Moore
• In the Moore model, the outputs of the sequential
circuit are synchronized with the clock because they
depend on only flip flop outputs that are synchronized
with the clock.
• In the Mealy model, the outputs may change if the
inputs change during the clock cycle and the outputs
may have momentary false values because of the
delay encountered from the time that the inputs
change and the time that the flip flop outputs change.
 To synchronize a Mealy type circuit, the inputs of
the sequential circuit must be synchronized with
the clock and the outputs must be sampled only
during the clock edge.

28. Summary
• Flip flops contain state information
• State can be represented in several forms:
– State equations
– State table
– State diagram
• Possible to convert between these forms
• Circuits with state can take on a finite set of values
– Finite state machine
• Two types of “machines”
– Mealy machine
– Moore machine
• Next :
– More about State machines
– State Reduction and Assignment
– Design Procedure of synchronous sequential circuits

29. State Machine
 State machine (also called as a
sequential circuit) can be viewed as a
synchronous counter with irregular
sequence.
 There two types of state machines:
1. Moore machine
Next state (output) depends on the present
internal state only.
2. Mealy machine
Next state (output) depends on the present
internal state and also input at that
particular of time.

30. Example: Detect 3 Consecutive 1
inputs
State S0 : zero 1s detected
State S1 : one 1 detected
State S2 : two 1s detected
State S3 : three 1s detected
0
Note that each state has 2 output arrows
Two bits needed to encode state

31. State Table for Sequence Detector
° Sequence of outputs, inputs,
and flip flop states enumerated
in state table
° Present state indicates current
value of flip flops
° Next state indicates state after
next rising clock edge
° Output is output value on
current clock edge
Present
State
Next
State
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1
Output
Input
° S0 = 00
° S1 = 01
° S2 = 10
° S3 = 11

32. Finding Expressions for Next State and Output Value
° Create K-map directly from state table (3 columns = 3 K-maps)
° Minimize K-maps to find SOP representations
° Separate circuit for each next state and output value

33. Circuit for Consecutive 1s Detector
° Note location of state
flip flops
° Output value (y) is
function of state
° This is a Moore
machine.

34. Vending Machine FSM
Step 1. Specify the problem
Vending
Machine
FSM
N
D
Reset
Clk
Open
Coin
Sensor
Gum
Release
Mechanism
Deliver package of gum after 15 cents deposited
Single coin slot for dimes, nickels
No change
Design the FSM using combinational logic and flip flops

35. Vending Machine FSM
State Diagram
Reset
N
N
N, D
[open]
15¢
0¢
5¢
10¢
D
D
Reuse states
whenever possible
Symbolic State Table
Present
State
0¢
5¢
10¢
15¢
D
0
0
1
1
0
0
1
1
0
0
1
1
X
N
0
1
0
1
0
1
0
1
0
1
0
1
X
Inputs Next
State
0¢
5¢
10¢
X
5¢
10¢
15¢
X
10¢
15¢
15¢
X
15¢
Output
Open
0
0
0
X
0
0
0
X
0
0
0
X
1

36. Vending Machine FSM
State Encoding
Next State
D1 D0
0 0
0 1
1 0
X X
0 1
1 0
1 1
X X
1 0
1 1
1 1
X X
1 1
1 1
1 1
X X
Present State
Q1 Q0
0 0
0 1
1 0
1 1
D
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
N
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Inputs Output
Open
0
0
0
X
0
0
0
X
0
0
0
X
1
1
1
X
How many flip-flops are needed?

37. Vending Machine FSM
Determine F/F implementation
K-map for Open
K-map for D0
K-map for D1
Q1 Q0
D N
Q1
Q0
D
N
Q1 Q0
D N
Q1
Q0
D
N
Q1 Q0
D N
Q1
Q0
D
N

38. Vending machine FSM implementation based on D flip-flops(Moore).
D Q
Q
R
D Q
Q
R
Q0
N
N
Q0
Q1
N
Q1
D
D0
D1 Q1
OPEN
D
0
Q
N
CLK
CLK
0
Q
1
Q
Q1
Q0
Reset
Reset
Minimized Implementation

39. Design of a state machine
1. State diagram
A diagram that shows all the transition of states
when clock is triggered.
Number of FF = number of bits
2. Next state table
Listing of all the present state along with its next
state.
3. Excitation table
Listing of all the JK connections of all FFs for the
next state transition to occur.
4. K-map
Determine the simplified logic expression for all J &
K
5. Circuit implementation
Draw the complete circuit.

40. Moore Machine
Example: Design a 3-bit Gray code up counter.
Design a 3-bit counter with this sequence
,000,001,011,010,110,111,101,100,000,
Solution
STEP 1: State diagram
Since this is a 3-bit counter
3 JK flip-flops are needed.

41. STEP 2: Next state table
The present state is arranged in incremental binary counting order although the
sequence of the counter is not.

42. STEP 3: Excitation table
By referring to JK flip-flop transition table
The excitation table is:

43. STEP 4: K-map
Step 4: K-map (need 6 K-map, two for each JK FF).

44. STEP 5: Circuit Implementation

45. Moore Machine
 Design a 3-bit Moore state machine
with state diagram
45

46. Next state table
46

47. Excitation table
47

48. K-map (need 6 K-map, two for each JK FF).
48

49. Circuit implementation
49

50. Mealy Machine
 The present output from Mealy state machine
depends on both the present input and the
previous output.
 Thus, the present input needs to be
considered too.
Example:
Design an up/down 3-bit Gray code counter. If
input Y is low, the counter will perform count
down operation else the counter will perform
count up operation.

51. Solution
STEP 1: State diagram
Since this is a 3-bit counter
3 JK flip-flops are needed.

52. STEP 2: Next state table
The present state is arranged in incremental binary counting order although
the sequence of the counter is not.

53. STEP 3: Excitation table
The excitation table is: (refer to JK FF transition table)
Present State Input Next state C FF B FF A FF
QC QB QA Y QC QB QA JC KC JB KB JA KA
0 0 0 0 1 0 0 1 X 0 X 0 X
0 0 0 1 0 0 1 0 X 0 X 1 X
0 0 1 0 0 0 0 0 X 0 X X 1
0 0 1 1 0 1 1 0 X 1 X X 0
0 1 0 0 0 1 1 0 X X 0 1 X
0 1 0 1 1 1 0 1 X X 0 0 X
0 1 1 0 0 0 1 0 X X 1 X 0
0 1 1 1 0 1 0 0 X X 0 X 1
1 0 0 0 1 0 1 X 0 0 X 1 X
1 0 0 1 0 0 0 X 1 0 X 0 X
1 0 1 0 1 1 1 X 0 1 X X 0
1 0 1 1 1 0 0 X 0 0 X X 1
1 1 0 0 0 1 0 X 1 X 0 0 X
1 1 0 1 1 1 1 X 0 X 0 1 X
1 1 1 0 1 1 0 X 0 X 0 X 1
1 1 1 1 1 0 1 X 0 X 1 X 0

54. STEP 4: K-map
For C flip-flop
00 01 11 10
00 X X 1 0
01 X X 0 1
11 X X 0 0
10 X X 0 0
QCQB
QAY
KC
00 01 11 10
00 1 0 X X
01 0 1 X X
11 0 0 X X
10 0 0 X X
QCQB
QAY
JC
QBQAY
QBQAY
QBQAY
QBQAY
KC = QB’QA’Y + QBQA’Y’
=QA’(QBY)
JC = QB’QA’Y’ + QBQA’Y
=QA’(QBY)

55. STEP 4: K-map (cont.)
For B flip-flop
00 01 11 10
00 X 0 0 X
01 X 0 0 X
11 X 0 1 X
10 X 1 0 X
QCQB
QAY
KB
00 01 11 10
00 0 X X 0
01 0 X X 0
11 1 X X 0
10 0 X X 1
QCQB
QAY
JB
QCQAY
QCQAY
QCQAY
QCQAY
JB = QC’QAY + QCQAY’
=QA(QCY)
KB = QC’QAY’ + QCQAY
=QA(QCY)

56. STEP 4: K-map (cont.)
For A flip-flop
00 01 11 10
00 X X X X
01 X X X X
11 0 1 0 1
10 1 0 1 0
QCQB
QAY
KA
00 01 11 10
00 0 1 0 1
01 1 0 1 0
11 X X X X
10 X X X X
QCQB
QAY
JA
JA = QC’QB’Y + QC’QBY’ + QCQBY
+ QCQB’Y’
= QC  QB  Y
KA = QC’QB’Y’ + QC’QBY + QCQBY’ +
QCQB’Y
= QC  QB  Y

57. STEP 5: Circuit Implementation

58. State Reduction and Assignment

59. Overview
 Important to minimize the size of digital circuitry
 Analysis of state machines leads to a state
table (or diagram)
 In many cases reducing the number of states
reduces the number of gates and flops
◦ This is not true 100% of the time
 In this course we attempt state reduction by
examining the state table
 Other, more advanced approaches, possible
 Reducing the number of states generally
reduces complexity.

60. State Reduction and
Assignment
 The analysis of sequential circuits starts from a
circuit diagram and culminates in a state table
or diagram.
 The design of a sequential circuit starts from a
set of specifications and culminates in a logic
diagram.
 One of the things we need to do is look at
properties of sequential circuits that may be
used to reduce the number of gates and flip
flops during design.
 Two techniques we can use are state
reduction and state assignment.

61. State Reduction
The reduction of the number of flip flops is referred
to as the state reduction problem.
• Algorithms are aimed at reducing the number of
states in the state diagram, while keeping the
external input-output requirements unchanged.
• Since m flip flops produce 2m states, a reduction
in the number of states may or may not result in
a reduction in the number of flip flops.
• An unpredictable effect in reducing the number
of flip flops is that sometimes the equivalent
circuit with fewer flip flops may require more
combinational gates.

62. FSM
Optimization
° State Reduction:
Motivation:
lower cost
- fewer flip-flops in
one-hot
implementations
- possibly fewer flip-
flops in encoded
implementations
- more don’t cares in
next state logic
- fewer gates in next
state logic
Simpler to design with
extra states then reduce
later.
° Example: Odd parity
checker
S0
[0]
S1
[1]
S2
[0]
0
1
1
1
0
0
S0
[0]
S1
[1]
0
1
0
1
Moore machine

63. State Reduction
 “Row Matching” is based on the state-transition table:
• If two states
◦ have the same output and both transition to the same next state
◦ or both transition to each other
◦ or both self-loop
◦ then they are equivalent.
• Combine the equivalent states into a new renamed state.
• Repeat until no more states are combined
NS output
PS x=0 x=1
S0 S0 S1 0
S1 S1 S2 1
S2 S2 S1 0
State Transition Table

64. FSM Optimization
 Merge state S2 into S0
 Eliminate S2
 New state machine
shows same I/O
behavior
 Example: Odd parity
checker.
S0
[0]
S1
[1]
S2
[0]
0
1
1
1
0
0
S0
[0]
S1
[1]
0
1
0
1
NS output
PS x=0 x=1
S0 S0 S1 0
S1 S1 S0 1
State Transition Table

65. Row Matching Example

66. State Reduction Algorithm
 Two states are said to be equivalent if, for
each member of the set of inputs, they give
exactly the same output and send the circuit
either to the same state or to an equivalent
state.
• When two states are equivalent, one of them
can be removed without altering the input-
output relationships.
 In our example, we look for two present
states that go to the same next state and
have the same output for both input
combinations.

67. State Reduction

68. Row Matching Example
NS output
PS x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f e f 0 1
NS output
PS x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
Reduced State Transition Diagram