MEWAR UNIVERSITY
Presented by: Presented to:
Kamal Jeet Mr Sayed arif ali
B.tech (ECE) 3rd yr Dept. of (ECE)
CONTENTS
Introduction
Inertial delay with examples
Transport delay
Conclusion
DELAY MODELS IN VHDL
The delay models are
 Inertial delay
 Transport delay
Inertial delay
Models the delays found in switching circuits.
It is used for removing noises
The value appears at the output after the
specified inertial delay.
Inertial Delay
The format is;
T<= reject TIME_2 inertial VALUE after TIME_1;
This is the default delay model.
 The following assignments are equivalent:
T<= VALUE after TIME_1; --(default inertial
delay)
 T<= inertial VALUE after TIME_1;
Furthermore “ T<= VALUE “ is just a shortcut
for
T<= VALUE after 0 ns
If no pulse rejection limit is specified, the
default PRL is the inertial delay value itself.
Transport delay model
 Models the propagation delay.
 Transport delay models signal transfers through wire with pure
propagation delay, thus spikes are not filtered out like inertial
delay.
 Key word transport must be use in a signal assignment statement.
CONCLUSION
In short we have seen that inertial delay model
can be used to model delays associated with
switching circuit and for rejecting noise in
particular.
Transport delay model is used for modelling
propagation delay
References
 https://web.ewu.edu/groups/technology/Claudio/ee36010/Lectures/delay_models.
pdf
 www.gmvhdl.com/delay
 www.technicalguruji.com
 http://surf-vhdl.com/vhdl-syntax-web-course-surf-vhdl/vhdl-delay-type-modeling/
 https://electronics.stackexchange.com/questions/227919/how-important-is-gate-
delay-when-designing-a-circuit

Delay model in vhdl

  • 1.
    MEWAR UNIVERSITY Presented by:Presented to: Kamal Jeet Mr Sayed arif ali B.tech (ECE) 3rd yr Dept. of (ECE)
  • 2.
    CONTENTS Introduction Inertial delay withexamples Transport delay Conclusion
  • 3.
    DELAY MODELS INVHDL The delay models are  Inertial delay  Transport delay
  • 4.
    Inertial delay Models thedelays found in switching circuits. It is used for removing noises The value appears at the output after the specified inertial delay.
  • 5.
    Inertial Delay The formatis; T<= reject TIME_2 inertial VALUE after TIME_1; This is the default delay model.
  • 7.
     The followingassignments are equivalent: T<= VALUE after TIME_1; --(default inertial delay)  T<= inertial VALUE after TIME_1; Furthermore “ T<= VALUE “ is just a shortcut for T<= VALUE after 0 ns If no pulse rejection limit is specified, the default PRL is the inertial delay value itself.
  • 8.
    Transport delay model Models the propagation delay.  Transport delay models signal transfers through wire with pure propagation delay, thus spikes are not filtered out like inertial delay.  Key word transport must be use in a signal assignment statement.
  • 9.
    CONCLUSION In short wehave seen that inertial delay model can be used to model delays associated with switching circuit and for rejecting noise in particular. Transport delay model is used for modelling propagation delay
  • 10.
    References  https://web.ewu.edu/groups/technology/Claudio/ee36010/Lectures/delay_models. pdf  www.gmvhdl.com/delay www.technicalguruji.com  http://surf-vhdl.com/vhdl-syntax-web-course-surf-vhdl/vhdl-delay-type-modeling/  https://electronics.stackexchange.com/questions/227919/how-important-is-gate- delay-when-designing-a-circuit