Analysis sequential circuits

Spring 2011 ECE 331 - Digital System Design 2
Combinational vs. Sequential
● Combinational Logic Circuit
– Output is a function only of the present inputs.
– Does not have state information.
– Does not require memory.
● Sequential Logic Circuit (aka. Finite State Machine)
– Output is a function of the present state.
– Has state information
– Requires memory.
– Uses Flip-Flops to implement memory.

Synchronous vs. Asynchronous
● Synchronous Sequential Logic Circuit
– Clocked
– All Flip-Flops use the same clock and change
state on the same triggering edge.
● Asynchronous Sequential Logic Circuit
– No clock
– Can change state at any instance in time.
– Faster but more complex than synchronous
sequential circuits.

Sequential Circuits: General Model
● Memory
– Stores state information
– Realized using Flip-Flops
● Combinational Logic
– Implements Flip-Flop input functions and output functions
– Realized using logic gates, a ROM or a PLA

Sequential Circuits: Models
● Moore Machine
– Outputs are a function of the present state.
– Outputs are independent of the inputs.
– State diagram includes an output value for each state.
● Mealy Machine
– Outputs are a function of the present state and the
present input.
– State diagram includes an input and output value for
each transition (between states).

Sequential Circuits: Models

Sequential Circuits: Mealy Model
output
Present state
Next state

Sequential Circuits: Moore Model
Present
state
output
Next state

Sequential Circuits: State Diagram
State
Output
Input
Moore Machine
Each node in the graph
represents a state in the
sequential circuit.

Sequential Circuits: State Diagram
Mealy Machine
Each node in the graph
represents a state in the
sequential circuit.
Input
State
Output

Sequential Circuit Analysis

Analysis: Signal Tracing
1.Assume an initial state for the sequential circuit.
 All Flip-Flops reset to 0 (unless otherwise stated).
2.Determine the sequential circuit output and the flip-
flop inputs for the first input value in the sequence.
3.Determine the next state of each Flip-Flop
 After the next active clock edge.
4.Determine the sequential circuit output and the flip-
flop inputs for the next value in the sequence.
5.Repeat steps 3 & 4.

Example: Moore Machine
input
Flip-Flop inputs
output
State = AB

Example: Moore Machine
0 1 1 0 1

Example: Mealy Machine

Analysis: State Tables and Graphs
Although constructing timing charts is satisfactory for small
circuits and short input sequences, the construction of state
tables and graphs provides a more systematic approach
which is useful for the analysis of larger circuits and which
leads to a general synthesis procedure for sequential
circuits.
The state table specifies the next state and output of a
sequential circuit in terms of its present state and input.

Analysis Procedure
1. Determine the Flip-Flop input equations
2. Determine the Sequential Circuit output equations
3. Derive the Next State equation for each Flip-Flop
 Using the corresponding input equation
 And the Flip-Flop characteristic equation
4. Plot the Next State K-map for each Flip-Flop
5. Construct the State Table (aka. Transition Table)
 Assign a state label to each binary state assignment
6. Draw the corresponding state diagram (aka. state graph)

Example:
Analyze a sequential circuit using D Flip-Flops

Example: Analysis (D FF)
Derive the State Table for the following Sequential Logic Circuit:

The flip-flop input equations are:
DA = X xor B' DB = X or A
Z = A xor B
The next-state equations for the flip-flops are:
A+
= DA = X xor B' B+
= DB = X or A
The sequential circuit output equation is:

The corresponding next-state (K-) maps are:

The state table, or transition table, is then:
A+
B+
A B X = 0 X = 1 Z
0 0 1 0 0 1 0
0 1 0 0 1 1 1
1 1 0 1 1 1 0
1 0 1 1 0 1 1
Present Next State
State X = 0 X = 1 Output
S0 S3 S1 0
S1 S0 S2 1
S2 S1 S2 0
S3 S2 S1 1

The state diagram can then be drawn from the state table:

Example:
Analyze a sequential circuit using JK Flip-Flops

Example: Analysis (JK FF)
Derive the State Table for the following Sequential Logic Circuit:

The flip-flop input equations are:
The next-state equations for the flip-flops are:
The sequential circuit output equation is:
JA = X.B JB = X
KA = X KB = X.A
Z = X.B' + X.A + X'.A'.B
A+
= JA.A' + KA'.A B+
= JB.B' + KB'.B
A+
= X.B.A' + X.A B+
= X.B' + X.A.B

The corresponding next-state (K-) maps are

The state table, and transition table, is then:

The state diagram can then be drawn from the state table:

Example:
Analyze a serial adder

Example: Serial Adder
The serial adder adds two n-bit binary numbers.
(serial) inputs
(serial) output
present
state
next state

Truth Table for the Full Adder:

The state table, or transition table, is then:
Ci+1 Sum
Ci XY = 00 XY = 01 XY = 10 XY = 11 XY = 00 XY = 01 XY = 10 XY = 11
0 0 0 0 1 0 1 1 0
1 0 1 1 1 1 0 0 1
Present Next State Output
State XY = 00 XY = 01 XY = 10 XY = 11 XY = 00 XY = 01 XY = 10 XY = 11
S0 S0 S0 S0 S1 0 1 1 0
S1 S0 S1 S1 S1 1 0 0 1

State Graph for the Serial Adder:
What type of state machine is this?

Timing Diagram for the Serial Adder:

Example:
Analyze a state machine with multiple inputs.

Example: Multiple Inputs
State Table for a state machine with multiple inputs:

Example: Multiple Inputs
State Graph for a state machine with multiple inputs:
How many paths
leave each state?
What type of state
machine is this?

Questions?

Analysis sequential circuits

More Related Content

What's hot

Similar to Analysis sequential circuits

Recently uploaded

Analysis sequential circuits