This document discusses key interconnect parameters for VLSI design including capacitance, resistance, and inductance. It notes that as device sizes shrink, wire lengths increase which leads to greater parasitic effects that must be considered. The document outlines how capacitance depends on shape and surroundings and can be modeled as parallel plates. Resistance is defined by resistivity, length and cross-sectional area, with aluminum a common interconnect material. Inductance also becomes important at higher frequencies. Models are simplified by ignoring less dominant effects.

1. Determining and Quantifying Interconnect Parameters
Dr. Varun Kumar
Dr. Varun Kumar (IIIT Surat) IIIT Surat 1 / 9

2. Outlines
1 Introduction
2 Key Points for VLSI Design
3 Interconnect Parameters - Capacitance, Resistance, and Inductance
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3. Introduction
⇒ Deep sub-micron semiconductor technologies causes rapid growth in
the field of VLSI.
⇒ Wires as a circuit components display a scaling behavior.
⇒ Active devices such as transistors,
Improvise gain
Reduces the device dimension
Improve the circuit speed
⇒ Larger die sizes economically feasible
Increase in the average length of an interconnect wire (parasitic effects)
Dr. Varun Kumar (IIIT Surat) IIIT Surat 3 / 9

4. Key points
⇒ Heavily doped n+ or p+ layers, typically used for the realization of
source and drain regions.
It can be employed for wiring purposes.
These wires have no apparent impact on the circuit performance.
⇒ Integrated circuits has a complex geometry that introduces
Capacitive ⇒ Impact on the energy dissipation and the power
distribution.
Resistive ⇒ Increase in propagation delay
Inductive ⇒ An introduction of extra noise sources, which affects the
reliability of the circuit.
⇒ For todays integrated circuits with their millions of circuit nodes, it
becomes useless.
⇒ The circuit behavior at a given circuit node is only determined by a
few dominant parameters.
Dr. Varun Kumar (IIIT Surat) IIIT Surat 4 / 9

5. Continued–
⇒ Two way to solve this complex problem
Design optimization
Follow a design process by a trial-and-error operation
⇒ Designer has a clear insight in the parasitic wiring effects, their relative
importance, and their models.
⇒ Substantial simplifications for VLSI design can be ,
Inductive effects can be ignored if the resistance of the wire is large.
When the interconnect material used has a low resistivity, a
capacitance-only model can be used.
Inter-wire capacitance can be ignored (neighboring wires is large or
wires only run together for a short distance) and all the parasitic
capacitance can be modeled as capacitance to ground.
Dr. Varun Kumar (IIIT Surat) IIIT Surat 5 / 9

6. Interconnect Parameters - Capacitance, Resistance, and Inductance
Capacitance
⇒ An accurate modeling of the wire capacitance(s) is a non-trivial task.
⇒ The capacitance of such a wire is a function of
Shape
Environment
Distance to the substrate
Distance to surrounding wires
⇒ If W >> tdi the electrical-field lines are orthogonal to the capacitor
plates, and that its capacitance can be modeled by the parallel-plate
capacitor
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7. Continued–
Resistance
⇒ The resistance of a wire is proportional to its length L and inversily
proportional to its cross-section A.
R = ρ
L
A
ρ → Resistivity of the material
⇒ Aluminum is the most common interconnect material.
Low cost
Compatibility with the standard IC fabrication process
Material ρ (Ω-m)
Silver (Ag) 1.6 ×10−8
Copper (Cu) 1.7 ×10−8
Gold (Au) 2.2×10−8
Aluminum (Al) 2.7×10−8
Tungsten (W) 5.5×10−8
Dr. Varun Kumar (IIIT Surat) IIIT Surat 7 / 9

8. Skin effect for different width of conductor
δ =
r
ρ
πf µ
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9. Continued–
Inductance
Inductance starts to play a role on a chip.
Adoption of low-resistive interconnect materials
Increasing of switching frequencies (GHz order)
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