This document discusses VLSI circuit design and focuses on wire characterization and performance estimation. It covers several topics related to wires including wire resistance, capacitance, RC delay, crosstalk, and the use of repeaters. Modern chip designs rely heavily on wires, known as interconnects, to connect transistors. As process technologies shrink, wires become more important for determining chip speed, power consumption, and noise.
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The Roman Empire, a vast and enduring power, stands as one of history's most remarkable civilizations, leaving an indelible imprint on the world. It emerged from the Roman Republic, transitioning into an imperial powerhouse under the leadership of Augustus Caesar in 27 BCE. This transformation marked the beginning of an era defined by unprecedented territorial expansion, architectural marvels, and profound cultural influence.
The empire's roots lie in the city of Rome, founded, according to legend, by Romulus in 753 BCE. Over centuries, Rome evolved from a small settlement to a formidable republic, characterized by a complex political system with elected officials and checks on power. However, internal strife, class conflicts, and military ambitions paved the way for the end of the Republic. Julius Caesar’s dictatorship and subsequent assassination in 44 BCE created a power vacuum, leading to a civil war. Octavian, later Augustus, emerged victorious, heralding the Roman Empire’s birth.
Under Augustus, the empire experienced the Pax Romana, a 200-year period of relative peace and stability. Augustus reformed the military, established efficient administrative systems, and initiated grand construction projects. The empire's borders expanded, encompassing territories from Britain to Egypt and from Spain to the Euphrates. Roman legions, renowned for their discipline and engineering prowess, secured and maintained these vast territories, building roads, fortifications, and cities that facilitated control and integration.
The Roman Empire’s society was hierarchical, with a rigid class system. At the top were the patricians, wealthy elites who held significant political power. Below them were the plebeians, free citizens with limited political influence, and the vast numbers of slaves who formed the backbone of the economy. The family unit was central, governed by the paterfamilias, the male head who held absolute authority.
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Operation “Blue Star” is the only event in the history of Independent India where the state went into war with its own people. Even after about 40 years it is not clear if it was culmination of states anger over people of the region, a political game of power or start of dictatorial chapter in the democratic setup.
The people of Punjab felt alienated from main stream due to denial of their just demands during a long democratic struggle since independence. As it happen all over the word, it led to militant struggle with great loss of lives of military, police and civilian personnel. Killing of Indira Gandhi and massacre of innocent Sikhs in Delhi and other India cities was also associated with this movement.
3. Introduction
• Chips are mostly made of wires called interconnect
• In stick diagram, wires set size
• Transistors are little things under the wires
• Many layers of wires
• Wires are as important as transistors
• Speed
• Power
• Noise
• Alternating layers run orthogonally
4. Wire Geometry
• Pitch = w + s
• Aspect ratio: AR = t/w
• Old processes had AR << 1
• Modern processes have AR 2
• Pack in many skinny wires
l
w s
t
h
5. Layer Stack
• AMI 0.6 mm process has 3 metal layers
• Modern processes use 6-10+ metal layers
• Example:
Intel 180 nm process
• M1: thin, narrow (< 3l)
• High density cells
• M2-M4: thicker
• For longer wires
• M5-M6: thickest
• For VDD, GND, clk
Layer T (nm) W (nm) S (nm) AR
6 1720 860 860 2.0
1000
5 1600 800 800 2.0
1000
4 1080 540 540 2.0
700
3 700 320 320 2.2
700
2 700 320 320 2.2
700
1 480 250 250 1.9
800
Substrate
8. Interconnect Slide 8
Wire Resistance
• r = resistivity (W*m)
• R = sheet resistance (W/)
• is a dimensionless unit(!)
• Count number of squares
• R = R * (# of squares) l
w
t
1RectangularBlock
R = R (L/W) W
4RectangularBlocks
R =R (2L/2W) W
= R (L/W) W
t
l
w w
l
l l
R R
t w w
r
9. Choice of Metals
• Until 180 nm generation, most wires were aluminum
• Modern processes often use copper
• Cu atoms diffuse into silicon and damage FETs
• Must be surrounded by a diffusion barrier
Metal Bulk resistivity (mW*cm)
Silver (Ag) 1.6
Copper (Cu) 1.7
Gold (Au) 2.2
Aluminum (Al) 2.8
Tungsten (W) 5.3
Molybdenum (Mo) 5.3
11. Contacts Resistance
• Contacts and vias also have 2-20 W
• Use many contacts for lower R
• Many small contacts for current crowding around periphery
12. Wire Capacitance
• Wire has capacitance per unit length
• To neighbors
• To layers above and below
• Ctotal = Ctop + Cbot + 2Cadj
layer n+1
layer n
layer n-1
Cadj
Ctop
Cbot
w
s
t
h1
h2
13. Capacitance Trends
• Parallel plate equation: C = eA/d
• Wires are not parallel plates, but obey trends
• Increasing area (W, t) increases capacitance
• Increasing distance (s, h) decreases capacitance
• Dielectric constant
• e = ke0
• e0 = 8.85 x 10-14 F/cm (dielectric constant of free space)
• k = 3.9 for SiO2
• Processes are starting to use low-k dielectrics
• k 3 (or less) as dielectrics use air pockets
15. M2 Capacitance Data
• Typical wires have ~ 0.2 fF/mm
• Compare to 2 fF/mm for gate capacitance
0
50
100
150
200
250
300
350
400
0 500 1000 1500 2000
C
total
(aF/mm)
w (nm)
Isolated
M1, M3 planes
s = 320
s = 480
s = 640
s=
8
s = 320
s = 480
s = 640
s=
8
16. Diffusion & Polysilicon
• Diffusion capacitance is very high (about 2 fF/mm)
• Comparable to gate capacitance
• Diffusion also has high resistance
• Avoid using diffusion runners for wires!
• Polysilicon has lower C but high R
• Use for transistor gates
• Occasionally for very short wires between gates
17. Lumped Element Models
• Wires are a distributed system
• Approximate with lumped element models
• 3-segment p-model is accurate to 3% in simulation
• L-model needs 100 segments for same accuracy!
• Use single segment p-model for Elmore delay
C
R
C/N
R/N
C/N
R/N
C/N
R/N
C/N
R/N
R
C
L-model
R
C/2 C/2
R/2 R/2
C
N segments
p-model T-model
18. Example
• Metal2 wire in 180 nm process
• 5 mm long
• 0.32 mm wide
• Construct a 3-segment p-model
• R = 0.05 W/ => R = 781 W
• Cpermicron = 0.2 fF/mm => C = 1 pF
260 W
167 fF 167 fF
260 W
167 fF 167 fF
260 W
167 fF 167 fF
19. Wire RC Delay
• Estimate the delay of a 10x inverter driving a 2x inverter at
the end of the 5mm wire from the previous example.
• R = 2.5 kW*mm for gates
• Unit inverter: 0.36 mm nMOS, 0.72 mm pMOS
• tpd = 1.1 ns
781 W
500 fF 500 fF
Driver Wire
4 fF
Load
690 W
20. Crosstalk
• A capacitor does not like to change its voltage
instantaneously.
• A wire has high capacitance to its neighbor.
• When the neighbor switches from 1-> 0 or 0->1, the wire tends to
switch too.
• Called capacitive coupling or crosstalk.
• Crosstalk effects
• Noise on nonswitching wires
• Increased delay on switching wires
21. Crosstalk Delay
• Assume layers above and below on average are quiet
• Second terminal of capacitor can be ignored
• Model as Cgnd = Ctop + Cbot
• Effective Cadj depends on behavior of neighbors
• Miller effect
A B
Cadj
Cgnd Cgnd
B DV Ceff(A) MCF
Constant VDD Cgnd + Cadj 1
Switching with A 0 Cgnd 0
Switching opposite A 2VDD Cgnd + 2 Cadj 2
22. Crosstalk Noise
• Crosstalk causes noise on nonswitching wires
• If victim is floating:
• model as capacitive voltage divider
Cadj
Cgnd-v
Aggressor
Victim
DVaggressor
DVvictim
adj
victim aggressor
gnd v adj
C
V V
C C
D D
23. Driven Victims
• Usually victim is driven by a gate that fights noise
• Noise depends on relative resistances
• Victim driver is in linear region, agg. in saturation
• If sizes are same, Raggressor = 2-4 x Rvictim
1
1
adj
victim aggressor
gnd v adj
C
V V
C C k
D D
aggressor gnd a adj
aggressor
victim victim gnd v adj
R C C
k
R C C
Cadj
Cgnd-v
Aggressor
Victim
DVaggressor
DVvictim
Raggressor
Rvictim
Cgnd-a
25. Noise Implications
• So what if we have noise?
• If the noise is less than the noise margin, nothing happens
• Static CMOS logic will eventually settle to correct output
even if disturbed by large noise spikes
• But glitches cause extra delay
• Also cause extra power from false transitions
• Dynamic logic never recovers from glitches
• Memories and other sensitive circuits also can produce the
wrong answer
27. Repeaters
• R and C are proportional to l
• RC delay is proportional to l2
• Unacceptably great for long wires
• Break long wires into N shorter segments
• Drive each one with an inverter or buffer
Wire Length: l
Driver Receiver
l/N
Driver
Segment
Repeater
l/N
Repeater
l/N
Receiver
Repeater
NSegments
28. Repeater Design
• How many repeaters should we use?
• How large should each one be?
• Equivalent Circuit
• Wire length l
• Wire Capacitance Cw*l, Resistance Rw*l
• Inverter width W (nMOS = W, pMOS = 2W)
• Gate Capacitance C’*W, Resistance R/W
R/W
C'W
Cw
l/2N Cw
l/2N
Rw
lN
29. Repeater Results
• Write equation for Elmore Delay
• Differentiate with respect to W and N
• Set equal to 0, solve
2
w w
l RC
N R C
2 2
pd
w w
t
RC R C
l
w
w
RC
W
R C
~60-80 ps/mm
in 180 nm process