Switched capacitor circuits_shish

Title: Introduction to Switched-Capacitor
Circuits

 Introduction
 General considerations
 Sampling switches
 Speed considerations
 Precision considerations
 Switched capacitor Amplifiers
 Switched capacitor Integrator
 Switched capacitor Common-Mode feedback
Fraunhofer IIS/EAS 2

 I/p signal continuously available (& applied)  o/p signal continuously observed
 Continuous-time systems
Applications : Audio, Video & High speed analog systems
 I/p signal sensed at periodic instants of time  sample & hold  o/p is processed
sample signal  Discrete-time /sampled-data systems
Applications : Filters, comparators in ADCs, DACs
 A common class of ‘discrete-time’ system is called as Switched-Capacitor circuits.

To understand the motivation for sampled-data circuits :
First let us consider the continuous-time amplifier, where Vout/Vin is ideally equal to
−R2/R1.
this circuit presents a difficult issue if implemented in CMOS technology, as R2 heavily drops
the open-loop gain, degrading the precision of the circuit.
Fig. 1: Continuous-time feedback amplifier

To avoid reducing the open-loop gain of the op amp, the resistors can be replaced by
capacitors[Fig.2(a)]. Ideally the gain is given by the impedance ratios : −C1/C2
 The node X in above circuit is not biased, so we add a large feedback resistor to provide dc
feedback [Fig.2(b)].
Exhibits high-pass transfer function, indicating that
Vout/Vin ≈ −C1/C2 only if ω >>(RfC2)−1
Fig. 2: (a)Continuous-time feedback amplifier using capacitor; (b) use of resistor to define bias
point

 Replacing Rf by a switch provides proper bias at node X and also a path for capacitive feedback.
S2 is on  forces VX to VB  Unity gain op-amp
S2 is off  VX = VB  Vin is amplified
Optimising the above circuit, yields SC circuit with 3 switches controlling the operation.
 S1 and S3 connect the left plate of C1 to Vin and ground
respectively;
 S2 as feedback switch.
Fig.3: Switch replacing feedback resistor
Fig.4: Switched-capacitor Amplifier

Fig.5: Operation of SC amplifier
Case 1 : (Sample)
S1 and S2 are ON
S3 is OFF
C1 is charged to Vin,
VA ≈ Vin
Vout ≈ 0
Case 2 : (Amplify)
S1 and S2 are OFF
S3 is ON
Charge on C1 is transferred to C2
VA ≈ 0 (Node A pulled to gnd)
Vout ≈ Vin(C1/C2)
 Assuming that the op-amp in Fig. 4. has very high open-loop gain, following cases are
analyzed.
 In addition to the analog input, Vin, the circuit requires a clock to define each phase

 The output voltage change should also be understood by the transfer of charges.
 The charge stored on C1 just before t0 is equal to Vin*C1.
After t = t0, the negative feedback through C2 drives the op amp input differential voltage, and
hence the voltage across C1, to zero (Fig. 6).
The charge stored on C1 at t = t0 must then be transferred to C2, producing an output voltage
equal to Vin(C1/C2).
Thus, the circuit amplifies Vin by a factor of (C1/C2)
Note : The feedback capacitor does not reduce the open-loop gain of the amplifier (if the output
voltage is given enough time to settle). Where as in Fig. 1, R2 loads the amplifier continuously.
Fig.6: Transfer of charge from C1 to C2

 A simple sampling circuit consists of a switch and a capacitor. A mos transistor can
serve as a switch because ‘It can be on while carrying zero current’.
 Vg is ON Mosfet as switch connects source & drain
 Vg is OFF  Mosfet isolates source & drain
Case 1: Assume that Vin=0 and the capacitor has an initial
voltage equal to Vdd. [Vd = Vdd, Vg = Vdd, Vs=0]
CK = high(Vdd) at t = t0 ; Vgs = Vds = Vdd.
M1  saturation, drawing Idsat from CH when
t > t0, Vout tends to fall, driving M1 into triode region.
Case 2: Now let Vin = 1V; Vout = 0; Vdd= 3V
Here, terminal connected to CH acts as source.
CK = high(Vdd) at t = t0 ; [Vd = 1V, Vg = Vdd, Vs=0]
M1  triode region, charging CH until
Vout = Vin (1V)
Fraunhofer IIS/EAS
Fig.7: Implementation of mosfet as switch
9
Saturation 
triode
Triode 
saturation

The previous observations reveal two important points.
First, a MOS switch can conduct current in either direction simply by exchanging the role of
its source and drain terminals.
Second, when the switch is on, Vout follows Vin, and when the switch is off, Vout remains
constant.
Thus, the circuit ‘tracks’ the signal when CK is high and ‘freezes’ the instantaneous value of Vin
across CH when CK goes low.
Fig.8: Track and hold function of SC
ON
OFF

 Nmos switches :
Vin = Vdd ???
[Vd= Vdd, Vs = 0, Vg= Vdd]
M1  Saturation
Vout = Vdd-Vth 
Vout does not follow Vin, if the
input is very high.
Vin(max) = Vdd-Vth
 Pmos switches :
Vin ≤ |Vthp|???
If gate is grounded and Vd ≤ |Vthp|,
M1 fails to act as switch.
 Vin(min) > |Vthp|
Fig.9: Nmos switch Fig.10: Pmos switch

 A simple measure of speed is the time required for Vout to go from 0 Vin0 , after S turns on.
Since the Vout would take infinite time to become equal to Vin0, we consider the output settled
when it is within a certain “error band”, ∆V around the final value. [∆V / Vin  accuracy, ex. 0.1
%]
 the circuit in Fig. 11, we surmise that the sampling speed is given by two factors:
 the on resistance of the switch
 the value of the sampling capacitor.
Thus, to achieve a higher speed, a large aspect ratio and a small capacitor must be used.
Fig.11: Speed in sampling circuit

The on-resistance also depends on the input level applied, we need large variation of Ron for better
voltage swings.
From Fig. 9 & 10, we observe that nmos and pmos switch limits the swing at each extremes.
It is then interesting to employ ‘complementary’ switches so as to allow rail-to-tail swings.
Such a combination requires complementary clocks which turns the switches off simultaneously. An
equivalent resistance is:
Fig.12: Complementary switch and its Ron,eq
Fig.13: Distortion when complimentary switches
do not turn off simultaneously

 Previously we discussed about speed issues, but these methods of increasing the speed degrade the
precision with which the signal is sampled.
Three mechanisms in MOS transistor operation introduce error at the instant the switch turns off.
3.3.1 Channel charge injection:
When the switch turns off, Qch exits through the source and drain terminals, a phenomenon called
‘channel charge injection’.
The charge injected to the left side of Fig. 14 is absorbed by the input source, creating no error. On
the other hand, the charge injected to the right side is deposited on CH , introducing an error in the
voltage stored on the capacitor
Fig.14: Effect of charge injection

3.3.2 Clock Feedthrough:
A MOS switch couples the clock transitions to the sampling capacitor through its gate-drain or gate-
source overlap capacitance, the effect introduces an error in the sampled output voltage.
The error ∆V is independent of the input level, exhibiting itself as a constant offset in the
input/output characteristics.
As with charge injection, clock feedthrough leads to a trade-off between speed and precision as well.
Fig.15: Clock feedthrough efffect

3.3.3 kT/C Noise:
 A resistor charging a capacitor gives rise to a rms noise voltage of 𝑘𝑇/𝐶 , similarly the Ron of
switch introduces thermal noise at the o/p.
This noise is stored on the capacitor along with sampled voltage when the switch is turned off.
In order to achieve low noise, the sampling capacitor must be sufficiently large, thus loading other
circuits and degrading the speed.
Fig.16: Thermal noise in sampling circuit

The charge injection contributes three types of errors in MOS sampling circuits:
gain error, dc offsets and nonlinearity.
In many applications, the first two can be tolerated or corrected whereas the last cannot.
First technique: The charge injected by M1 can be removed by a dummy transistor M2, with a
complementary signal at gate.
The assumption of equal splitting of charge between source and drain is generally invalid,
making this approach less attractive.
Fig.17: Dummy device technique

Second Technique: Another approach is the use of complementary switches, such that the opposite
charge packets injected by the two cancel each other.
For∆q1 to cancel ∆q2, we must have
W1L1Cox (VCK − Vin − VTHN) = W2L2Cox (Vin − |VTHP |)
Thus, the cancellation occurs for only one input level !
Incomplete cancellation of clock feedthrough as well.
Third technique: The use of differential operation provides best way to cancel charge injection.
∆q1 = WLCox (VCK − Vin1 − VTH1) and
∆q2 =WLCox (VCK − Vin2 − VT H2)
we observe that ∆q1 = ∆q2 only if Vin1 = Vin2.
This technique removes constant offset and lowers the
n nonlinear component.
Fig.18: Complementary switches
Fig.19: Differential sampling switches

The CMOS feedback amplifiers are more easily implemented with a capacitive feedback network
than with a resistor.
 Let us now consider and analyze few SC amplifiers.
 A unity-gain amplifier can be realized with no resistors or capacitors in the feedback network, but
for discrete-time applications, it still requires a sampling circuit.
Fig.20: Unity gain buffer with sampling switches
 Sampling Mode:
S1 & S2 On; S3 Off; t< t0
CH tracks Vin reaching to V0
Vout = Vx=0.
 Amplification Mode:
At t= t0 , Vin =V0
S1 & S2 Off; S3 On;
Node X  still virtual ground,
Charge on CH must be conserved,
Vout rises to V0
Flipping of capacitor around the op-amp circuit
enters amplification node.

4.1.1 Precision considerations:
S2’s effect: When S2 turns off, it injects a charge packet ∆q2 onto CH , producing an error equal to
∆q2/CH . However, this charge is independent of the input level because node X is a virtual ground.
For ex: If S2 is realized by an NMOS device whose gate voltage equals VCK , then
The constant magnitude of ∆q2 means that the channel charge of S2 introduces only an offset (rather
than gain error or nonlinearity) in the input/output characteristic.
S1’s effect: After S2 turns off, node X ‘floats’, maintaining a constant total charge regardless of the
transitions at other nodes of the circuit. As a result, after the feedback configuration is formed, the
Vout is not influenced by the charge injection due to S1 (∆q1).
The charge injection by S1 introduces no error if S2 turns off first.
S3’s effect: In order to turn on, S3 must establish an inversion layer at its oxide interface. The
required charge should be supplied from CH or op-amp, but we see the charge on CH remains same
(V0CH ), unaffected when S3 is off.
The channel charge of this switch is therefore entirely supplied by the op amp, introducing no
error.
∆q2 =WLCox (VCK −VT H -Vx)

Differential op amp along with two sampling capacitors allows complete cancellation of channel
charge injection, by differential operation.
4.1.2 Speed considerations:
 In the amplification mode, the circuit must begin with Vout ≈0 and eventually produce Vout ≈ V0.
 Let us rewrite the unity gain buffer configuration with input capacitance and load capacitance.
Fig.21: Differential realization of unity gain buffer
Node X and Y should have equal charges.
Seq, suppresses the charge injection mismatch
between S2 and S2`.

If Cin is relatively small, we can assume that the voltages across CL and CH do not change
instantaneously, concluding that if Vout ≈ 0 and VCH ≈ V0, then Vx = −V0 at the beginning of the
amplification mode.
In other words, the input difference sensed by the op amp initially jumps to a large value, possibly
causing the op amp to slew. The slewing continuous until Vx is sufficiently close to the Vin.
It reveals that Cin of the opamp degrades both the speed and precision of the unity-gain buffer.
For this reason, the bottom plate of CH is usually driven by the input signal or the output of the op
amp, and the top plate is connected to node X.
This technique is called ‘bottom-plate sampling’,
 minimizes the parasitic capacitance seen from node X to ground.
 also avoids the injection of substrate noise to node X
Fig.22: Time response of unity gain buffer (amplification mode) Fig.23: Bottom sampling technique

The critical advantage of the unity-gain sampler is the input-independent charge injection.
 In the sampling mode, S1 and S2 are on and S3 is off, creating a virtual ground at X and allowing
the voltage across C1 to track the input voltage.
At the end of sampling mode, S2 turns off first, injecting a constant charge, ∆q2, onto node X.
 Subsequently, S1 turns off and S3 turns on. Since VP goes from Vin0 to 0, the output voltage
changes from 0 to approximately Vin0(C1/C2) providing a voltage gain equal to (C1/C2).
Vout has same polarity as that of Vin and Av is greater than unity.
Fig.24: Non-inverting amplifier
Fig.25: Sampling mode and transition to amplification mode respectively

4.2.1 Precision considerations
S1’s effect: The charge injected by S1∆q1, changes the voltage at node P by approximately
∆VP=∆q1/C1 , and hence the output voltage by -∆q1(C1/C2).
After S3 turns on, Vp drops to zero. Thus the overall change in Vp is equal to 0-Vin0=-Vin0 ,
producing an overall change in the output equal to -Vin0(-C1/C2) =Vin0(C1/C2).
Since the output voltage of interest is measured after node P is connected to ground, the charge
injected by S1 does not affect the final output.
Fig.26: Effect of charge injected by S1
VP goes from one fixed voltage, Vin0  0, with
an intermediate perturbation due to S1

After S2 is off, the total charge at node X remains constant, making the circuit insensitive to
charge injection of S1 or charge “absorption” of S3.
In summary, proper timing ensures that node X is perturbed only by the charge injection of S2,
making the final value of Vout free from errors due to S1 and S3.
The constant offset due to S2 can be suppressed by differential operation.
Fig.27: Charge redistribution in noninverting amplifier.
S2 is off, charge on right plate of C1 is –VinoC1
Total charge at node X is constant  even if S2 is off
Node P pulled to ground  voltage across C1 is 0, hence
Charge -VinoC1 is transferred on left plate of C2.
Fig.28: Differential realization non-inverting amp

Speed consideration :
The feedback capacitor is made smaller so as to get a high closed loop gain (gain factor C1/C2).
 The smaller feedback factor C2 suggests that the time response of the amplifier may be slower than that
of the unity-gain sampler.
 While a larger C2 introduces heavier loading at the output and provides a greater feedback factor.
 The circuit in fig.24 can operate in high closed-loop gain, but it suffers from speed and precision
degradation due to the low feedback factor.
 This topology that provides a nominal gain of two while achieving a higher speed and lower gain error.
4.2.2 Precision Multiply-by-two circuit
Fig.29: Multiply-by-two circuit;

 The amplifier incorporates two equal capacitors, C1=C2=C. In the sampling mode, the circuit is
configured as in (a), establishing a virtual ground at X and allowing the voltage across C1 and C2 to
track Vin.
 In transition to the amplification mode, S3 turns off first, C1 is placed around the op-amp and the left
plate of C2 is switched to ground.
 The moment S3 turns off, the total charge on C1 and C2 equals 2Vin0C and the voltage across C2
approaches zero in the amplification mode(c).
 The final voltage across C1 and hence the output voltage are approximately equal to 2Vin0.
 The advantage of the circuit is the higher feedback factor (2) for a given closed-loop gain.
Precision :
The charge injected by S1 and S2 and absorbed by S4 and S5 is unimportant and the one, injected by S3
introduces a constant offset which is removed by differential operation.
Fig.30: Transition of multiply-by-two circuit from sampling to amplification mode

In a continuous-time integrator, if the op-amp gain is very large, the output of which can be
expressed as:
To devise a discrete-time counter part, consider a resistor connected between two nodes, carrying a
current equal to (VA- VB)/R.
The role of the resistor is to take a certain amount of charge from node A every second and move it to
node B
Now, consider a capacitor CS is alternately connected to nodes A and B at a clock rate fck.
Fig.31: Continuous time integrator
Fig.32: Continuous time and discrete time resistors

The average current flowing from A to B is then equal to the charge moved in one clock period:
We can therefore view the circuit as a “resistor” equal to (CS fCK )−1, this property formed the
foundation for many modern switched-capacitor circuits.
By replacing this discrete-time resistor in fig. 31, we get an integrator which operates on sampled
data systems.
From fig. 33, for every clock cycle, C1 absorbs a charge equal to C1*Vin when S1 is on and deposits
the charge on C2 when S2 is on (node X is a virtual ground.)
If Vin is constant, output changes by Vin(C1/C2) at every clock cycle. By approximating the staircase
waveform by a ramp, we note that the circuit behaves as an integrator.
Fig.33: Discrete time integrator and its response

This integrator suffers from two drawbacks :
 The input-dependent charge injection of S1 introduces nonlinearity in the charge stored on C1 and
hence the output voltage.
 The nonlinear capacitance at node P resulting from the source/drain junctions of S1 and S2 leads to
a nonlinear charge-to-voltage conversion when C1 is switched to X.
An integrator topology that resolves both of the foregoing issues is shown in fig.34. Lets study the
circuit’s operation in the sampling and integration modes.
Fig.34: Parasitic insensitive discrete time integrator
 Sampling Mode:
S1 & S3  On
S2 & S4  Off
C1 tracks Vin
op-amp & C2 hold previous value
 Integration Mode:
S3  Off  injecting ∆q1 to C1
S1  Off
S2 & S4  On
Charge transfer C1  C2
(through virtual ground node)

Precision consideration :
 Since S3 turns off first, it introduces only a constant offset, which can be suppressed by
differential operation.
 The charge injection or absorption S1 and S2 contributes no error, because thy drive only the left
plate of C1. (same as on non-inverting amps)
 As node X is a virtual ground, the charge injected or absorbed by S4 is constant and independent
of Vin.
 The voltage across the nonlinear(junction) capacitance changes by a very small amount, the
resulting nonlinearity is negligible.

In fully differential opamp, CMFB is needed to keep the opamp safe from output mismatches.
Sensing the output CM level by resistors lowers the diff. Av and in case of mosfet it suffers from
limited linear range.
Switched-capacitor CMFB provides a good solution, where the outputs are sensed by capacitors. In
fig.35, equal capacitors C1 & C2 reproduce the average of the changes in each o/p voltage at node X.
The output CM level is the equal to Vgs5 + (voltage across C1 &C2)
Vout1 & Vout2  positive/negative
CM change
Vx & ID5  increase/decrease
Vout1 & Vout2 are pulled/pushed
down
Fig.35: Simple SC CMFB

How is the voltage across C1 and C2 defined?
This is typically carried out when the amplifier is in the sampling (or reset) mode and can be
accomplished.
To understand this, consider the fig.36:
 The amplifier differential input is zero and switch S1 is on. Transistors M6 and M7 operate as a
linear sense circuit because their gate voltages are nominally equal.
 Thus, the circuit settles such that the output CM level is equal to Vgs6,7 + Vgs5.
 At the end of this mode, S1 turns off, leaving a voltage equal to Vgs6,7 across C1 and C2.
Fig.36: Defining voltage across C1& C2 in SC CMFB

In applications where the output CM level must be defined more accurately than in the previous
example, the topology shown in Fig. 37 may be used.
Here, in the reset mode, one plate of C1 and C2 is switched to VCM while the other is connected to the
gate of M6.
 Each capacitor therefore sustains a voltage equal to VCM − VGS6.
In the amplification mode, S2 and S3 are on and the other switches are off, yielding an output CM
level equal to VCM − Vgs6 + Vgs5.
This value is equal to VCM if ID3 and ID4 are copied properly from IREF so that Vgs6 = Vgs5.
Fig.37: Alternative topology for defining output CM level

 This presentation is just to summarize the chapter 13 from the book “Design of
Analog CMOS IC”, Behzad Razavi [2nd edition]
 All images and writings are from the above book.

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