The summary provides an overview of the key points about interfacing with the DS1307 real-time clock (RTC) chip using the I2C protocol: 1) The document discusses the I2C protocol signals and components used to interface with the DS1307 RTC, which stores time and date data. 2) It describes initializing the I2C bus, addressing the DS1307 slave device, and transmitting/receiving data to read from and write to the RTC registers. 3) The DS1307 has registers to store seconds, minutes, hours, date, and other time/date fields in BCD format and can output a square wave time signal on its SQW pin at different frequencies.

1. Inter-integrated Circuit (I2
C)
Protocol and
DS1307 RTC Interfacing
Presented by:-Bhargav Kakadiya (140070110006)

2. The I2
C Protocol
• Developed by Philips in late 1980s
• Version 1.0 published in 1992
– Supports standard (100 Kbps) and fast (400 Kbps) mode
• Version 2.0 published in 1998
– High-speed mode (3.4 Mbps) added
• Classifies devices into slave and master
• Allows multiple masters to be attached to the same bus
• The master device uses either a 7-bit or 10-bit address to specify
the slave device as its partner of data communication.
• Supports bi-directional data transfer
• Allows multiple masters (microcontrollers) to share the same
peripheral devices

3. I2
C Signal Level
• Float high and driven low
• Use the SCL signal to carry clock signal to synchronize
data transfer
• Use the SDA signal to carry data and address
• The SDA and SCL pins of I2
C devices (masters and
slaves) are open-drain and need external pull up
resistors.
• The resistors 2.2 KΩ and 1 K Ω are recommended for
100 Kbps and 400 Kbps baud rate.

4. +VDD
RP
RP
CLK1
OUT
CLK1
IN
Data1
OUT
Data1
IN
CLK2
OUT
CLK2
IN
Data2
OUT
Data2
IN
Device1 Device2
SDA line
SCL line
Figure 11.1Connecting standard- andfast-mode devices to theI2Cbus

5. Signal Components
• I2
C data transfer consists of 5 signal
components:
– Start (S)
– Stop (P)
– Repeated Start (R)
– Data
– Acknowledge (A)

6. SDA
SCL
Figure 11.2 I2C Start condition
Start Condition
• Used to indicate that a device would like to
transfer data on the I2
C bus
• Represented by the SDA line going low when
the clock (SCL) signal is high
• Will initialize the I2
C bus

7. SDA
SCL
Figure 11.3 Stop (P) condition
Stop Condition
• A condition that a device wants to release the I2
C bus
• Is represented by the SDA signal going high when the
SCL signal is high
• Once the stop condition is complete, both the SCL and
SDA signals are high. This is the idle bus.

8. SDA
SCL
Figure 11.4Restart condition
start condtion
data transfer restart
condition
Repeated Start (R) Condition
• A Start signal generated without first generating a Stop
condition to terminate the communication
• Used by the master to communicate with another slave
or change data transfer direction without releasing the
bus
• Also referred to as Restart condition

9. SDA
SCL
Figure 11.5 I2
Cbus dataelements
Note. Data bit is always stable when clock (SCL) is high
Data
• It represents the transfer of eight bits of information.
• Data on the SDA line is considered valid only when the SCL signal
is high.
• When the SCL signal is low, the data is allowed to change.
• The eight-bit data may be a control code, an address, or data.

10. SDA
SCL
Figure11.6 ACKcondition
SDA
SCL
Figure11.7 NACKcondition
Acknowledge (ACK) Condition
• Data transfer needs to be acknowledged either positively (A) or
negatively (NACK).
• A device acknowledges a byte it receives positively by bringing the
SDA line low during the ninth clock pulse of SCL.
• If the device allows the SDA line to float high, it is transmitting a
negative acknowledge (NACK).

11. Synchronization (1 of 2)
• All masters generate their clocks on the SCL line to transfer
messages on the I2C bus.
• A defined clock is needed for the bit-by-bit arbitration procedure to
take place.
• Most microcontrollers generate the SCL clock by counting down a
programmable reload value using the instruction clock signal.
• Clock synchronization occurs when multiple masters attempt to
drive the I2C bus and before the arbitration scheme can decide
which master is the winner.
• Clock synchronization is performed using the wired-AND connection
of I2C interfaces to the SCL line.
• The high-to-low transition on the SCL line causes the devices
concerned (masters) to start counting off their low period.

12. Synchronization (2 of 2)
• A master device that is counting off their low period will hold the SCL
line low until the counter is count down to 0. At this point, the device
will release the SCL line to high.
• If there are other devices holding the SCL low, then the SCL line will
remain low until all master devices have counted down to 0. At this
point, the SCL line will go high and all devices will start to count
high.
• The SCL line will be held low by the device with the longest low
period.
• By the same reasoning, the high period of the SCL signal is
determined by the device with the shortest high period.

13. wait
state
start counting
high period
counter
reset
CLK1
CLK2
SCL
Figure 11.8 Clock synchronization during the
arbitrationprocedure
Handshaking
• The clock synchronization mechanism can be used as a
handshake in data transfer.
• Slave device can hold the SCL line low after completion
of one byte transfer (9 bits).
• Slave halts the bus until it gets ready for the next
operation and then release the SCL line.

14. master 1 loses arbitration
Data 1 ≠ SDA
SCL
Data1
Data2
SDA
Figure 11.9 Arbitration procedure of two masters
Arbitration
• In the event two or more master devices attempt to begin a transfer at the
same time, an arbitration scheme is employed to force one or more masters
to give up the bus.
• The master devices continue to transmit data until one master attempts to
send a high while the other transmits a low.
• Since the SDA bus has open drain, the master device that attempts to send
a high will detect a low. At this point, it will stop driving the bus.
• The arbitration process does not slow down the winning master’s transfer
and no data gets lost.

15. A6 A5 A4 A3 A2 A1 A0 R/W
Figure 11.13a 7-bit I2C address
1 1 1 1 0 A9 A8 R/W A7 A6 A5 A4 A3 A2 A1 A0
Figure 11.13b 10-bit I2C address
I2
C Addressing Methods
• I2
C protocol allows master devices to use either the 7-bit and 10-bit
address to specify the slave device for data communication.
• The 7-bit addressing uses the upper 7 bits of the address byte for
address and the least significant bit to specify the data transfer
direction. The format is shown in Figure 11.13.
• The 10-bit addressing uses two bytes to carry the address
information.
– The bit 0 of the high byte is used to indicate the data transfer direction.
– The upper 7 bits have the pattern of 1111 0xx with xx representing the
most significant two address bits of the slave.
– The second byte carries the lower 8 address bits.

16. S Slave address R/W A Data A Data A/A P
data transferred
(n bytes + acknowledge)
'0' (write)
from master to slave
from slave to master
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = start condition
P = stop condition
Figure 11.10 A master-transmitter addressing a slave receiver with a 7-bit address.
The transfer direction is not changed.
Data Transfer Format (7-bit Addressing) (1 of 2)
• Master transmitter to slave receiver – shown in Figure 11.10
• Master reads slave immediately after the first byte (address byte) –
shown in Figure 11.11
• Combined format. A master may transfer some data to the slave and
then generate a restart condition to read data from the slave or
send/read data to/from other slave-- shown in Figure 11.12.

17. S Slave address R/W A Data Data P
data transferred
(n bytes + acknowledge)
'1' (read)
Figure 11.11 A master reads a slave immediately after the first byte
AA
S Slave address R/W A Data Data
read or
write
Figure 11.12 Combined format
A/A R Slave address R/W A/A P
(n bytes +
ack.)
repeated
start
read or
write
A
(n bytes +
ack.)*
direction of
transfer may
change at this
point
* not shaded because
transfer direction of data
and acknowledge bits
depends on R/W bits
Data Transfer Format (7-bit Addressing) (2 of 2)

18. TWI

19. TWBR
TWBR selects the division factor for the bit rate generator. The bit
rate generator is a frequency divider which generates the SCL clock
frequency in the Master modes.
TWBR = Value of the TWI Bit Rate Register
TWPS = Value of the prescaler bits in the TWI Status Register

20. TWSR
Bits [7:3] – TWS: TWI Status
These five bits reflect the status of the TWI logic and the Two-wire Serial Bus. The
different status codes are described later in this section. Note that the value read from
TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application
designer should mask the prescaler bits to zero when checking the Status bits. This
makes status checking independent of prescaler setting. This approach is used in this
datasheet, unless otherwise noted.
Bit 2 – Reserved Bit
This bit is reserved and will always read as zero.
Bits [1:0] – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.

21. TWCR
Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects
application software response. If the I-bit in SREG and TWIE in TWCR are set, the
MCU will jump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL
low period is stretched.
Bit 6 – TWEA: TWI Enable Acknowledge Bit
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is
written to one, the ACK pulse is generated
Bit 5 – TWSTA: TWI START Condition Bit
The application writes the TWSTA bit to one when it desires to become a master on
the Two wire Serial Bus. The TWI hardware checks if the bus is available, and
generates a START condition on the bus if it is free.
Bit 4 – TWSTO: TWI STOP Condition Bit
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the
Two-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO
bit is cleared automatically.

22. Bit 3 – TWWC: TWI Write Collision Flag
The TWWC bit is set when attempting to write to the TWI Data Register –
TWDR when TWINT is low. This flag is cleared by writing the TWDR Register
when TWINT is high.
• Bit 2 – TWEN: TWI Enable Bit
The TWEN bit enables TWI operation and activates the TWI interface. When
TWEN is written to one, the TWI takes control over the I/O pins connected to
the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit
is written to zero, the TWI is switched off and all TWI transmissions are
terminated, regardless of any ongoing operation.
• Bit 1 – Reserved Bit
This bit is a reserved bit and will always read as zero.
• Bit 0 – TWIE: TWI Interrupt Enable
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt
request will be activated for as long as the TWINT Flag is high.

23. TWDR
These eight bits contain the next data byte to be transmitted, or the
latest data byte received on the Two-wire Serial Bus.
In Transmit mode, TWDR contains the next byte to be transmitted.
In Receive mode, the TWDR contains the last byte received.

24. TWAR
These seven bits constitute the slave address of the TWI unit.
The TWAR should be loaded with the 7-bit slave address (in the
seven most significant bits of TWAR) to which the TWI will
respond when programmed as a slave transmitter or receiver. In
multimaster systems, TWAR must be set in masters which can be
addressed as slaves by other masters.

25. 1X1
2X2
3VBAT
4GND
8
7
6
5 SDA
SCL
SQWOUT
VCC
DS1307
Oscillator
and divider
X1 X2
square
wave out
SQWOUT
power
control
VCC
VBAT
GND
serial bus
interface
SCL
SDA
control
logic
address
register
RTC
RAM
(56x8)
Figure 11.27 DS1307 pin assignment and block diagram
The Serial Real-Time Clock DS1307
• Uses BCD format to represent the clock and calendar information
• Has 56 bytes to store critical information
• Clock calendar provides seconds, minutes, hours, day, date, month, and year information
• Operates in either the 24-hour or 12-hour format with AM/PM indicator
• Has built-in power sense circuit that detects power failure and automatically switches to the
battery supply
• The SQW output frequency may be 1 Hz, 4 KHz, 8 KHz, and 32 KHz.

26. $00
$07
$08
$3F
seconds
minutes
hours
day
date
month
year
control
RAM
56 x 8
Figure 11.28 DS1307 address map
$01
$02
$03
$04
$05
$06
CH 10 seconds seconds
10 minutes0
0
minutes
hours12
24
10 HR
A/P
10 HR
0 0 0 0 0 day
0 0
0 0 0
10 date
10
month
date
month
year10 year
out sqwe0 0 0 0 RS1 RS0
Figure 11.29 Contents of RTC registers
Bit 7 Bit 0
- Bit 6 of the hours register selects whether the 12-hour or 24-hour
mode is used.
- Bit 5 of the hours register selects whether the current time is AM or
PM if 12-hour mode is selected.
DS1307 Address Map

27. Interfacing with ATMega32

28. Table11.7 Squarewaveoutputfrequency
RS1 RS0 SQWoutputfrequency
0
0
1
1
0
1
0
1
1 Hz
4.096 KHz
8.192 KHz
32.768 KHz
DS1307 Control Register
• Bit 7 controls the output level of the SQWOUT pin when
the square output is disabled.
• The SQWE bit enables/disables the SQWOUT pin
output.
• Bits 1 and 0 select the output frequency of the SQWOUT
pin.

29. DS1307 Write Operation

30. DS1307 Read Operation

31. THANK YOU