Philips Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire bus for efficient inter-IC control. This bus is called the Inter-IC or I2C-bus which is a 8-bit oriented serial bus. Only two bus lines are required:
a serial data line (SDA)
a serial clock line (SCL).
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems. It was invented by Philips and now it is used by almost all major IC manufacturers. Each I2C slave device needs an address – they must still be obtained from NXP (formerly Philips semiconductors).
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems.
Slow peripheral interfaces (i2 c spi uart)PREMAL GAJJAR
The Serial Peripheral Interface or SPI bus is a synchronous serial data link, a de facto standard, named by Motorola, that operates in full duplex mode. It is used for short distance, single master communication, for example in embedded systems, sensors, and SD cards.
AMBA AHB is a bus interface suitable for high-performance synthesizable designs. It defines the interface between components, such as masters, interconnects, and slaves.
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems. It was invented by Philips and now it is used by almost all major IC manufacturers. Each I2C slave device needs an address – they must still be obtained from NXP (formerly Philips semiconductors).
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems.
Slow peripheral interfaces (i2 c spi uart)PREMAL GAJJAR
The Serial Peripheral Interface or SPI bus is a synchronous serial data link, a de facto standard, named by Motorola, that operates in full duplex mode. It is used for short distance, single master communication, for example in embedded systems, sensors, and SD cards.
AMBA AHB is a bus interface suitable for high-performance synthesizable designs. It defines the interface between components, such as masters, interconnects, and slaves.
Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift registers, sensors, and SD cards.
SPI is a serial bus standard established by Motorola and supported in silicon products from various manufacturers.
It is a synchronous serial data link that operates in full duplex (signals carrying data go in both directions simultaneously).
Devices communicate using a master/slave relationship, in which the master initiates the data frame. When the master generates a clock and selects a slave device, data may be transferred in either or both directions simultaneously.
This presentation discusses the details of the I2C protocol and interfacing of EEPROM with 8051 based on I2C protocol. It also discusses the other applications of I2C protocol
Serial peripheral Interface - Embedded System ProtocolAditya Porwal
Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by micro-controllers for communicating with one or more peripheral devices quickly over short distances. It can also be used for communication between two micro-controllers.
UVM RAL is an object-oriented model for registers inside the design. To access these design registers, UVM RAL provides ready-made base classes and APIs
Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift registers, sensors, and SD cards.
SPI is a serial bus standard established by Motorola and supported in silicon products from various manufacturers.
It is a synchronous serial data link that operates in full duplex (signals carrying data go in both directions simultaneously).
Devices communicate using a master/slave relationship, in which the master initiates the data frame. When the master generates a clock and selects a slave device, data may be transferred in either or both directions simultaneously.
This presentation discusses the details of the I2C protocol and interfacing of EEPROM with 8051 based on I2C protocol. It also discusses the other applications of I2C protocol
Serial peripheral Interface - Embedded System ProtocolAditya Porwal
Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by micro-controllers for communicating with one or more peripheral devices quickly over short distances. It can also be used for communication between two micro-controllers.
UVM RAL is an object-oriented model for registers inside the design. To access these design registers, UVM RAL provides ready-made base classes and APIs
I²C (Inter-Integrated Circuit), pronounced I-squared-C, is a multi-master, multi-slave, single-ended, serial computer bus invented by Philips Semiconductor (now NXP Semiconductors). It is typically used for attaching lower-speed peripheral ICs to processors and microcontrollers. Alternatively I²C is spelled I2C (pronounced I-two-C) or IIC (pronounced I-I-C).
Since October 10, 2006, no licensing fees are required to implement the I²C protocol. However, fees are still required to obtain I²C slave addresses allocated by NXP.[1]
Several competitors, such as Siemens AG (later Infineon Technologies AG, now Intel mobile communications), NEC, Texas Instruments, STMicroelectronics (formerly SGS-Thomson), Motorola (later Freescale), and Intersil, have introduced compatible I²C products to the market since the mid-1990s.
SMBus, defined by Intel in 1995, is a subset of I²C that defines the protocols more strictly. One purpose of SMBus is to promote robustness and interoperability. Accordingly, modern I²C systems incorporate policies and rules from SMBus, sometimes supporting both I²C and SMBus, requiring only minimal reconfiguration.
The Serial Peripheral Interface (SPI) bus is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems. The interface was developed by Motorola and has become a de facto standard. Typical applications include sensors, Secure Digital cards, and liquid crystal displays.
SPI devices communicate in full duplex mode using a master-slave architecture with a single master. The master device originates the frame for reading and writing. Multiple slave devices are supported through selection with individual slave select (SS) lines.
Sometimes SPI is called a four-wire serial bus, contrasting with three-, two-, and one-wire serial buses. The SPI may be accurately described as a synchronous serial interface,[1] but it is different from the Synchronous Serial Interface (SSI) protocol, which is also a four-wire synchronous serial communication protocol, but employs differential signaling and provides only a single simplex communication channel.
Implementation of I2C Master Bus Protocol on FPGAIJERA Editor
The focus of this paper is on I2C (Inter-Integrated Circuit) protocol interface between Master Bus protocol and
slave. Here we are interfacing between micro-controller and DS1307. I2C bus protocol sends 8 bit data from
micro-controller to DS1307. This module was designed in VHDL and simulated and synthesized using Xilinx
ISE Design Suite 14.2. I2C and optimized for area and power. This concept is widely applicable from any high
speed device or low speed device to any low speed device or high speed device. This module acts as a slave for
the DS1307 at the same time acts like a master for the micro-controller device which can be considered as a
slave. . It can be used to interface low speed peripherals like motherboard, embedded system, mobile phones,
set top boxes, DVD, PDA’s or other electronic devices.
An Implementation of I2C Slave Interface using Verilog HDLIJMER
The focus of this paper is on implementation of Inter Integrated Circuit (I2C) protocol
following slave module for no data loss. In this paper, the principle and the operation of I2C bus protocol
will be introduced. It follows the I2C specification to provide device addressing, read/write operation and
an acknowledgement. The programmable nature of device provide users with the flexibility of configuring
the I2C slave device to any legal slave address to avoid the slave address collision on an I2C bus with
multiple slave devices. This paper demonstrates how I2C Master controller transmits and receives data to
and from the Slave with proper synchronization.
The module is designed in Verilog and simulated in ModelSim. The design is also synthesized in Xilinx
XST 14.1. This module acts as a slave for the microprocessor which can be customized for no data loss.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
HEAP SORT ILLUSTRATED WITH HEAPIFY, BUILD HEAP FOR DYNAMIC ARRAYS.
Heap sort is a comparison-based sorting technique based on Binary Heap data structure. It is similar to the selection sort where we first find the minimum element and place the minimum element at the beginning. Repeat the same process for the remaining elements.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
For more technical information, visit our website https://intellaparts.com
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
4. Philips Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire bus for efficient inter-IC control. This bus is
called the Inter-IC or I2C-bus which is a 8-bit oriented serial bus. Only two bus lines are required:
a serial data line (SDA)
a serial clock line (SCL).
Data transfers operation modes:
1) Standard-mode >> up to 100 kbit/s
2) Fast-mode >> up to 400 kbit/s
3) Fast-mode plus (Fm+) >> up to 1 Mbit/s
4) High-speed mode >> up to 3.4 Mbit/s
5) Ultra Fast-mode (uni-directional mode) >> up to 5 Mbit/s
6)
7)
All I2C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C-bus.
This design concept solves the many interfacing problems encountered when designing digital control circuits.
Introduction
Mostafa KhamisI2C-Bus Design and Verification Specs
5. Some intelligent control, usually a single-chip micro—controller
General-purpose circuits like LCD and LED drivers, remote I/O ports, RAM, EEPROM, real-time clocks or A/D and D/A
converters
Application-oriented circuits such as digital tuning and signal processing circuits for radio and video systems, temperature
sensors, and smart cards
I2C-bus Applications:
Mostafa KhamisI2C-Bus Design and Verification Specs
6. Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL).
Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at
all times; masters can operate as master-transmitters or as master-receivers.
It is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters
simultaneously initiate data transfer.
Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in
the Fast-mode, up to 1 Mbit/s in Fast-mode Plus, or up to 3.4 Mbit/s in the High-speed mode. The freq could be easily
programmed by software.
Serial, 8-bit oriented, unidirectional data transfers up to 5 Mbit/s in Ultra Fast-mode
The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance. More capacitance
may be allowed under some conditions.
I2C Features
Mostafa KhamisI2C-Bus Design and Verification Specs
7. Compatible with multiple masters.
Includes clock stretching, so it could support a wait state generation.
The acknowledge bit is software programmable.
The core has interrupt driven byte-by-byte data transfers.
The core supports different modes of operating conditions like- start, stop, repeated start and detects these conditions.
Support to detect if the bus is busy processing other requests.
Provides support for both 7-bit and 10-bit addressing modes.
I2C Features
Mostafa KhamisI2C-Bus Design and Verification Specs
8. Terminology
The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected
to it. As masters are usually microcontrollers, let us consider the case of a data transfer between two microcontrollers
connected to the I2 C-bus
Mostafa KhamisI2C-Bus Design and Verification Specs
9. Terminology
A is a master, addresses B(Slave)
For transmission and receiving
A terminates the transfer
A generates the clk signals
Mostafa KhamisI2C-Bus Design and Verification Specs
12. Start and Stop Conditions
From high to low
while SCL is high
From low to high
while SCL is high
Generated by the master
The bus is considered to be busy after start (S) condition and free after stop (P)
The same for repeated start (Sr)
Mostafa KhamisI2C-Bus Design and Verification Specs
14. ACK and NACK
The Acknowledge signal is defined as follows: the transmitter releases the SDA line during the acknowledge clock
pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock
pulse. Set-up and hold times must also be taken into account.
When SDA remains HIGH during this ninth clock pulse, this is defined as the Not Acknowledge signal. The master
can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new
transfer.
NACK Conditions:
No receiver is present on the bus with the transmitted address so there is no device to respond with an
acknowledge.
The slave is unable to receive or transmit because it is performing some real-time function and is not ready to
start communication with the master.
During the transfer, the receiver gets data or commands that it does not understand.
During the transfer, the receiver cannot receive any more data bytes.
A master-receiver must signal the end of the transfer to the slave transmitter.
Mostafa KhamisI2C-Bus Design and Verification Specs
15. Slave Address and R/W bit
Mostafa KhamisI2C-Bus Design and Verification Specs
16. Slave Address and R/W bit
A master-transmitter addressing
a slave receiver with a 7-bit address
A master reads a slave immediately after the first byte
Combined format
Mostafa KhamisI2C-Bus Design and Verification Specs
17. 10-bit Addressing
10-bit addressing expands the number of possible addresses
The first seven bits of the first byte are the combination 1111 0XX of which the last two bits (XX) are the two Most-
Significant Bits (MSB) of the 10-bit address; the eighth bit of the first byte is the R/W bit that determines the
direction of the message.
The remaining first 5 bits are reserved for future I2C bus enhancements.
A master-transmitter addresses a slave-receiver with a 10-bit address
A master-receiver addresses a slave-transmitter with a 10-bit address
Mostafa KhamisI2C-Bus Design and Verification Specs
19. General Call Address
This format is done to write or program all slaves that are connected on the I2C bus.
The master is waiting for acknowledgement at least from one slave.
The general call address format
When B = ‘0’: The second byte has the following meanings:
0000 0110 (06h): Reset and write programmable part of slave address by hardware.
0000 0100 (04h): Write programmable part of slave address by hardware.
0000 0000 (00h): This code is not allowed to be used as the second byte.
When B = ‘1’: The second byte is a hardware general call, this means that the transmitted sequence is sent by a
hardware master device, such as keyboard scanner (which can be programmed to transmit a desired slave
address).
Note: the remaining 7-bits are for the hardware master
address to acknowledge all connected slaves.
Mostafa KhamisI2C-Bus Design and Verification Specs
20. Bus Clear
If the data line (SDA) is stuck LOW, the master should send nine clock pulses.
The device that held the bus LOW should release it sometime within those nine clocks.
If not, then use the HW reset or cycle power to clear the bus.
Mostafa KhamisI2C-Bus Design and Verification Specs
21. Device ID
An optional 3-byte read-only (24 bits) word giving the following information:
Could be accessed as follows:
1) START condition
2) The master sends the Reserved Device ID I2C-bus address followed by the R/W bit set to ‘0’ (write): ‘1111 1000’.
3) The master sends the I2C-bus slave address of the slave device it must identify.
4) The master sends a Re-START condition.
5) The master sends the Reserved Device ID I2C-bus address followed by the R/W bit set to ‘1’ (read): ‘1111 1001’.
6) The Device ID Read can be done, starting with the 12 manufacturer bits followed by the nine part identification bits, and then the
three die revision bits.
7) The master ends the reading sequence by NACKing the last byte, thus resetting the slave device state machine and allowing the
master to send the STOP condition.
8)
1) Note: If the master continues to ACK the bytes after the third byte, the slave rolls back to the first byte and keeps sending the
Device ID sequence until a NACK has been detected.
Mostafa KhamisI2C-Bus Design and Verification Specs
Twelve bits with the manufacturer name, unique per manufacturer
Nine bits with the part identification, assigned by manufacturer
Three bits with the die revision, assigned by manufacturer
24. If two or more masters try to put information onto the bus, the first to produce a ‘one’ when the other produces a ‘zero’ loses
the arbitration. The clock signals during arbitration are a synchronized combination of the clocks generated by the masters using
the wired-AND connection to the SCL line.
Slaves are not included in the arbitration procedure.
Arbitration proceeds bit by bit. During every bit, while SCL is HIGH, each master checks to see if the SDA level matches what
it has sent.
Two masters can actually complete an entire transaction without error, as long as the transmissions are identical.
A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration and
must restart its transaction when the bus is free.
Arbitration Logic
Mostafa KhamisI2C-Bus Design and Verification Specs
25.
Undefined conditions, if the arbitration procedure is still in progress at the moment when one master sends a repeated
START or a STOP condition:
Master 1 sends a repeated START condition and master 2 sends a data bit.
Master 1 sends a STOP condition and master 2 sends a data bit.
Master 1 sends a repeated START condition and master 2 sends a STOP condition.
Arbitration Procedure
Mostafa KhamisI2C-Bus Design and Verification Specs
27. Generation of clock signals on the I2C-bus is always the responsibility of master devices; each master generates its own clock
signals when transferring data on the bus. Bus clock signals from a master can only be altered when they are stretched by a slow
slave device holding down the clock line or by another master when arbitration occurs.
Two masters can begin transmitting on a free bus at the same time and there must be a method for deciding which takes
control of the bus and complete its transmission. This is done by clock synchronization and arbitration using the wired-AND.
In single master systems, clock synchronization and arbitration are not needed.
Synchronization Logic
A synchronized SCL clock is generated with its
LOW period determined by the master with the
longest clock LOW period, and its HIGH period
determined by the one with the shortest clock
HIGH period.
Mostafa KhamisI2C-Bus Design and Verification Specs
29. Instead of the master and slave agreeing to a predefined baud rate, the master controls the clock speed.
Optional procedure, for pausing the transaction by holding the SCL to low.
The transaction cannot continue until the line is released HIGH again
Slaves are not applicable to stretch the clock because they don’t have SCL driver.
For byte date level, when being sent in a fast rate, the device needs more time to store the byte before start another one.
So, a clock stretching here is needed after reception and acknowledgement of a byte by forcing the master into a wait state.
Also, it can be used to slow down the bus clk when communicating with other controller with/without limited hardware.
Clock Stretching
Mostafa KhamisI2C-Bus Design and Verification Specs
31. Operates from DC to 5 MHz transmitting data in one direction.
It is most useful for speeds greater than 1 MHz to drive LED controllers and other devices that do not need feedback.
Is based on the standard protocol which consists of START, slave address, command bit, ninth clock, and a STOP bit. But the
command bit is a ‘write’ only, and the data bit on the ninth clock is driven HIGH, ignoring the ACK cycle due to the
unidirectional nature of the bus.
The 2-wire push-pull driver consists of a UFm serial clock (USCL) and serial data (USDA).
Since UFm I2C-bus uses push-pull drivers, it does not have the multi-master capability of the wired-AND open-drain Sm, Fm,
and Fm+ I2C-buses.
The possibility of connecting more than one UFm master to the UFm I2C-bus is not allowed due to bus contention on the
push-pull outputs. (One Hot MUX)
Ultra Fast-mode (Ufm) protocol
Mostafa KhamisI2C-Bus Design and Verification Specs
37. Prescaler 16-bits registers:
The prescaler factor can be determined through the following equation: prescaler = (peripheral_clock / (5 * desired_SCL)) -1.
Control Register:
Transmit Register:
Receive Register
I2C-Bus Registers
Mostafa KhamisI2C-Bus Design and Verification Specs
38. Command Register:
To generate and tells the Core what commands to do next. All the bits of this register are automatically cleared
and are usually read as Zeros.
I2C-Bus Registers
Mostafa KhamisI2C-Bus Design and Verification Specs
39. Status Register:
Gives information about the status of the core and if any data transfer is in progress.
I2C-Bus Registers
Mostafa KhamisI2C-Bus Design and Verification Specs
42. I2C Interface:
It consists of Clock, Reset, SCL, and SDA signals for communication with the bus functional model and DUT.
I2C BFM:
It is used as drivers to drive the I2C interface signals through untimed separated tasks.
UVM driver controls the BFM anyway and calls the tasks in BFM.
UVM monitor also can call the BFM tasks to read from the DUT.
I2C BFM Tasks:
Reset Task
Write Task
It takes in the arguments delay, the master interface handle, the address and the data that needs to be
written
Read Task
It is similar to the write task in terms of the parameter it takes in but instead of writing data, the task read
data from the given address
I2C-Bus UVM Environment
Mostafa KhamisI2C-Bus Design and Verification Specs