The focus of this paper is on I2C (Inter-Integrated Circuit) protocol interface between Master Bus protocol and
slave. Here we are interfacing between micro-controller and DS1307. I2C bus protocol sends 8 bit data from
micro-controller to DS1307. This module was designed in VHDL and simulated and synthesized using Xilinx
ISE Design Suite 14.2. I2C and optimized for area and power. This concept is widely applicable from any high
speed device or low speed device to any low speed device or high speed device. This module acts as a slave for
the DS1307 at the same time acts like a master for the micro-controller device which can be considered as a
slave. . It can be used to interface low speed peripherals like motherboard, embedded system, mobile phones,
set top boxes, DVD, PDA’s or other electronic devices.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An Implementation of I2C Slave Interface using Verilog HDLIJMER
The focus of this paper is on implementation of Inter Integrated Circuit (I2C) protocol
following slave module for no data loss. In this paper, the principle and the operation of I2C bus protocol
will be introduced. It follows the I2C specification to provide device addressing, read/write operation and
an acknowledgement. The programmable nature of device provide users with the flexibility of configuring
the I2C slave device to any legal slave address to avoid the slave address collision on an I2C bus with
multiple slave devices. This paper demonstrates how I2C Master controller transmits and receives data to
and from the Slave with proper synchronization.
The module is designed in Verilog and simulated in ModelSim. The design is also synthesized in Xilinx
XST 14.1. This module acts as a slave for the microprocessor which can be customized for no data loss.
This presentation discusses the details of the I2C protocol and interfacing of EEPROM with 8051 based on I2C protocol. It also discusses the other applications of I2C protocol
I2c interfacing raspberry pi to arduinoMike Ochtman
A complete reference how-to guide to connect and interface a Raspberry Pi and an Arduino over I2C using Python and smbus. Including how to configure both Raspberry Pi and Arduino to start communication over TWI/I2C
Full source code and documentation at https://github.com/MikeOchtman/Pi_Arduino_I2C
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An Implementation of I2C Slave Interface using Verilog HDLIJMER
The focus of this paper is on implementation of Inter Integrated Circuit (I2C) protocol
following slave module for no data loss. In this paper, the principle and the operation of I2C bus protocol
will be introduced. It follows the I2C specification to provide device addressing, read/write operation and
an acknowledgement. The programmable nature of device provide users with the flexibility of configuring
the I2C slave device to any legal slave address to avoid the slave address collision on an I2C bus with
multiple slave devices. This paper demonstrates how I2C Master controller transmits and receives data to
and from the Slave with proper synchronization.
The module is designed in Verilog and simulated in ModelSim. The design is also synthesized in Xilinx
XST 14.1. This module acts as a slave for the microprocessor which can be customized for no data loss.
This presentation discusses the details of the I2C protocol and interfacing of EEPROM with 8051 based on I2C protocol. It also discusses the other applications of I2C protocol
I2c interfacing raspberry pi to arduinoMike Ochtman
A complete reference how-to guide to connect and interface a Raspberry Pi and an Arduino over I2C using Python and smbus. Including how to configure both Raspberry Pi and Arduino to start communication over TWI/I2C
Full source code and documentation at https://github.com/MikeOchtman/Pi_Arduino_I2C
COVERAGE DRIVEN VERIFICATION OF I2C PROTOCOL USING SYSTEM VERILOGIAEME Publication
The rapid advances in the integration technologies, enables fabrication of millions of transistors in single IC/Chip. So as the design grows, the verification techniques are required to meet the correctness of the design without exercising exhaustive input - output combination. This paper accommodates reusability of I2C protocol under various test environmen ts, by the following System Verilog which support the complexities of the SoC designs. Here, The RTL Design of I2C is obtained from Opencore.org and its functional verification is carried by self, using System verilog completely wrap DUT.The whole verifica tion done using system verilog Hardware description and Verification language(HDVL), simulated on Questa Sim 10.0b. The concept of seed is used to control the quality of random number generator (RNG) algorithm to run the same test case. The functional cove rage found using Constraint random verification(C RV) approach is 100% and code coverage found is 86.88% & for DUT 93%.
Design &Implementation of I2C Master Controller Interfaced With RAM Using VHDLIJERA Editor
In most of the applications, the physical systems require a real-time operation to interface high speed constraints. In most of the applications, the physical systems require a real-time operation to interface high speed constraints. The Inter Integrated Circuits (I2C) is a 2-wireed communication bus. Physically, it consists of 2 active wires: SDA (Serial Data), SCL (Serial Clock) and a ground connection. All I2C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C-bus.
This paper focuses on the software implementation for I2C Driver and its interfacing with RAM. Specifically, this paper describes in detail an I2C Master connected to I 2C Slave using an I2C bus. The I2C protocol was given by Philips Semiconductors for faster devices to communicate with slower devices and each other without data loss. The complete module is designed in VHDL and simulated in Xilinx ISE 14.5.
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems.
this presentation contains all sort of information regarding USCI(Universal Serial Communication Interface)
UART, SPI, I2C etc.
this will be very helpful to the people those who are planning or starting projects or want to get idea how devices interfaced.
Serial peripheral Interface - Embedded System ProtocolAditya Porwal
Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by micro-controllers for communicating with one or more peripheral devices quickly over short distances. It can also be used for communication between two micro-controllers.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
COVERAGE DRIVEN VERIFICATION OF I2C PROTOCOL USING SYSTEM VERILOGIAEME Publication
The rapid advances in the integration technologies, enables fabrication of millions of transistors in single IC/Chip. So as the design grows, the verification techniques are required to meet the correctness of the design without exercising exhaustive input - output combination. This paper accommodates reusability of I2C protocol under various test environmen ts, by the following System Verilog which support the complexities of the SoC designs. Here, The RTL Design of I2C is obtained from Opencore.org and its functional verification is carried by self, using System verilog completely wrap DUT.The whole verifica tion done using system verilog Hardware description and Verification language(HDVL), simulated on Questa Sim 10.0b. The concept of seed is used to control the quality of random number generator (RNG) algorithm to run the same test case. The functional cove rage found using Constraint random verification(C RV) approach is 100% and code coverage found is 86.88% & for DUT 93%.
Design &Implementation of I2C Master Controller Interfaced With RAM Using VHDLIJERA Editor
In most of the applications, the physical systems require a real-time operation to interface high speed constraints. In most of the applications, the physical systems require a real-time operation to interface high speed constraints. The Inter Integrated Circuits (I2C) is a 2-wireed communication bus. Physically, it consists of 2 active wires: SDA (Serial Data), SCL (Serial Clock) and a ground connection. All I2C-bus compatible devices incorporate an on-chip interface which allows them to communicate directly with each other via the I2C-bus.
This paper focuses on the software implementation for I2C Driver and its interfacing with RAM. Specifically, this paper describes in detail an I2C Master connected to I 2C Slave using an I2C bus. The I2C protocol was given by Philips Semiconductors for faster devices to communicate with slower devices and each other without data loss. The complete module is designed in VHDL and simulated in Xilinx ISE 14.5.
I2C is a serial protocol for two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in embedded systems.
this presentation contains all sort of information regarding USCI(Universal Serial Communication Interface)
UART, SPI, I2C etc.
this will be very helpful to the people those who are planning or starting projects or want to get idea how devices interfaced.
Serial peripheral Interface - Embedded System ProtocolAditya Porwal
Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by micro-controllers for communicating with one or more peripheral devices quickly over short distances. It can also be used for communication between two micro-controllers.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Finite Element Simulation of Plasma Transferred ARC Welding [PTAW] of Structu...IJERA Editor
Plasma transferred Arc welding is one of the most widely used welding process, in which the metals are fused just above the melting point, and makes the metal to fuse. It is employed in many applications like tool die and metal casting, strip metal welding etc. This investigation is to analyze temperature distribution residual stress and distortion by varying the heat source parameter in SYSWELD, and compared the results with ANSYS. The simulation of Plasma Transferred Arc welding was of structural steel plate performed using a non-linear transient heat transfer analysis. Heat losses due to convection and variation of material properties with temperature were considered in this analysis. To incorporate the heat developed the Gaussian distribution was considered. Finite element simulations were performed using ANSYS Parametric Design Language (APDL) code and using SYSWELD. The temperatures obtained were compared with experimental results for validation. It was found that the predicted values of temperature agree very well with the experimental values. Residual Stress and Distortion were also predicted for various heat Input. The effect of heat input on residual stress and distortion was investigated.
Join this video course on udemy . Click here :
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In this course, the code is developed such a way that, It can be ported to any MCU you have at your hand.
If you need any help in porting these codes to different MCUs you can always reach out to me!
The course is strictly not bound to any 1 type of MCU. So, if you already have any Development board which runs with ARM-Cortex M3/M4 processor,
then I recommend you to continue using it.
But if you don’t have any Development board, then check out the below Development boards.
This ppt explains Metal Detector Robotic Vehicle, student is provided with his/her authorized tag to swipe over the reader to record their attendance.
Edgefxkits.com has a wide range of electronic projects ideas that are primarily helpful for ECE, EEE and EIE students and the ideas can be applied for real life purposes as well.
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Visit our page to get more ideas on popular electronic projects developed by professionals.
Edgefx provides free verified electronic projects kits around the world with abstracts, circuit diagrams, and free electronic software. We provide guidance manual for Do It Yourself Kits (DIY) with the modules at best price along with free shipping.
Philips Semiconductors (now NXP Semiconductors) developed a simple bidirectional 2-wire bus for efficient inter-IC control. This bus is called the Inter-IC or I2C-bus which is a 8-bit oriented serial bus. Only two bus lines are required:
a serial data line (SDA)
a serial clock line (SCL).
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
Understanding Inductive Bias in Machine LearningSUTEJAS
This presentation explores the concept of inductive bias in machine learning. It explains how algorithms come with built-in assumptions and preferences that guide the learning process. You'll learn about the different types of inductive bias and how they can impact the performance and generalizability of machine learning models.
The presentation also covers the positive and negative aspects of inductive bias, along with strategies for mitigating potential drawbacks. We'll explore examples of how bias manifests in algorithms like neural networks and decision trees.
By understanding inductive bias, you can gain valuable insights into how machine learning models work and make informed decisions when building and deploying them.
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...
Implementation of I2C Master Bus Protocol on FPGA
1. Regu Archana Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 10 ( Version 5), October 2014, pp.06-10
www.ijera.com 6 | P a g e
Implementation of I2
C Master Bus Protocol on FPGA
Regu Archana, Mr. J.V.Rao
M.Tech (VLSI), ECE Dept Vignan Institute of Technology & Science Deshmukhi, Hyderabad
Ph.D ECE Dept, Associate Professor, Vignan Institute of Technology & Science Deshmukhi, Hyderabad
ABSTRACT
The focus of this paper is on I2
C (Inter-Integrated Circuit) protocol interface between Master Bus protocol and
slave. Here we are interfacing between micro-controller and DS1307. I2
C bus protocol sends 8 bit data from
micro-controller to DS1307. This module was designed in VHDL and simulated and synthesized using Xilinx
ISE Design Suite 14.2. I2
C and optimized for area and power. This concept is widely applicable from any high
speed device or low speed device to any low speed device or high speed device. This module acts as a slave for
the DS1307 at the same time acts like a master for the micro-controller device which can be considered as a
slave. . It can be used to interface low speed peripherals like motherboard, embedded system, mobile phones,
set top boxes, DVD, PDA’s or other electronic devices.
I. INTRODUCTION
The bus protocol which manages the
communication between the ICs within a system and
between the systems is called the Inter-IC bus or I2
C
bus. In the world of multiple application based
product it is very much a mandatory to have multiple
devices connected to a system, this includes
peripherals following different communication
protocols as well. This requirement give rise to the
need for an intermediate system which can act as a
bridge between two or more devices following
different communication protocols. This is where I2
C
master protocol design is very useful. Today a
system is connected to a number of devices and
make the communication smooth and fast, I2
C bus
protocol is considered as one of the best. DS1307 is
low speed peripherals is taken as slave. The I2
C
master protocol on one end is connected to micro-
controller interface and on the other end it is
connected to ds1307 interface. Its main function will
be, to understand the control register transmitted by
micro-controller and convert it into DS1307 low
speed signals.
Fig.1 demonstrates the overview of the
functionality of the I2
C master protocol. In this
project, we are implementing I2
C bus protocol for
interfacing low speed peripheral devices on FPGA. It
is also the best bus for the control applications,
where devices may have to be added or removed. I2
C
protocol can also be used for communication
between multiple circuit boards in equipments with
or without using a shielded cable depending on the
distance and speed of data transfer. I2
C bus is a
medium for communication where master protocol is
used to send and receive data to and from the slave
DS1307. The low speed peripheral, DS1307 is
interfaced with I2
C master bus interface and
synthesized. Fig-1 shows the I2
C bus system with the
I2
C master protocol implemented on a FPGA and the
DS1307 interface acting as the slave. One micro-
controller can communicate with any number of
devices with I2
C protocol with different speeds. In
this project I2
C protocol we are taking two modes
,if mode '0' is selected by I2
C protocol according to
slave speed then the clock frequency will selected
which is "clock divide 2 for 400khz". If mode '1' is
selected , then this means that clock frequency is
selected which is "clock divide by 4 for 400khz ".
Fig 1: Functional Block Diagram
II. PROPOSED WORK
As mentioned earlier, the I2
C bus consists of
only two lines, SDA and SCL. Both of these lines are
open-drained, and must be pulled up to VCC with a
5.6KΩ resistor. Regardless of how many devices are
connected to the bus, only one pull-up resister is
needed per line. Furthermore, the SCL line needs to
be pulled up with a resistor only if there will be two
or more masters in the system, or when the slave will
do clock stretching as a flow-control measure. In the
first case, the pull-up resistor on the SCL line is
required for arbitration purposes when two or more
masters try to initiate a data transfer at the same time.
RESEARCH ARTICLE OPEN ACCESS
2. Regu Archana Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 10 ( Version 5), October 2014, pp.06-10
www.ijera.com 7 | P a g e
An arbitration procedure has been defined to avoid
the chaos that might ensue from such an event. In the
second case, a receiver may not be ready to receive
data from the transmitter, and so it will hold the SCL
line low to “stretch” the clock to delay the
transmitter.
III. I2
C Protocol
The I2
C bus is idle when both SCL and SDA are
at a logic 1 level. The master initiates a data transfer
by issuing a START condition, which is a high to low
transition on the SDA line while the SCL line is high
as shown in Figure 2 (a). The bus is considered to be
busy after the START condition. After the START
condition, a slave address is sent out on the bus by
the master. This address is 7 bits long followed by an
eighth bit which is a data direction bit (R/W) where a
0 indicates a write from the master to the slave and a
1 indicates a read from the slave to the master. The
master, who is controlling the SCL line, will send out
the bits on the SDA line, one bit per clock cycle of
the SCL line, with the most significant bit sent out
first. The value on the SDA line can be changed only
when the SCL line is at a low.
Fig. 2 (a) Start condition (b) Stop Condition
The slave device whose address matches the
address that is being sent out by the master will
respond with an acknowledgment bit on the SDA line
by pulling the SDA line low during the ninth clock
cycle of the SCL line as shown in Figure 3. The
direction bit (R/W) determines whether the master or
the slave will be the transmitter in the subsequent
data transmission after the sending of the slave
address. Every byte put on the SDA line for
transmission must be 8-bits long with the most
significant bit first. Except for the START and STOP
conditions, the SDA line must not changed when the
SCL line is high. The number of bytes that can be
transmitted is unrestricted. Each byte has to be
followed by an acknowledge bit. The acknowledge-
related clock pulse is generated by the master. The
transmitter releases the SDA line (sets it high) during
the acknowledge clock pulse, and the receiver must
pull down the SDA line during the acknowledge
clock pulse to acknowledge the receipt of the byte.
The one exception is when a master-receiver is
involved in a transfer. In this case the master-receiver
must signal the end of data to the slave-transmitter by
not generating an acknowledge on the last byte that
was clocked out of the slave.
To signal the end of data transfer, the master will
send a STOP condition by pulling the SDA line from
low to high while the SCL line is at a high as shown
in Figure 2 (b). Instead of sending a STOP condition,
the master can send a repeated START condition so
that the master can change the direction of the data
transmission without having to release the bus.
IV. Serial Data Communication
The I2
C bus has two modes of operation: master
transmitter and master receiver. The I2
C master bus
initiates data transfer and can drive both SDA and
SCL lines. Slave device (DS1307) is addressed by the
master. It can issue only data on the SDA line.
In master transmission mode, after the initiation
of the START sequence, the master sends out a slave
address. The address byte contains the 7 bit DS1307
address, which is 1101000, followed by the direction
bit (R/ w ). After receiving and decoding the address
byte the device outputs acknowledge on the SDA
line. After the DS1307 acknowledges the slave
address + write bit, the master transmits a register
address to the DS1307 this will set the register
pointer on the DS1307. The master will then begin
transmitting each byte of data with the DS1307
acknowledging each byte received. The master will
generate a stop condition to terminate the data write.
In master receiver mode, the first byte is received
and handled as in the master transmission mode.
However, in this mode, the direction bit will indicate
that the transfer direction is reversed. Serial data is
transmitted on SDA by the DS1307 while the serial
clock is input on SCL. START and STOP conditions
are recognized as the beginning and end of a serial
transfer (Fig-5). The address byte is the first byte
received after the start condition is generated by the
master. The address byte contains the 7-bit DS1307
address, which is 1101000, followed by the direction
bit (R/ w ). After receiving and decoding the address
byte the device inputs acknowledge on the SDA line.
The DS1307 then begins to transmit data starting
with the register address pointed to by the register
pointer. If the register pointer is not written before
the initiation of a read mode, the first address that is
read is the last one stored in the register pointer. The
DS1307 must receive a “not acknowledged” to end a
read.
3. Regu Archana Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 10 ( Version 5), October 2014, pp.06-10
www.ijera.com 8 | P a g e
Fig. 5 - Master Receiver Mode
Fig. 6: Acknowledgement on the I2
C Bus
MAXIM DS1307:
The DS1307 supports a bi-directional, 2- wire
bus and data transmission protocol. The pin
assignment of DS1307 is given in Fig-6. The DS1307
operates as a slave on the 2- wire bus. Fig-7 shows
the interface connection of I2
C bus in Spartan 3E
with the DS1307 RTC chip.
Fig. 7: DS1307 connected to two wire data bus
V. SOFTWARE IMPLEMENTATION
I2
C master protocol is designed using VHDL
based on Finite State Machine (FSM). FSM is a
sequential circuit that uses a finite number of states to
keep track of its history of operations, and based on
history of operation and current input, determines the
next state. There are several states in obtaining the
result.
Algorithm
State 1: An idle condition: I2
C bus doesn’t
perform any operation. (SCL and SDA remains
high).
State 2: Start condition: master initiates data
transmission by providing START (SCL is high
and SDA is from high to low).
State 3: Slave address - write: master sends the
slave address-write (11010000) to the slave.
State 4: If the slave address matches with the
slave, it sends an acknowledgement bit in
response to the master.
State 5: 8 Bit Register Address[12] will be
transmitted to the slave. Again acknowledgement
is sent to the master by the slave.
State 6: Data to be transmitted is sent to the
slave by the master. After receiving the data,
slave acknowledges the master.
State 7: Stop condition: Slave sends a stop bit to
the master to terminate the communication (SCL
is high and SDA is from Low to high). For
performing read operation, write operation is
performed first and then read operation is done.
Slave address for read is 11010001. (State 7 will
not be performed for read operation)
State 8: Master transmits slave address for read
operation to the slave.
State 9: Master receives the data from the slave
and acknowledges the slave.
State 10: Master sends a STOP bit to terminate
the connection (SCL is high and SDA is from
Low to high).
Fig.8 shows the flowchart for I2
C master bus
communication with slave device. Fig-10 shows the
simulation result for DS1307. In DS1307, we have
activated only 4th order FIR filter for the given data
input and filter coefficients are applied and output is
observed. Generated square output is also observed
programmed in VHDL. Fig-11 shows the simulation
4. Regu Archana Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 10 ( Version 5), October 2014, pp.06-10
www.ijera.com 9 | P a g e
result for I2
C, a dataout, sda, read and write
operations are observed in the I2
C Master. To read
the written data from the slave, the write operation
takes place first followed by the repeated start
condition and sending the slave address read
(11010001) in each state of FSM.
Fig. 8: Flowchart for I2
C master bus communication
with slave device
VI. Results & Discussion
Here the I2
C bus protocol is designed using
VHDL and implemented in Spartan 3E using Xilinx
ISE Design Suite14.2. The simulation results are
shown below:
Fig. 9: Schematic Diagram of I2
C Master Bus
The below table shows the Xilinx Device
Utilization Summary. The result shows that minimal
resources are utilized in designing the I2
C master as
only 2% slices, 1% flip flops and 1% LUTs are
utilized.
Device Utilization Summary (estimated values)
In DS1307, we have activated only 4th order
FIR filter and chosen the below values pertaining to
the filter.
Input Signal: x0, x1, x2, x3 = '2';
Filter Coefficients: h0=1, h1=2, h2=4, h3=5.
Data Output (y) = x(0).h(3) + x(1).h(2) +
x(2).h(1) + x(3).h(0)
We obtained the output dataoutput(y) = 24 after
4 taps, square wave is generated at sqt_out.
Fig. 10: Simulation of DS1307
Fig. 11: Simulation of I2
C master
VII. CONCLUSION
The result shows that minimal resources are
utilized in Spartan 3E. The design process is
simplified using VHDL to design the I2
C bus
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www.ijera.com 10 | P a g e
protocol, I2
C Master (Master) transmits and receives
data to and from the DS1307 (Slave). So that any low
speed peripheral devices can be interfaced using I2
C
bus protocol as master. In future, this can be
implemented as real time clock in networks that
contains multiple masters and multiple slaves to
coordinate the entire system by clock synchronization
techniques.
REFERENCES
[1] I2
C Bus Specification, Philips
Semiconductor, version 2.1, January 2000.
[2] DS1307 64 x 8, Serial, I2
C Real Time
Clock, Maxim integrated, 2008.
[3] Prof. Jai Karan Singh et al “Design and
Implementation of I2
C master controller on
FPGA using VHDL,” IJET, Aug-Sep 2012.
[4] Raj Kamal, “Devices and Communication
Buses for Devices Network,” in Embedded
system: Architecture programming and
Design, Shalini Jha Ed. New Delhi, India:
Tata McGraw-Hill Education, 2008, pp.160-
165.
[5] Tim Wilmshurst, “Starting with Serial,” in
Designing Embedded
[6] Spartan-3A/3AN FPGA Starter Kit Board
User Guide, Xilinx, version 1.1, 2008.
[7] A.P.Godse, D.A.Godse, “Bus Standards,” in
Microprocessors and its Applications, 3rd
Ed. Pune, India: Technical publications,
2008.
[8] Systems with PIC Micro-controllers:
Principles and Applications, 2nd Ed.
Burlinton: Newnes, 2009, pp.307-327.
[9] Vincent Himpe, “Historical background of
I2
C,” in Mastering the I2
C Bus, Aachen,
Germany: Elektor Verlag publications,
2011.
[10] Pong P.Chu, “I/O Modules,” in FPGA
Prototyping by Verilog Examples: Xilinx
Spartan – 3 Version, New Delhi, India:
Wiley, 2008.