Girish Bharadwaj is seeking a position as a physical design engineer where he can contribute to growth while advancing. He has over 4 years of experience in physical design closure, verification, and low power techniques. His skills include placement and routing, timing analysis, custom layout, and scripting. He has worked on blocks up to 14.5mm^2 and completed tapeout of SoCs at TSMC 28nm. Girish holds an M.Tech in VLSI design and has published work in conferences.

1. Girish Bharadwaj. K
E-mail: gbkajala@gmail.com
Mobile: +91-9902324404
Seeking position as a physical design engineer in an organization that offers an opportunity for
advancement while contributing to the growth of organization.
Experience Summary:
 Total of 4 years of experience as Physical Design engineer with primary focus on Block
Physical Design closure and Block+SoC Physical verification.
 Associated with Freescale Semiconductor India Pvt. Ltd(NXP group of companies), Bangalore as
Sr. Design Engineer from Jan 7th
2013 till Date.
 Associated with Appsconnect Technology India Pvt. Ltd, Bangalore as Design Engineer from
September 3rd
2012 till Dec 31st
2012.
 Associated with Intel Mobile Communications, Bangalore as Intern from July 13 2011 to July
13 2012 during M.Tech course.
 In addition 1year of experience as lecturer in Dr. MVSIT, Moodbidri.
Skills & Abilities:
Synthesis Logic equivalence checking Block Conformal Low power
Block STA&SDC creation Placement&Routing ECO implementation
Calibre&PVS tiling Physical verification Full custom layout design
Basic TCL&AWK scripting Power Estimation IO ring Integration
 Hands on Experience in block RTL2GDS flow, block & fullchip backend activities, power estimation,
IO integration and C4 bump placement.
 Successfully completed physical design closure of 7 blocks and back end activities of SoC for
rev1.0, rev2.0.
 Able to work independently and as part of a team.
 Technically proficient with proven ability to deliver on time.
 Mentored one fresher in Physical Design domain.
Tool Expertise:
 Cadence - RTL Compiler/Genus, Conformal LEC&CLP, EDI/Innovus, QRC, ETS/Tempus,
Virtuoso Layout Suite, MVS(LPA, CMP).
 Synopsys – IC compiler, PrimeTime, Spyglass (CDC& power estimation).
 Mentor Graphics – Calibre (DRC/LVS/ANTDRC/XOR/PERC/Tiling), Questasim.
 Freescale – Daphne Viper
Academic Credentials:
 M.Tech in VLSI Design & Embedded Systems from SJCE, Mysore (affiliated to VTU, Belgaum)
in 2012 with aggregate of 77.6%.
 B.Tech in Electronics & Communication from Amrita School of Engineering, Bangalore in 2009
with CGPA of 7.02.
Award:
 Freescale peer to peer award for multibit flow and testing Innovus EDA tool features.
 Awarded Rating of 1 two times at Freescale.

2. Projects Executed:
Organization: Freescale Semiconductor India Pvt Ltd, Bangalore.
I. Block Physical Design Closure – 6 blocks for Rev1.0 SoC.
Technology Node: TSMC 28nm HPM & Samsung 28nm FDSOI
Role and Responsibility: Synthesis, LEC, CPF modification, CLP, SDC preparation, PnR, STA,
timing and functional ECO and PV closure at block level.
 Physical Design Closure of five blocks of different SoC with maximum size of block being
14.5mm2 (2Million instance count, 39macros). Clock frequency being 600MHz.
 Physical design closure of block level design at 28nm FDSOI technology node. Block size is
1.7mm2 (8lakh instance count, 31 macros), clock frequency of 600MHz.
II. Block Metal ECO Implementation
Technology Node: TSMC 28nm HPM.
Role and Responsibility: Implement functional and timing ECO using spare cells, LEC, physical
Verification closure.
 Metal ECO for 15lakh cell count design with 60Hard macros and 900MHz core frequency.
III. Block Physical Design Flow flush
Technology Node: TSMC 16nm FF+.
Role and Responsibility: Synthesis, LEC, PnR, exploring multibit flop option, DPT in 16nm FinFET.
 Physical Design flow flush on 1Million instance count design, clock frequency of 450MHz.
IV. Full Chip physical Verification and Tapeout (Rev1.0, Rev2.0)
Technology Node: TSMC 28nm HPM
Role and Responsibility: Block and SoC level tiling, Physical verification (DRC,LVS,ANTDRC,
PERC,XOR,LPA,CMP) at block and SoC level, final Tapeout.
 Chip Level and block level Physical Verification on hierarchical design, 28.4mm2 Die size, 6
blocks, 4 major macros, FCBGA package.
V. Custom layout design for SoC (Rev1.0)
Role and Responsibility: Prepare Custom OA cells for maskID, sealring, crack detect, Fiducial,
guard ring, block tiling exclude instance for top tiling, C4&IO template.
 Custom layout cells for SoC integration in Virtuoso and integrate to top design with
28.4mm2 Die area.
VI. IO Ring Integration, C4 Bump placement for SoC (Rev1.0)
Role and Responsibility: Integrate C4&IO template into top and core C4 bump placement.
Generate C4 map XLS, io ring RTL, DEF, BSDL, IBIS model.
 IO ring integration using Freescale Daphne tool for 28.4mm2 SoC, Bump pitch of 165u.
FCBGA package.
VII. Power Estimation
Technology Node: Samsung 28nm FDSOI
Role and Responsibility: Subsystem level hierarchical netlist based power estimation for different
power modes.

3.  Netlist based hierarchical power estimation using Spyglass for media subsystem with size15mm2
and 9 subblocks, maximum clock frequency is 800MHz.
VIII. Subsystem level hierarchical CDC
Role and Responsibility: Subsystem level hierarchical RTL CDC and abstract generation.
 RTL level CDC using spyglass for media subsystem with size15mm2 and 9 subblocks,
maximum clock frequency is 800MHz.
Organization: Intel Mobile Communications India Pvt Ltd, Bangalore.
I. Ring Oscillator - Full Custom Macro Design
Technology Node: TSMC 28nm HPM
Role and responsibility: Schematic design of frequency counter, standard cell ring structure. Pre-
layout simulation, hierarchical layout implementation, physical verification and gate level simulation.
 Full custom Ring osicallator design for a testchip in Virtuoso with size of each block being
100x200u. Total of 4 custom blocks.
II. Physical Implementation OF eFUSE block for Testchip
Technology Node: TSMC 28nm HPM
Roles and Responsibility: synthesis, place & route, LEC, static timing checks and physical
verification.
 Block level design, 600 registers, 1K combo cells. This was my M.Tech Thesis.
Publication:
 PHYSICAL IMPLEMENTATION OF AN eFUSE BLOCK FOR TESTCHIP in International
Conference on Science and Information Technology (ICSIT)-2012.
Personal Details:
Date of birth : 30th
May, 1988
Marital status : single
Nationality : Indian
Languages : English, Kannada, Tulu, Hindi, Malayalam & Tamil
Hobbies : Listening to music, gaming playing table tennis and cricket.
Permanent Address : S/o Ganesh Bhat P V, Kajala Farms, Post Ullodi, Bela Village,
Kasaragod Taluk and District, Kerala State-671321, India.
References :
Mr. Sahil Dabare
Senior Design Manager,
Freescale India Pvt Ltd, Noida.
E-mail: sahil.dabare@nxp.com