This document contains the resume of Sravya Vanganur. She completed her M.Tech in VLSI from National Institute of Technology, Calicut, Kerala in 2016 with a CGPA of 7.67. She has work experience as an intern at Intel technologies Pvt. Ltd. since June 2016 where she is responsible for physical design, timing closure, and reliability analysis. Her technical skills include synthesis, placement and routing flows, timing analysis, and familiarity with CAD tools like Synopsys. She has completed projects in ASIC implementation from RTL to GDSII, magnitude comparators, and reversible data hiding techniques. Her strengths are listed as individual learning skills, strong analytical ability, and being optimistic in nature

1. PAGE 1
Course College/University Percentage /
CGPA
Year of
Passing
M.Tech
(VLSI)
National Institute of Technology, Calicut, Kerala 7.67 2016
B.Tech
(ECE)
S V College of Engineering, Tirupathi, Andra Pradesh 83% 2014
HSC
(MPC)
Sri Chaitanya College of Engineering, Tirupathi, Andra Pradesh 92% 2010
SSC Kendriya Vidhyalaya No.1, Vadodara, Gujarat 77% 2008
Sravya Vanganur
Phone: +91 7795895815
E-mail: v.sravya16@gmail.com
Objective:
Seeking a position to utilize my skills and abilities in the organization, to wield as well as hone the IC design
skills that serves in bringing technology closer to human lives.
Summary:
 Working in Intel technologies Pvt. Ltd. as INTERN ( June,2016 to till date)
 Responsible to clean the Design w.r.t functionality equivalence, timing closure, reliability, antenna, IR
drop and EM violations.
 Good knowledge in Physical Design, IR & EM reliability analysis, STA, Timing Closure.
Technical Skills:
 Working on Synthesis, PnR flow- Floorplanning, Placement, Clock Tress Synthesis (CTS), Routing,
STA, IR & EM reliability analysis.
 Handling a partition of SoC, responsible for PnR Implementation and timing closure for 10nm
technology node.
 Good ability in writing TCL scripts with ICC DB commands
 Basic Knowledge in FEV and power intent verification (UPF checks).
 Familiar with different CAD tools like Synopsys DC, Synopsys ICC, Synopsys Primetime, Synopsys
Spyglass, ,and Apache Redhawk.
 Good VHDL coding skills, worked on Altera FPGA Kit.
Education:

2. PAGE 2
Project 1
(M.Tech)
Title: Block Level Structural Design Implementation for a Complex SoC at Evolving Technology
Nodes
Role: Intern in Intel technologies Pvt Ltd.
Abstract:
 Implementation of Physical Design, PnR flow in an efficient way to reduce the turn-around
time and converging design w.r.t timing, power at 10nm technology nodes.
 Resolved the timing closure and reliability issues in the design
Project 2
(M.Tech)
Title: ASIC implementation of Booth Multiplier from RTL to GDSII using Cadence SoC
Encounter
Abstract:
 Using Cadence SoC Encounter, Booth Multiplier circuit was synthesized and optimal layout
was obtained.
 Also Static Timing Analysis has been carried out to reduce Setup time and Hold time
violations.
Project 3
(M.Tech)
Title: One Bit Magnitude Comparator Using Different Logic Styles
Abstract:
 Using SYMICA DE, the comparator circuit for CMOS logic, Pass transistor Logic and
pseudo CMOS logic styles was implemented
 It was compared w.r.t power dissipation, switching activity and short circuit currents. In
every logic design, there is a tradeoff between one or more desired quantities
Project 4
(B.Tech)
Title: A Secure Transformation Of Data In Encrypted Image Using Reversible Data Hiding
Technique
Abstract:
 The aim is to implement a high capacity secure data in a chipper image using hiding
techniques through image compression methods to reduce image sizes and data transfer
Project Profile:
Strengths:
 Individual learning Skills, quick learner
 Strong analytical Ability Skills
 Optimistic in nature