I am working as Physical design engineer

1. GANESH MACHAVARAPU
Email: ganeshmachavarapu@gmail.com | Phone No: 94942804445 | Kundhanahalli, Bangalore, Karnataka.
Objective:
To enhance career development and gain professionalism within the VLSI industry by accepting and executing
challenging duties continuously by learning new skills, and utilizing my excellent knowledge and communication skills
towards organization goals.
Personal Overview:
 1.5Years of experience in VLSI Physical Design in latest technologies of 14nm, 28nm and 32mn
with multi-million gate design tape outs in Intel and Different clients of Sankalp semiconductor Pvt Ltd.
 Hands on Experience in Physical Design flow from Netlist to GDSII.
 Good understanding and knowledge on all aspects of backend ASIC design flow like Floor-
planning/Power-Planning, Timing Closure, Signal Integrity Analysis, Static IR Drop Analysis, Logical
Equivalence Check (LEC), and Physical Verification (DRC).
Experience Summary : - 1.5+ Years’ experience in Physical design domain
10 months experience in Sankalp semiconductor pvt Ltd as a Physical design engineer
(July2015 to present)
Project: ASIC Flow Development for the 14nm Designs
Technology: 14nm.
Tools: Innovus, Tempus, caliber.
Description: In this project my contribution towards team is to develop a RTL to GDS flow for block. In this flow I
have to create a flow for synthesis, PNR, STA and Layout verification according to customer requirement.
Client name: INTEL
Project: ASIC QA Flow Development for the 14nm Designs
Technology: 14nm.
Tools: Cadence and Synopsys
Description: In this project my contribution towards team is to develop a RTL to GDS flow for block. In this flow I
have to create a flow for synthesis, PNR, STA and Layout verification for both Cadence and Synopsys tools (like:
Synopsys: - ICC, DC, PT, StarRC and ICV
Cadence: - RC, Innovus, Encounter, Tempus, QRC and Caliber
According to customer requirement. Here I have done complete automation for this flow which will provide end to end
flow to the user along with reports to their corresponding mail. This is all carried by one GUI which created by different
scripting languages like:
GUI: python, Tcl tk, and html
Synopsys and Cadence tools flow: Tcl
UNIX environment: shell
Reporting XLS at each stage SYN, APR and LV: Perl
Client name: INTEL
Project: Block level implementation and Full chip Layout Verification
Technology: 32nm.
Tool used: IC compiler, caliber.
Description: In this project my contribution towards team is PNR flow for block and built the setup for full chip
layout verification. Here in PNR flow my role is to do floorplan, placement and CTS. After creation of setup for LV using
that flow to fix DRC violations using caliber. And I need to create Milk way cells using gds file.
Client name: AmpdRF

2. Project: Full chip Layout Verification
Technology: 14nm.
Tool used: IC compiler, caliber.
Description: In this project my contribution towards team is to fix DRC violations using caliber. And I need to create
Milk way cells using gds file.
Client name: Semtech
Project: 8 bit Microprocessor design (RTL to Netlist)
Technology: 45nm.
Tool used: Modalism, NC launch, RC compiler, Encounter.
Description: I have done this project in my training period. In this project I have done 8-bit microprocessor using
Verilog. After design I have verified with some test cases and performed synthesis for this. Now I am doing PnR
Flow for this project.
Client name: Sankalp
Internship at INTEL:-
9 Months’ experience in Physical design domain as graduate intern in INTEL Corporation
. (October 2014 to July 2015)
Project: Full chip Clock Tree Synthesis and Design Implementation
Objective: In this project my contribution towards team is to enable the new flow for full chip clock trees synthesis for
hierarchical design. Here I need to analyze the flow and I have to do few experiments on different stages in flow. After
these experiments I have to suggest for the flow which one is best. I have done automation scripts for ETM checks. Using
this flow I have done clock tree synthesis for the design.
Work Area: SOCs for Iot Applications
Technology summary: Work experience in both flat and hierarchical design
 Technology: 32nm, process node 1269 technology
 Die Size: 53 sq. nm,
 Hard macros: 7 partitions in full chip
 Gate count: 10 million
 Clocks: 235
 Frequency: 530 MHz
 Tool: IC compiler, Prime time analyzer
Technical Skills:-
 Programming Languages : Verilog, basics of C, Perl, Shell, Tcl, Tcl tk, Python and html.
 Tools : Modelsim, Quartus II
Cadence (Virtuoso, RTL compiler, NC Launch, SOC Encounter, Innovus, Tempus)
Synopsis (DC compiler, IC compiler, prime time analyzer, StarRC, ICV)
Mentor graphics (Caliber)
 Area of interest : Physical design (Synthesis, Place &Route, Floor plan at full chip level and block
Level implementation, Layout verification and DA methodologies)

3. Educational Qualifications:-
Course Board or University Name of the institution Year CGPA/%
M.Tech
(VLSI Design) VIT University VIT University 2013-2015 87%
B. Tech
(E.C.E)
J.N.T.U Kakinada
Avanti Institute Of
Engineering & Technology,
Visakhapatnam
2009-2013 81.92%
Intermediate
Board of Intermediate
Education (A.P)
Narayana Junior College,
Visakhapatnam
2007-2009 95.2%
S.S.C
Board of Secondary
School Education (A.P)
Z.P.H School,
Chanduluru,vizianagaram
2006-2007 88.6 %
Major Projects:-
 PG PROJECTS:-
 Reduction of Power Droop during Capture Phase in Logic BIST
Technology: 45nm
Tool used: Cadence (NC-sim, RTL compiler)
Description: This project presents a method to reduce the power droop during capture phase in scan based
Logic BIST. This is achieved by the generation of substitute test vector. By this method we can reduce switching
activity.

 ASIC Implementation of 64bit Reversible Comparator Tree
Technology: 45nm
Tool used: Cadence (NC-sim, RTL compiler, SOC Encounter)
Description: This project Designed a reversible comparator is compare in terms of delay, quantum cost
And number of garbage outputs. This binary tree can be possible with non-uniform sizing nodes with
Minimal overhead of Garbage outputs.
 Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
Technology: 180nm
Tool used: Cadence, Virtuoso tool
Description: In this project, we have described the analysis on the delay of the dynamic comparator and a
New dynamic comparator is proposed, where the circuit of a conventional double tail comparator is modified for
Low-power and fast operation even in small supply voltages.
 Design of Low Power Tunable Trans conductance (Gm) Circuit:
Technology: 45nm
Tool used: Cadence, Virtuoso tool
Description: In this project we have described low power tunable Trans conductance circuit is presented.
In order to achieve low power, this Trans conductance circuit is designed in subthreshold region.
This circuit simulation Results are carried out on cadence virtuoso tool in 45nm CMOS technology and
Achieved a tuning Range of 1μS to 9μS Trans conductance with a low power consumption of 0.8μW.

4. Achievements:-
 Got district 1
st
prize in elocution competitions during my schooling, held at Sri Maharaja College of engineering,
vizianagaram.
 Got 1
st
prize in “Paper Presentations “event during VIDYOTHA 2K12 held at Prajna institute of technology and
management, Srikakulam, Andhra Pradesh.
 Participated as a leader in “youth for rural development” during NSS CAMP held by JNTU Kakinada
University
 Awarded Gold medal during my b.tech in academics from JNTU Kakinada University.
Personal Details:-
Father’s name : M.Eswara Rao
Sex : Male
Date of Birth : 5
th
Aug 1992
Nationality : Indian
Languages known : English, Telugu
Hobbies : Listening Music, Playing volleyball and shuttle.
Permanent Address : Door no: 5-42, chanduluru (village), Lakkavarapu Kota (Mandal), vizianagaram
(District), Andhra pradesh-535161.
Declaration:-
I hereby declare that the above mentioned information is correct up to my knowledge and I bear the responsibility for the
correctness of the above mentioned particulars.
Place: Bangalore yours sincerely,
(Ganesh)