1. Gaurang Prabhakar Narvekar
Email: gnarvekar3@gatech.edu Phone: +1-404-374-4199
Current address: 1068 Appt C Westshire PL, NW, Atlanta, GA. 30318.
Objective: Seeking Co-op/Intern position with leadership responsibilities including problem solving, planning &
organizing in the field of Digital/Analog/RF Circuit designs, Hardware/PCB design, IC fabrication & packaging,
software programming & development; commencing from Jan, 2011 or full time positions commencing from May,
2011.
Education:
Georgia Institute of Technology 2010–2011 (anticipated)
MS: Electrical and Computer Engineering
Mumbai University, V.E.S Institute of Technology 2004-2008
B.E: Electronics Engineering
Achievements:
Secured 2nd prize at the national level in the Chip design contest organized by Cadence, India for the
project: Design of Low-power DPA resistant AES crypto engine.
Secured prizes in inter-collegiate competitions for Robotics.
Relevant Courses:
Digital MOS Integrated Circuits Analog Integrated Circuits
Micro-Electro Mechanical Devices Wireless IC design
IC Fabrication Physical Design Automation
Advanced VLSI Micro Electronics System Packaging
Graduate Projects/Research at GeorgiaTech:
Analysis and design of Decision Feedback Equalizer (DFE) architectures for high speed wireless applications
(Ongoing research project).
Advisor: Prof. Kevin Kornegay
The implemented DFE architecture will have maximum bandwidth along with minimum filter taps which will
thereby reduce the circuit implementation cost.
Design of SRAM memory block for 1.2v power supply, 1Ghz operating frequency in 45 nm Technology using
Cadence design tools: ongoing course project under Prof. Saibal Mukhopadhyay.
Design and implementation Wireless transmitter and receiver modules (including Power amplifier, Low noise
amplifier, Mixer, Phase shift blocks: ongoing course project under Prof. Kevin Kornegay
IC fabrication of MOS devices, ring oscillator and CMOS logics: course-project under Prof. A.B.Frazier.
The fabrication process followed 6 mask photolithography steps and the fabricated devices on the wafer were tested
for their functionality in the testing phase.
7-Transistor Op-amp design with negative feedback: course project under Prof. G.A. Rincon Mora.
Designed and implemented a 7 transistor op-amp transimpedance amplifier with negative feedback. The designed
circuit was simulated in spice for validating the analytical model.
Optimization of routing and floor-planning in VLSI designs.
Advisor: Prof. Sung Kyu Lim.
A flattened verilog netlist was broken down into partitions by means of perl scripting procedure. These partiti ons
were then floor-planned in 2-D and 3D design environment.
2. 64x64 6T SRAM memory using 1.2um CMOS technology (Vdd = 5v): course-project under Prof. Kevin Kornegay.
The design achieved a worst case read access time of 40nsec with minimum power consumption in standby.
Vascular shear stress sensor: course-project under Prof. Oliver Brand.
MEMS endovascular shear stress sensor was designed which measured shear stress indirectly by using near wall fluid
velocity at the wall. It was implemented using principle of a hot wire anemometer.
Undergraduate Projects at V.E.S Institute of Technology, Mumbai:
Design of Low-power DPA resistant AES crypto engine.
Advisor: Prof. D.R. Pagay
This design is useful in embedded systems such as smart cards, wireless sensor networks etc.
The design was SOC compatible having wishbone signal structures.
The designed chip attained the high standards of low power characteristics and a peak throughput rate of 556Mbps.
Undergraduate thesis: Design and implementation of smart-home devices
Advisor: Prof. Naveeta Kant
Final year undergraduate thesis on Smart-Home devices implemented with a budget of $75.
This masterpiece offered home surveillance system, fire alarms, code-locks, water-tap switches and other ancillary
features at an extremely competitive cost.
The sensor networks were interfaced to AT8535 microcontroller, and there were readouts/alarms to indicate the
sensing activity.
Other Projects:
Implemented Algorithms in Numerical Techniques in C/C++
Implemented partitioning and floor-planning project on Verilog netlist using Perl script.
Perl scripts for extracting/formatting data in verilog netlists.
Work Experience:
Accenture Services Private Ltd. July, 2008 to Oct, 2009
Associate Software Engineer.
Led and implemented release of three project modules: eCI, SDP and ISAACS.
Project involved implementation of Extraction, Transform and Load (ETL) processes on data in accordance to
client’s needs.
This involved implementing data-mining operations on client data using BI-tool Informatica and then scheduling jobs
to move data on a daily basis by means of Unix scripting procedures. The client data was located on multiple
databases ranging from Oracle to Teradata.
Accenture certified professional for:
Data Warehousing-Business Intelligence and Informatica {Beginner and Intermediate level}
Datastage & Cognos {Beginner and Intermediate level} Level 1 vendor Certified for Informatica.
Part-time teaching Experience at V.E.S Institute of Technology, Mumbai, India: Jan, 2009 to March 2009
VLSI course covering topics: Usage of Cadence tools like SOC Encounter, RTL compiler and ISE Xilinx.
Implementation of Verilog programming.
Skills:
Cadence Chip Design tools: RTL compiler, SOC Encounter, Virtuoso, Spice.
Xilinx ISE, Comsol, Suprem tool for fabrication, ADS tool.
Verilog HDL programming. C, C++, UNIX, Perl/TCL scripting.
ETL tools: Datastage, Informatica, Cognos, SQL server 2005, Oracle databases, Microsoft Office.
Extra-curricular activities:
Represented Hindu gymkhana: In Intra-city Cricket tournament.
Represented V.E.S. Institute of Technology, Mumbai: In intra-college badminton, chess and debates competitions.
