- Currently working as a Design & Verification Engineer with over 2 years of experience in VLSI design and verification. Experienced in debugging and simulation using tools like Xilinx ISE, Vivado, and Mentor Graphics QuestaSim. - Has worked on several projects involving memory controller verification, Ethernet packet verification, 1553 data bus development, micro SD card controller design, and multiboot design. Responsibilities included test plan development, testbench coding, and functional verification. - Seeks to leverage expertise in SystemVerilog, Verilog, UVM basics, and tools like Vivado, ISE, and QuestaSim for further career advancement.

1. GUTTIKONDA BHARGAV
E-mail ID: bhargav.ramudu@gmail.com Mobile No: +91-9849987907
SUMMARY:
• Currently working as Design & Verification Engineer In OptimusLogic Pvt Ltd.
• 2+ years of experience in VLSI Design & Verification.
• Expert in debugging and Simulation Issues.
• Good Exposure to Simulation with Xilinx ISE, Vivado & Mentor Graphics QuestaSim.
• Excellent communication, debugging skills and a strong team player.
Technical Skills System Verilog, Verilog, UVM basics.
HDL Tools Xilinx Vivado, ISE, Chipscope Pro, Mentor Graphics QuestaSim
10.b, Lattice diamond, Aldec Active HDL.
Editors Vim.
Operation Systems Linux.
PROFESSIONAL EXPERIENCE & PROJECTS:
Company: OptimusLogic Pvt Ltd, Bangalore
Position: Verification Engineer Duration: Presently Working
Project1: Memory controller functional verification using System Verilog
Description: Design supports SDRAM, SSRAM, Flash & Synchronous Chip select devices. It
has support for 8 chip selects. It also supports flexible timing configuration for different memory
types. As part of this design verification, we created test bench using SV to generate scenarios
targeting all types of supported memories for different possible combinations & different sizes
supported. We also developed monitor, reference model & checker as part self-checking test
bench implementation.
Responsibility:
• Listing down features, scenarios.
• Test plan development.
• Developing test bench architecture.
• Coding test bench components including reference models and checkers.
Language used: System Verilog, Verilog.
Tools Used: Mentor Graphics QuestaSim 10.b.

2. Company: OptimusLogic Pvt Ltd, Bangalore
Position: Verification Engineer Duration: 3 months.
Project2: Ethernet Packet frame format verification using System Verilog.
Description: Design checks the incoming Ethernet packets at the receive interface for CRC, sof
errors, data len errors, etc. Packet is looped back on Transmit interface if it is good, else dropped.
As part of this design verification we developed testbench with generate all types of Ethernet
packets and also developed reference model for the self-checking the design behavior.
Responsibility:
• Listing down features, scenarios.
• Test plan development.
• Developing test bench architecture.
• Coding test bench components including reference models and checkers.
• Verification closure using Functional coverage & Code coverage as closing criteria.
Language used: System Verilog, Verilog.
Tools Used: QuestaSim 10.b.
Company: OptimusLogic Pvt Ltd, Bangalore
Position: Verification Engineer Duration: 5 months
Project3: 1553 multiplex data bus system development and verification.
Description: It was design for avionics data bus, commonly used in spacecraft on-board data
handling subsystems. It consists of Bus Controller (BC) controlling multiple Remote Terminal
(RT) all are connected together by a data bus providing a single data path between BC and all
associated RT, there also be a Bus Monitor (BM) its only used to capture or record data for
analysis. It does redundant bus implementation.
Responsibility:
• Understand the spec and develop each functionality.
• Simulation using Xilinx Vivado.
• Developing bus functional models of BC, RT.
• Making a successful data transfer from the BC to RT
Language used: Verilog, SystemVerilog.
Tools Used: Xilinx Vivado.
Company: OptimusLogic Pvt Ltd, Bangalore.
Position: Verification Engineer Duration: 6 months
Project4: Micro SD Card Controller and digital IO in SoC through SDIO.
Description: On a custom board lattice ECP3 developing micro sd card controller using
SDIO(secure digital input/output) and host side it is connected to the Wishbone bus. Digital IO is
also connected to the wishbone bus. This controller is used to get the micro sd card bring it up to
do writes and reads from the micro sd card support 2 gb to 32 gb (tested) theoretical up to 2tb,
able to get the file system up on it.
Responsibility:
• Debugging the controller in simulation using Active Hdl.
• Probing the signals in the hardware to get work with the software.
• Used lattice diamond for debugging and validating on lattice ECP3 custom board.
Language used: VHDL, Verilog.
Tools Used: Xilinx Lattice Diamond, Active HDL.

3. Company: OptimusLogic Pvt Ltd, Bangalore.
Position: Verification Engineer Duration: 3 month
Project5: Multiboot design and ADC and DAC IC configuration through SPI.
Description: Multiboot design purpose is to switch the different bit files dynamically on the
board without reprogramming it. Configuring the IC register with the required values in order to
make the analog to digital converter and digital to analog ic to work as per requirement. Client
requires different data rate bit files need to be loaded on the device dynamically on the field
without re-programming on custom board Xilinx Artix7.
Responsibility:
• Load the mcs file to flash memory and to boot the bit file.
• Design the top level Verilog code for multiboot for Artix7.
• Debugging it on board and testing it for multiple number of bit files.
• Validating the adc and dac on board through loopback, CRO.
Language used: VHDL, Verilog.
Tools Used: Xilinx ISE, Vivado.
EDUCATION:
• M.S in VLSI Design & Embedded System from “JNTU Hyderabad”, in 2014 with 71.1%.
• Bachelor of Engineering in Electronics and communication Engineering from “Samskruti
college of Engineering and Technology”, JNTU in 2012 with 61.8%.
• 12th, from “G Pulla Reddy junior College”, Hyderabad in 2008 with 70%
• 10th from“St. Augustine High School”, Hyderabad in 2006 with 60%
Professional Training:
Undergoing UVM training at VLSI GURU, Bangalore.
Completed VLSI Design & Verification training at Lucid VLSI, Hyderabad.
Topics Covered:
• Synthesizable RTL Code using Verilog.
• Design flow and validation in FPGA.
Projects:
• Design and Verification of Reconfigurable Router for NoC applications.
Personal Details:
Data of Birth : 15th Aug 1991
Father’s Name : G V Joga Rao
Languages Known : English, Telugu, Hindi.
Strengths : Good Debugging skills, Good Learner
alternate email : bhargav.ramudu@engineer.com
Declaration:
I hereby declare that the information furnished above is true to the best of my knowledge.
Place: Bangalore G. Bhargav