Gayathri R is seeking a challenging career to enhance her knowledge and skills. She has over 3 years of experience as a Physical Design Engineer at Intel India, where she has worked on block implementation from synthesis to routing for the 14nm process, and handled timing closure and layout verification. Previously she interned at Intel where she performed block implementation from 22nm to 14nm, extracting ILMs. She has an MTech in VLSI Design from VIT University and a BTech in ECE from Anna University. Her technical skills include Verilog, C, Synopsys tools, and Cadence tools. She has done academic projects in clock tree synthesis, RF stability simulation, FPGA implementation, and Vedic multiplier implementation

1. GAYATHRI R
Email: gayavijay9@gmail.com Physical Design Engineer,
Mobile: 91-8508663660 INTEL India Pvt Ltd
Bangalore
Career Objective: To pursue a challenging career and be part of a progressive organization that
gives scope to enhance my knowledge, skills with sheer determination, dedication and hard work.
Work Experience
Graphics Hardware Engineer, INTEL INDIA, Bangalore (Nov 2015–Present)
Tool Used Synopsys ICC, Design Compiler, PrimeTime
Responsibilities
 Block implementation (Synthesis till Routing) for Intel Foundry 14nm process 
 Timing Closure of blocks in PrimeTime 
 Involved in Layout Verification team for tapping out two blocks (Handled
Manual routing for DRC, LVS fixes and Antenna violations). 

Intern, INTEL INDIA, Bangalore (Nov 2014 – June 2015)
Project Title: Timing and Area analysis on scaling down technology node from 22nm to
14nm
Tools Used: Synopsys ICC compiler
Project Description:
 Block Level implementation (APR complete Flow) in 22nm technology
node for three different blocks of different levels of complexity.
 Scaling down the same blocks to 14nm by scaling the Macros size, Core
size, pin size to a ratio for the best timing results and congestion free
design.
 ILMs are extracted for all the three blocks in 22nm and 14nm for the
hierarchical level implementation.
Program Analyst in Cognizant (1.5 years)
Academic Projects
 Chip Level Clock Tree Synthesis

Technology Used: Matlab, NGSPICE, Linux

Project Description: Exact Zero Skew Algorithm is implemented in a Chip Level
scale with 10 IP cores and the skew is calculated to ensure the reliability of the
Algorithm developed. Latency at all the IP cores is also calculated using HSPICE

2. tool and found to be small
 RF Stability Performance of SiGe Double Gate TunnelFET

Technology Used: TCAD

Project Description: Basic MOSFET is simulated with SiGe as the Source
material and the RF stability performance is studied using TCAD. Two different
high k - dielectric material is used for the simulation.
 Snake Game Implementation using FPGA

Technology Used: SOPC builder, ALTERA DE-2-115

Project Description: Classic Snake game is Implemented using SOPC builder
in Quartus.
 ASIC Implementation of Multiplier using Indian Vedic Mathematics

Technology Used: Verilog, Model-Sim, Cadence-Encounter

Project Description: 8-bit multiplier using the Urdhva triyambaka Sutra
where number of multiplication term is reduced is implemented in Cadence
Encounter, Floorplanning, and Routing is done
Academic Profile:
GATE – 2013 Qualified
Examination Passed University /Board Year % Marks Obtained
Mtech ( VLSI Design) VIT University 2015 8.97 (CGPA)
B.E ( ECE) Anna University 2010 84
12th State Board 2006 89.4
TamilNadu
Technical Skills
Programming languages: C, Verilog HDL, Matlab
Scripting: Perl, TCL
Operating System: Windows, Linux
Tools:
Synopsys Design Compiler, PrimeTime, ICC ,
ModelSim, Cadence Virtuso, Encounter,Quartus
Field of interest:
Physical Design (APR), STA, Scripting
.
Declaration: I hereby declare that all the details furnished above are true to the best of my
knowledge and belief
GAYATHRI R