1. RESUME
Anuradha.M Senior Specialist
e-mail : anuradham2015@gmail.com Mobile: 8861987631 , 080- 25605501
Career Objective : Place and Route (PD) Engineer
Educational Background : Cadence Certified PG Diplomo in VLSI – Physical Design, ITRI(Industrial Training and
Research Institute) Bangalore
Batch : Feb 2016 – April 2016 ;
Completed :BE-ECE
Technical Skill Summary :
EDATools : Cadence SOC Encounter (90nm),Cadence – RTL compiler.
Vinyas Gate Array Tool 3 micron ,Solo ES2 ,Cadence Design Systems 1 micron (Cell Ensemble).
Technology : 90nm
Scripting Languages : Shell Scripting ,Perl,TCL
Software Languages : C, C++
Core Competency:
Good Knowledge of RTL to GDSii flow.
Hands on experience with Cadence SOC Encounter 90nm.
Hands on experience with Synthesis (RTL Complier),STA,DFT,,Place and Route .
Knowledge of 45nm technology.
Projects Handled:
Project 1 : DTMF Core
Physical Design implementation of DTMF Core in Cadence SOC Encounter
DTMF Core is Dual Tone Multi Frequency Receiver.In telephone network DTMF is a common in band signaling
technique used in transmitting information between network entities.DTMF signals are commonly generated by touch tone
telephones.
Description: Design includes 4 blocks including Macros and Standard Cells..The clock frequency is 400mHz.Complexity
of the design is 50K Gates.
The Design goes through all phases of Flooplanning ,Power Planning, Placement,CTS,Optimization,Routing,Parasitic
Extraction,Physical Verification.
Writing Scripting(Tcl) File for P&R flow.
Physical Design is done with Cadence SOC Encounter in 90nm.
Problems Faced:
Problem 1: Macros Placed to the Corners and Std Cell as a cluster
Reports Wire Length and Congestion H&V .
Problem 2: Macros overlapping each other.
Reports- Use default delay limit to 101.
This may result in high fanout nets.
Problem 3: Reducing width and spacing Power Rings
Reports: Power Planner did not generate vertical stripes since stripes merge with rings.
Problem 4. Route (NanoRoute)
Reports:Pin does not have a physical Port.
Power Planner detected wires close to Std cell area.
Pitch- 1.00..for layer Metal 5 – Will cause routing problem for Nanoroute.
Check for the height and metal thickness value for Routability layers in Metal1
DRC Violations.
Problem 5: Detailed Routing
Reports: Stopped b’cos of to many violations.
Problem 6: No VDD VSS Rings, Vertical,Horizontal Stripes.
Report : Warnings like track is smaller than pitch,Routing issues.

2. DRC Viloations.
Problem 7: When design is not placed ie Empty FloorPlan
Reports: After timing Analysis .
Error:.Design is not yet place
Project 2:
Synthesis implemented using Cadence RTL - Compiler
Project : RISC Processor .
Description: RISC is a control Logic of a RISC processor.This is a small RISC core design.
The design is taken from Sourcing the Verilog file to Generating a Gate Level Netlist.
Synthesised RISC with the tcl script file with all the constraints from the input specification.
The design is synthesized for Low Power . Generated Reports on Timing, Area and Power.
Reports: Checking for Wireload Model, Total Area of RISC design,Timing slack on the critical Path
in top module and subblocks..
Project : Low Power Syntheis - RISC Processor.
The design is synthesized for Low Power with the Timing constraints in the tcl file with low power constraints.
A comparision done with the Normal synthesis and Low Power Synthesis.
Report : generatated .
Area Power Timing slack
Normal Synthesis 682 85625.3 1ps
Low power Synthesis 840 38723.2 0ps
Project 3:
Synthesis of DTMF core .
Description: DTMF Core is Dual Tone Multi Frequency Receiver.
The design is taken from Sourcing the Verilog file to Generating a Gate Level Netlist.
Synthesised RISC with the tcl script file with all the constraints from the input specification.
The design is synthesized for Low Power . Generated Reports on Timing, Area and Power.
Reports: Checking for Wireload Model, Total Area of RISC design,Timing slack on the critical Path
in top module and subblocks.
Low Power Synthesis:
The design is synthesized for Low Power with the Timing constraints in the tcl file with low power constraints.
A comparision done with the Normal synthesis and Low Power Synthesis.
Project 4:
DFT Analysis of ROM BIST .
Description:ROM – Read only Memory .
It consists of 4 Blocks. LFSR ,MISR,ROM- input, Compare .Depending on the random
generation of 8 bit address in LFSR, data is fetched from ROM- input. Compared with the signature bit
in MISR and generates a output.Results are viewed in SimVision waveform.
Title : ASIC METHODOLOGY DESIGN
Organization: Tata Elxsi Ltd ,Bangalore
Contribution : Handled RTL-GDSII
flow releases for individual technologies in TSMC .
Flow : TI Pyramid Flow. PrimeTime,Magma,Synopsys .
Organization :Tata Elxsi Client : TexasInstruments –India
Project Leader ; Period :July2001-2003
Title : Layout Design
Description:
Team consists of 15 members. Interaction with TI and team members ,Project
discussion,Project allocation ,Recruitment ,Training in VLSI .
Problems Faced :
All Phases of Project from Member Selection to
discussion,Project allocation ,Recruitment ,Training in VLSI .

3. Contribution : Involved in Layout Design and heading the team
Organization :Tata Elxsi Client : TexasInstruments –India
Senior Specialist : Period :DEC 2000 to July2001
Title :Physical Design
Organization II - INDIAN TELEPHONE INDUSTRIES Ltd ,Bangalore
Team Leader ; Period : 1991-2000 ; Client : Defence Organization
Description : Handled projects from simulation to Mask Preparation for fabrication. for Defence customers.
EDA Tool : Cadence Tool for 1 Micron Standard Cell Designs –Cell Ensemble
Contribution: As a Team Member, was responsible for the following activities:
* Involved in verification using ES2 FAST simulation.
* Generation of Estimated SDF delay Files.
* Synthesis & simulations of the Verilog modules
* Floor Planning using Cell Ensemble.
* Placement and Routing using Cell Ensemble.
* Extraction of Parasitics with and without SDF delays.
* Simulation with Back annotated Delays.
Project 1: Timetag
Application :Satellite Control Circuits
It is used in control circuits of satellite for the payload at specified intrevals.Maximun of 255 commands can be tagged
.Time delay of 0 to 72 hours.On chip command and Delay memory,onchip error correction and detection.
Duration: Three months
Frequency of operation: 1 MHz
Gate Complexity : 35,000 gates
Packaging : 68L pin PGA
Foundry : One micron FAB at ITI Ltd., Bangalore, India.
Hardware operating system : Unix
Project 2:
Skill Programming for Automatic Placement of Layout for Mask shop.
Contribution :
As a Team Member, was responsible for the following activities:
* Involved in writing code in skill Language for Automatic Placement of Layout for
Mask shop.
* Involved in writing code in SKILL Language for Automatic Placement of CD's
(Critical Dimension) for Mask shop.
Project 2A: Diva Command File
Contribution :
As a Team Member, was responsible for the following activities:
* Involved in writing Diva code for biasing of 10 layers for 1micron Technology
Process.
* Sizing done using DIVA command file and generated STREAM IN/OUT.
Verification done in Virtuoso Layout Editor.
Duration : Three months.
Technology : 1 micron Standard Cell design
EDA tool : Cadence (Full suit of Cadence tools)
Foundry : One micron FAB at ITI Ltd., Bangalore, India.
Customer : ITI Limited
Language : Skill language
Project 3: SRAM 1kx4
Duration: Three months.

4. Frequency of operation: 5 MHz
Gate Complexity : 15 gates
Technology : 1 micron Standard Cell design
Packaging : 18L pin BCE
EDA tool used : Cadence(Full suit of Cadence tools)
Foundry : One micron FAB at ITI Ltd., Bangalore, India.
Operating Frequency : 5 Mhz
Contribution :
As a Team Member, was responsible for the following activities:
* Involved in Floor planning, Placement and Routing
* Extraction of Parasitics with Estimated Delays and back annotated delays.
* Simulation with Back annotated delays
* Generating Composite Field Layout for Mask shop.
* Tape Out in GDSII format.
Project 4: SRAM 2kx 8
Duration : one month.
Access time : 15ns
Gate Complexity : 440 gates
Technology : 1 micron Standard Cell design
Packaging : BCE 24S
EDA tool used : Cadence – Cell Ensemble
Foundry : One micron FAB at ITI Ltd., Bangalore, India.
Operating frequency : 5Mhz
As a Team Member, was responsible for the following activities:
* Involved in Physical Design, Place and Route, Parasitic Extraction.
* Synthesis & simulations with and without SDF delays.
* Generating Composite Field Layout for Mask shop.
* Tape Out in GDSII format.
Project 5: CAM (Comparator Associative Multiplier)
It is used to compare 16bit input data to all the stored data.
It consists of 4 blocks.
Contribution:
As a Team Member, was responsible for the following activities:
* Involved in Physical Design,Floor Planning,Place and Route,Diva parasitic
Extraction,DRC and LVS,Simulation with Back Annotated Delays.
* Generating Composite Field Layout for Mask shop.
Duration : one month.
Frequency of operation: 10 MHz
Gate Complexity : 6,127 gates
Technology : 1 micron Standard Cell Design
Packaging : BGA 120L
EDA tool : CADENCE- Cell Ensemble
* Tape Out in GDSII format.
Project 6: CMUL (Complex Multiplier)
Application : It is 16x16 bit multiplier used in data processing.
Contribution:
* Involved in Physical Design,Floor Planning,Place and Route,Diva parasitic
Extraction,DRC and LVS,Simulation with Back Annotated Delays.
* Generating Composite Field Layout for Mask shop.
* Tape Out in GDSII format.
Duration : one month.
Frequency of operation: 20MHz

5. Gate Complexity : 7533
Technology : 1 micron Standard Cell Design
Packaging : PGA 144s
Project 7: DFDC
Application: This chip is used in Telecommunication Equipments.
Contribution:
* Involved in Physical Design,Floor Planning,Place and Route,Diva parasitic
Extraction,DRC and LVS,Simulation with Back Annotated Delays.
* Generating Composite Field Layout for Mask shop.
* Tape Out in GDSII format.
Duration : one month.
Frequency of operation: 10 MHz
Gate Complexity : 2k
Technology : 1 micron Standard Cell Design
Packaging : DIP 14
EDA tool used: Cadence – cell Ensemble
Title : Design and development of ASICS for 3micron Gate Array Designs.
Hardware operating system : Unix
EDA Tools : Vinyas Gate Array Tool for 3 Micron
Company : ITI Ltd ,Bangalore
My role : Design and Development of Asics for 3 Micron Gate Array Designs.
Project 8: codec
Application: It is an encoder Decoder in the same chip .Used for telecommunication equipments.
Contribution:
Involved in Schematic Entry,Simulation,Verification,Gate Array Place and Route.
Duration : six month.
Frequency of operation: 3mhz
Gate Complexity : 2800 gates
Technology : 3 Micron Gate array Design
Packaging : PGA 64
EDA tool used : VINYAS(Full suit of Vinyas tools)
Project 9:
ALU (8 bit Arithmetic and Logic Unit)
Contribution:
*Involved in Design, Implememtation,Simulation,Verification
Duration : six month.
Frequency of operation: 3mhz
Gate Complexity : 600gates
Technology : 3 Micron Gate array Design
EDA tool used : VINYAS(Full suit of Vinyas tools)

6. Personal Details :
Anuradha M : DOB : 22-03-1966
Martial Status : Married
Education Qualification:
SSLC : Alvernia Matriculation Higher Secondary School, Coimbatore
Hr Secondary : RKM Sarada Vidayalaya ,Chennai
Bachelor of Engineering : Electronics and Communication Engineering
Government College of Technology – Coimbatore
Percentage of Marks : 69.7%
Year of Completion : 1989
Years of Experience : 12yrs
Working Experience : 1991 – 2003
Address For Communication:
No :35, 6 th cross Munnireddy Layout
PWD Main Road .Opp to Nirmal Jyothi Apartment
B Narayanapura ,Bangalore :16
Mobile : 8861987631
Declaration:
I hereby declare that all the details furnished above are true to the best of my knowledge and belief.
Anuradha m

7. Personal Details :
Anuradha M : DOB : 22-03-1966
Martial Status : Married
Education Qualification:
SSLC : Alvernia Matriculation Higher Secondary School, Coimbatore
Hr Secondary : RKM Sarada Vidayalaya ,Chennai
Bachelor of Engineering : Electronics and Communication Engineering
Government College of Technology – Coimbatore
Percentage of Marks : 69.7%
Year of Completion : 1989
Years of Experience : 12yrs
Working Experience : 1991 – 2003
Address For Communication:
No :35, 6 th cross Munnireddy Layout
PWD Main Road .Opp to Nirmal Jyothi Apartment
B Narayanapura ,Bangalore :16
Mobile : 8861987631
Declaration:
I hereby declare that all the details furnished above are true to the best of my knowledge and belief.
Anuradha m