This document contains the resume of Venkataapparao. It summarizes his professional experience in physical design including floorplanning, placement and routing. It lists his technical skills in EDA tools like Encounter, Innovus, and languages like Verilog and VHDL. It also provides details of his educational qualifications and projects undertaken in physical design across different technology nodes from 45nm to 65nm.
Smit Patel is seeking a position in analog and mixed signal layout design. He has experience in standard cell layout design, analog layout design, and memory layout design from internships. His projects include layout of a 32x32 bit SRAM cell in 28nm technology and design of a two stage op-amp in 180nm technology. He is familiar with tools like IC Studio, Pyxis, Calibre, Virtuoso and Eldo.
Deepak Anand Ravindran is seeking a full-time position in digital ASIC RTL design or verification. He has a Master's degree in Electrical Engineering from USC and a Bachelor's degree from NIT Trichy. He has work experience in memory circuit design at Dolphin Technology, chip validation and failure analysis at Broadcom, and digital and power embedded systems design at CDOT Alcatel-Lucent Research Center. His technical skills include Verilog, C, Perl, and digital design tools from Synopsys and Cadence. He has completed academic projects in memory controller design, ATPG, processor performance simulation, and network processor design.
This document discusses Toshiba's 65nm (TC320) family of ultra-high density and ultra-low power system-on-chip (SoC) and system-in-package (SiP) solutions. The 65nm process technology offers unprecedented integration levels and power savings. It allows easy mixing of analog and digital cores on a single chip. The TC320 family is well-suited for applications such as mobile phones and portable media players that require high integration and low power consumption.
The signal processing algorithms can be implemented on hardware using various strategies such as DSP processors and ASIC. This PPT compares and contrasts the two methods.
Sonia Sharma has worked as a physical design engineer and staff engineer at STMicroelectronics since 2006 specializing in SoC top level design, block implementation, analog and digital integration, ESD closure, and library development from 90nm to 28nm process nodes. Her responsibilities included place and route, timing analysis, physical verification, I/O ring creation, and characterization of standard cell libraries.
ASIC DESIGN OF MINI-STEREO DIGITAL AUDIO PROCESSOR UNDER SMIC 180NM TECHNOLOGYIlango Jeyasubramanian
- Designed and analyzed a complete MSDAP with optimized convolution computation by only shifts and adds using power-of-2 coefficients. Synthesized the chip through high level architecture design (C Program), Logic synthesis (Synopsys Design Compiler) and Physical Synthesis (Synopsys IC compiler).
- Achieved a low power consumption of 3.1438mW at 29.186Mhz clock frequency, with core utilization of 70% and chip area of 1.29mm2.
Nathaniel Weathers is a motivated field operations personnel with over 20 years of experience in network engineering and operations. He has extensive experience testing, installing, and troubleshooting fiber optic and copper networks including experience with test equipment from EXFO, JDSU, Fluke, and Acterna. He is proficient in Microsoft Office, network monitoring software, and various carrier systems. His most recent role is as a Datacenter Tech III at TELX LLC where he performs remote hands services and oversees infrastructure installations and maintenance.
This document is a resume for Jaydip Patel seeking an internship or entry-level position in VLSI design and validation. It summarizes his education, including an M.S. in Electrical and Electronics Engineering from California State University, Sacramento and a B.S. in Electronics and Communication Engineering from Gujarat University, India. It also lists relevant coursework, professional experience including internships, tools and software skills, and projects in analog and mixed signal design, logic design, computer architecture, and VLSI validation and testing.
Smit Patel is seeking a position in analog and mixed signal layout design. He has experience in standard cell layout design, analog layout design, and memory layout design from internships. His projects include layout of a 32x32 bit SRAM cell in 28nm technology and design of a two stage op-amp in 180nm technology. He is familiar with tools like IC Studio, Pyxis, Calibre, Virtuoso and Eldo.
Deepak Anand Ravindran is seeking a full-time position in digital ASIC RTL design or verification. He has a Master's degree in Electrical Engineering from USC and a Bachelor's degree from NIT Trichy. He has work experience in memory circuit design at Dolphin Technology, chip validation and failure analysis at Broadcom, and digital and power embedded systems design at CDOT Alcatel-Lucent Research Center. His technical skills include Verilog, C, Perl, and digital design tools from Synopsys and Cadence. He has completed academic projects in memory controller design, ATPG, processor performance simulation, and network processor design.
This document discusses Toshiba's 65nm (TC320) family of ultra-high density and ultra-low power system-on-chip (SoC) and system-in-package (SiP) solutions. The 65nm process technology offers unprecedented integration levels and power savings. It allows easy mixing of analog and digital cores on a single chip. The TC320 family is well-suited for applications such as mobile phones and portable media players that require high integration and low power consumption.
The signal processing algorithms can be implemented on hardware using various strategies such as DSP processors and ASIC. This PPT compares and contrasts the two methods.
Sonia Sharma has worked as a physical design engineer and staff engineer at STMicroelectronics since 2006 specializing in SoC top level design, block implementation, analog and digital integration, ESD closure, and library development from 90nm to 28nm process nodes. Her responsibilities included place and route, timing analysis, physical verification, I/O ring creation, and characterization of standard cell libraries.
ASIC DESIGN OF MINI-STEREO DIGITAL AUDIO PROCESSOR UNDER SMIC 180NM TECHNOLOGYIlango Jeyasubramanian
- Designed and analyzed a complete MSDAP with optimized convolution computation by only shifts and adds using power-of-2 coefficients. Synthesized the chip through high level architecture design (C Program), Logic synthesis (Synopsys Design Compiler) and Physical Synthesis (Synopsys IC compiler).
- Achieved a low power consumption of 3.1438mW at 29.186Mhz clock frequency, with core utilization of 70% and chip area of 1.29mm2.
Nathaniel Weathers is a motivated field operations personnel with over 20 years of experience in network engineering and operations. He has extensive experience testing, installing, and troubleshooting fiber optic and copper networks including experience with test equipment from EXFO, JDSU, Fluke, and Acterna. He is proficient in Microsoft Office, network monitoring software, and various carrier systems. His most recent role is as a Datacenter Tech III at TELX LLC where he performs remote hands services and oversees infrastructure installations and maintenance.
This document is a resume for Jaydip Patel seeking an internship or entry-level position in VLSI design and validation. It summarizes his education, including an M.S. in Electrical and Electronics Engineering from California State University, Sacramento and a B.S. in Electronics and Communication Engineering from Gujarat University, India. It also lists relevant coursework, professional experience including internships, tools and software skills, and projects in analog and mixed signal design, logic design, computer architecture, and VLSI validation and testing.
Shruti Nalla seeks a position as a VLSI physical design engineer. She has experience with Cadence tools through an internship and has worked on physical design flows from netlist to GDS II. She describes several projects involving floorplanning, placement, routing, and timing closure on designs from 90nm to 180nm technology nodes. Her roles included performing checks, analysis, and closure tasks. She is skilled in TCL, C programming, and Cadence tools including Encounter, RTL Compiler, Virtuoso, and Assura. She holds a B.Tech in ECE and her academic project involved a low power propeller LED display.
Manoj Verma is a physical design engineer with over 2.5 years of experience in 16nm, 20nm, and 28nm technologies. He has worked on projects with up to 0.6 million gates including floorplanning, placement, routing, timing closure, power analysis, and physical verification. His skills include experience with EDA tools like Aprisa AtopTech, PrimeTime, Tempus, Calibre, and he has developed automation flows for tasks like memory grouping and H-tree building. He holds a B.E. in Electronics and Communication Engineering with 8.81 CGPA from LJ Institute of Engineering and Technology.
Girish Bharadwaj is seeking a position as a physical design engineer where he can contribute to growth while advancing. He has over 4 years of experience in physical design closure, verification, and low power techniques. His skills include placement and routing, timing analysis, custom layout, and scripting. He has worked on blocks up to 14.5mm^2 and completed tapeout of SoCs at TSMC 28nm. Girish holds an M.Tech in VLSI design and has published work in conferences.
The document provides profile information and career details for Chandan Merwade. It summarizes his education as an Electronics and Communication Engineering graduate with experience in ASIC design physical layout. His core competencies include understanding CMOS theory, the physical design flow, placement and routing. Projects involved block-level design of circuits using Synopsys and Cadence tools, addressing challenges like timing closure and design rule violations.
This document is a resume for Ramesh Kumar Bankapalli summarizing his objective, qualifications, skills and projects. He has a PG Diploma in ASIC Design from RV-VLSI Design Center and an M.Tech in VLSI. He has experience with synthesis tools like PrimeTime and design tools like IC Compiler. His projects include block level physical design of a torpedo subsystem and static timing analysis using 180nm technology.
Prince Kumar is an ASIC/PD engineer with over 1 year of experience in physical design. He has skills in floorplanning, placement, routing, timing closure, and power optimization. His experience includes a project at RV VLSI Design Center working on a 40nm design with 34 macros, 40K standard cells, area of 4.2mm2, power budget of 600mW, and IR drop below 55mV. He is interested in digital design, physical design, STA, Verilog, and physical verification. Prince Kumar holds an Advanced Diploma in ASIC Design and a B.Tech in ECE.
The resume summarizes Pavan Teja Dama's qualifications for an ASIC design position. He has a PG Diploma and MTech in VLSI design. His core competencies include experience with EDA tools like IC Studio and layout design skills in analog, memory and standard cells. Some of his project experiences involved SRAM memory layout in 28nm technology and analog layout design in 180nm process. He is proficient in languages like C, Verilog and VHDL.
- Mahesh has over 3 years of experience in VLSI semiconductor industry in physical design. He has worked on designs from floorplanning to GDSII.
- He has worked on two successful tapeouts at PMC-Sierra and AMD with timing and physical closure activities. At PMC-Sierra, he implemented power gating and clock trees on 28nm chips.
- At AMD, he routed clocks and implemented shielding on a critical 16nm design with multiple clocks up to 909MHz.
Jon Berry has over 15 years of experience in physical design and layout of integrated circuits. He has worked at Intel, Qimonda, and Infineon in roles such as staff engineer, senior engineer, and engineer. Berry has expertise in place-and-route methodology, floorplanning, timing closure, and verifying designs meet requirements for power, area, routing congestion and manufacturability. He also has skills in developing automation scripts, training others, and troubleshooting layout tools.
Jon Berry has over 15 years of experience in physical design and layout of integrated circuits. He has worked at Intel, Qimonda, and Infineon in roles such as staff engineer, senior engineer, and engineer. Berry has expertise in place-and-route methodology, floorplanning, timing closure, and verifying designs meet requirements for power, area, routing congestion and manufacturability. He also has skills in developing automation scripts, training others, and troubleshooting layout tools.
Vikas Gupta has over 4 years of experience in embedded board design. He has worked on projects involving high speed board design in consumer and automotive electronics. Some of his responsibilities have included requirements gathering, schematic design, layout coordination, board testing, debugging, and production support. He has expertise in developing analog, digital and mixed signal multilayer board designs using tools such as ORCAD and Allegro. He has experience interfacing with technologies such as I2C, SPI, USB 3.0, Ethernet, and memory. Vikas holds a Bachelor's degree in electronics and communication engineering.
William S. Check Jr. has over 30 years of experience in analog and mixed-signal integrated circuit design. He is currently a Staff Design Engineer at Cadence Design Systems, where he generates behavioral models and designs analog IP blocks. Previously he has held various engineering leadership roles developing high-speed serial communication chips, including as Director of Applications Engineering and Architect and Principal Design Engineer. He has extensive experience in circuit design, simulation, verification, and characterization.
Sr. Kakarla is a physical design engineer with over 6 years of experience in roles including IC physical design, CAD STA, layout design automation, and corporate design solutions. He has worked at Qualcomm and Intel on projects ranging from 32nm to 10nm technology nodes. Sr. Kakarla seeks a challenging role implementing high performance and low power SOC designs.
- The candidate has over 11 years of experience in hardware design, including 9+ months at Neotech Systems and 2 years and 4 months at Larsen & Toubro.
- Areas of expertise include mixed-signal design, microcontroller interfacing, power distribution, protocol communication, sensor interfacing, and reverse engineering.
- Notable projects include developing environmental monitoring systems, low voltage cut-off devices, and AC to DC converters.
The document is an experience summary and resume for Chandan Kumar. It summarizes his 6+ years of experience in hardware design, including mixed signal design, communication protocols, and reverse engineering of AC drives. It also lists his educational qualifications and provides details on several projects he contributed to, including environmental monitoring systems, low voltage cut-off devices, and capacitor module design.
- Kenneth L. Feken has over 20 years of experience in electronics assembly, testing, and troubleshooting. He has worked for companies like Intel, CDTI, Tektronix, and Laerdal Medical Supply where he performed tasks like circuit board assembly, soldering, testing, reworking, and quality control.
- He has an Associate's Degree in Electrical Engineering Technology from ITT Technical Institute where he gained skills in engineering, programming, software, and testing.
- Currently, he is looking for a position where he can utilize his extensive experience in electronics assembly, circuit board work, software testing, and troubleshooting.
Syed Atif Shamim has over 9 years of experience in telecommunications, networking, and information security. He holds an Executive Master's in Information Security Systems from the University of The Cumberland and has worked in roles managing networks, data centers, and IT infrastructure for various organizations in Pakistan, Abu Dhabi, and the United States. He has extensive technical skills across networking, routing, switching, wireless, cloud computing, and information security technologies.
John Nguyen is a multifaceted wireless network engineer with over 15 years of experience in diverse telecom roles. He has extensive expertise in wireless network engineering, development, testing and troubleshooting. Currently he works as a wireless mobility field engineer contractor for Ericsson, where he provisions equipment for major wireless carriers and performs technical support. Nguyen has a background in wireless integration and translation engineering for AT&T, as well as roles with Ericsson, Motorola, IBM, Pluris and Cisco in engineering, testing and technical support. He holds several industry certifications and has a bachelor's degree in electronic engineering technology.
This document is a resume for Meldia Thomas seeking a position as a Physical Design Engineer. It summarizes her education and qualifications which include an advanced diploma in ASIC Design - Physical Design in 2017 and a Bachelor's Degree in Electronics and Communication in 2016. Her core competencies include experience with ASIC design flows, physical design tasks like floorplanning, timing analysis, and signoff. She has worked on projects implementing an 180nm torpedo subsystem and performing static timing analysis. Her objective is to enhance her skills and gain professional growth working as a Physical Design Engineer.
Shruti Nalla seeks a position as a VLSI physical design engineer. She has experience with Cadence tools through an internship and has worked on physical design flows from netlist to GDS II. She describes several projects involving floorplanning, placement, routing, and timing closure on designs from 90nm to 180nm technology nodes. Her roles included performing checks, analysis, and closure tasks. She is skilled in TCL, C programming, and Cadence tools including Encounter, RTL Compiler, Virtuoso, and Assura. She holds a B.Tech in ECE and her academic project involved a low power propeller LED display.
Manoj Verma is a physical design engineer with over 2.5 years of experience in 16nm, 20nm, and 28nm technologies. He has worked on projects with up to 0.6 million gates including floorplanning, placement, routing, timing closure, power analysis, and physical verification. His skills include experience with EDA tools like Aprisa AtopTech, PrimeTime, Tempus, Calibre, and he has developed automation flows for tasks like memory grouping and H-tree building. He holds a B.E. in Electronics and Communication Engineering with 8.81 CGPA from LJ Institute of Engineering and Technology.
Girish Bharadwaj is seeking a position as a physical design engineer where he can contribute to growth while advancing. He has over 4 years of experience in physical design closure, verification, and low power techniques. His skills include placement and routing, timing analysis, custom layout, and scripting. He has worked on blocks up to 14.5mm^2 and completed tapeout of SoCs at TSMC 28nm. Girish holds an M.Tech in VLSI design and has published work in conferences.
The document provides profile information and career details for Chandan Merwade. It summarizes his education as an Electronics and Communication Engineering graduate with experience in ASIC design physical layout. His core competencies include understanding CMOS theory, the physical design flow, placement and routing. Projects involved block-level design of circuits using Synopsys and Cadence tools, addressing challenges like timing closure and design rule violations.
This document is a resume for Ramesh Kumar Bankapalli summarizing his objective, qualifications, skills and projects. He has a PG Diploma in ASIC Design from RV-VLSI Design Center and an M.Tech in VLSI. He has experience with synthesis tools like PrimeTime and design tools like IC Compiler. His projects include block level physical design of a torpedo subsystem and static timing analysis using 180nm technology.
Prince Kumar is an ASIC/PD engineer with over 1 year of experience in physical design. He has skills in floorplanning, placement, routing, timing closure, and power optimization. His experience includes a project at RV VLSI Design Center working on a 40nm design with 34 macros, 40K standard cells, area of 4.2mm2, power budget of 600mW, and IR drop below 55mV. He is interested in digital design, physical design, STA, Verilog, and physical verification. Prince Kumar holds an Advanced Diploma in ASIC Design and a B.Tech in ECE.
The resume summarizes Pavan Teja Dama's qualifications for an ASIC design position. He has a PG Diploma and MTech in VLSI design. His core competencies include experience with EDA tools like IC Studio and layout design skills in analog, memory and standard cells. Some of his project experiences involved SRAM memory layout in 28nm technology and analog layout design in 180nm process. He is proficient in languages like C, Verilog and VHDL.
- Mahesh has over 3 years of experience in VLSI semiconductor industry in physical design. He has worked on designs from floorplanning to GDSII.
- He has worked on two successful tapeouts at PMC-Sierra and AMD with timing and physical closure activities. At PMC-Sierra, he implemented power gating and clock trees on 28nm chips.
- At AMD, he routed clocks and implemented shielding on a critical 16nm design with multiple clocks up to 909MHz.
Jon Berry has over 15 years of experience in physical design and layout of integrated circuits. He has worked at Intel, Qimonda, and Infineon in roles such as staff engineer, senior engineer, and engineer. Berry has expertise in place-and-route methodology, floorplanning, timing closure, and verifying designs meet requirements for power, area, routing congestion and manufacturability. He also has skills in developing automation scripts, training others, and troubleshooting layout tools.
Jon Berry has over 15 years of experience in physical design and layout of integrated circuits. He has worked at Intel, Qimonda, and Infineon in roles such as staff engineer, senior engineer, and engineer. Berry has expertise in place-and-route methodology, floorplanning, timing closure, and verifying designs meet requirements for power, area, routing congestion and manufacturability. He also has skills in developing automation scripts, training others, and troubleshooting layout tools.
Vikas Gupta has over 4 years of experience in embedded board design. He has worked on projects involving high speed board design in consumer and automotive electronics. Some of his responsibilities have included requirements gathering, schematic design, layout coordination, board testing, debugging, and production support. He has expertise in developing analog, digital and mixed signal multilayer board designs using tools such as ORCAD and Allegro. He has experience interfacing with technologies such as I2C, SPI, USB 3.0, Ethernet, and memory. Vikas holds a Bachelor's degree in electronics and communication engineering.
William S. Check Jr. has over 30 years of experience in analog and mixed-signal integrated circuit design. He is currently a Staff Design Engineer at Cadence Design Systems, where he generates behavioral models and designs analog IP blocks. Previously he has held various engineering leadership roles developing high-speed serial communication chips, including as Director of Applications Engineering and Architect and Principal Design Engineer. He has extensive experience in circuit design, simulation, verification, and characterization.
Sr. Kakarla is a physical design engineer with over 6 years of experience in roles including IC physical design, CAD STA, layout design automation, and corporate design solutions. He has worked at Qualcomm and Intel on projects ranging from 32nm to 10nm technology nodes. Sr. Kakarla seeks a challenging role implementing high performance and low power SOC designs.
- The candidate has over 11 years of experience in hardware design, including 9+ months at Neotech Systems and 2 years and 4 months at Larsen & Toubro.
- Areas of expertise include mixed-signal design, microcontroller interfacing, power distribution, protocol communication, sensor interfacing, and reverse engineering.
- Notable projects include developing environmental monitoring systems, low voltage cut-off devices, and AC to DC converters.
The document is an experience summary and resume for Chandan Kumar. It summarizes his 6+ years of experience in hardware design, including mixed signal design, communication protocols, and reverse engineering of AC drives. It also lists his educational qualifications and provides details on several projects he contributed to, including environmental monitoring systems, low voltage cut-off devices, and capacitor module design.
- Kenneth L. Feken has over 20 years of experience in electronics assembly, testing, and troubleshooting. He has worked for companies like Intel, CDTI, Tektronix, and Laerdal Medical Supply where he performed tasks like circuit board assembly, soldering, testing, reworking, and quality control.
- He has an Associate's Degree in Electrical Engineering Technology from ITT Technical Institute where he gained skills in engineering, programming, software, and testing.
- Currently, he is looking for a position where he can utilize his extensive experience in electronics assembly, circuit board work, software testing, and troubleshooting.
Syed Atif Shamim has over 9 years of experience in telecommunications, networking, and information security. He holds an Executive Master's in Information Security Systems from the University of The Cumberland and has worked in roles managing networks, data centers, and IT infrastructure for various organizations in Pakistan, Abu Dhabi, and the United States. He has extensive technical skills across networking, routing, switching, wireless, cloud computing, and information security technologies.
John Nguyen is a multifaceted wireless network engineer with over 15 years of experience in diverse telecom roles. He has extensive expertise in wireless network engineering, development, testing and troubleshooting. Currently he works as a wireless mobility field engineer contractor for Ericsson, where he provisions equipment for major wireless carriers and performs technical support. Nguyen has a background in wireless integration and translation engineering for AT&T, as well as roles with Ericsson, Motorola, IBM, Pluris and Cisco in engineering, testing and technical support. He holds several industry certifications and has a bachelor's degree in electronic engineering technology.
This document is a resume for Meldia Thomas seeking a position as a Physical Design Engineer. It summarizes her education and qualifications which include an advanced diploma in ASIC Design - Physical Design in 2017 and a Bachelor's Degree in Electronics and Communication in 2016. Her core competencies include experience with ASIC design flows, physical design tasks like floorplanning, timing analysis, and signoff. She has worked on projects implementing an 180nm torpedo subsystem and performing static timing analysis. Her objective is to enhance her skills and gain professional growth working as a Physical Design Engineer.
1. venkatag
M: +91 9010511113
Venkatgantainfo@gmail.com
Professional Summary
Responsible and Expertise in Flow from Net List to GDS II, Floor Planning, Place and Route,
CTS and Timing. Responsible for Block level Floor planning, Power planning, End Cap
Placement, Placement Driven Synthesis. Post placement Timing closure, Clock Tree Synthesis,
Post clock Timing closure, clock slew fixing, Set-up Fixing on prewired database. Hold fixing
on prewired database, Detailed Routing, Fixing DRCs Checks, Timing Fixes.
TECHNICAL SKILLS
Physical Design: Cadence -SOC Encounter Suit,Innovus,Cadence-ETS and Tempus,
IBM CAD tool suit,Prime Timer,ICC.
Simulation& Synthesis: NC Sim Cadence, Cadence, Xilinx11.1i,ACTIVE- HDL5.7i,
ModelSim9.4i, RTL Compiler.
HDL’s and Script: System Verilog,Verilog,VHDL and TCL scripts
Office Tools: UNIX environment and Windows.
EDUCATIONAL QUALIFICATION
M.Tech in VLSI S D (Dec’2007 – Feb’2010), Hyderabad (JNTUH), A.P. %: 76, 2010
EXPERIENCE
Cyient ,Hydrabad. 2015’Aug- till Date
My role as Senior Physical Design Engineer
• Responsible for Block level Floor planning, Power planning, End Cap Placement,
Placement Driven Synthesis
• Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing ,Late mode optimization (Set-up Fixing on prewired database).
• Early mode optimization (Hold fixing on prewired database), Detailed Routing, Fixing
DRCs Checks, Timing Fixes,Signoff fixes…
Synapse Techno Design Innovations Pvt Ltd,Bangalore. Dec’2014-2015’Aug
My role as Senior Engineer
• Responsible for Block level Floor planning, Power planning, End Cap Placement,
Placement Driven Synthesis
• Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing ,Late mode optimization (Set-up Fixing on prewired database).
• Early mode optimization (Hold fixing on prewired database), Detailed Routing, Fixing
DRCs Checks, Timing Fixes,Signoff fixes…
WEG Hr Services Ltd, Bangalore May’2013 – Nov’2014
The role involves providing complete technical, economical and practical real time consulting
with regards to Floor Planning, Place and Route, CTS and Timing. Responsible for Block level
2. Floor planning, Power planning, End Cap Placement, Placement Driven Synthesis. Post
placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock slew
fixing,Set-up Fixing on prewired database.Hold fixing on prewired database, Detailed Routing,
Fixing DRCs Checks, ETS Timing Fixes.
InfoTech Enterprises Ltd, Hyderabad Aug’2011 – April’2013
My role as Design Engineer
• Responsible for Block level Floor planning, Power planning, End Cap Placement,
Placement Driven Synthesis.
• Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing ,Late mode optimization (Set-up Fixing on prewired database).
• Early mode optimization (Hold fixing on prewired database), Detailed Routing, Fixing
DRCs Checks,Timing Fixes.
PROJECTS
Project 1:
Description: Cu-28nm Technology, 15 Macros, Standard cell Count 480K, Initial Utilization
65.3%, No. Of Ports 2845, Frequency 850MHz, Rectangular Shape (0.0 0.0 4930.0 1889.4)
Role: Block level Physical Design.
Responsibilities:
• Responsible for Net List to GDS II FLOW, Block level Floor planning, Power
planning, Pre-placed cells Placement, Placement and Routing.
• Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing, Set-up Fixing on prewired and postwired database.
• Hold fixing on postwired database and Optimization, Detailed Routing, DRCs
Checks and Antenna fixing ,Timing Fixes and Singoff fixes….
Project 2:
Description: Cu-45nm Technology, 18 Macros, Standard cell Count 69K, Initial Utilization
70.2%, No. Of Ports 2058, Frequency 200MHz, Rectangular Shape (0.0 0.0 3732.0 2302.4)
Role: Block level Physical Design.
3. Responsibilities:
• Responsible for Block level Floor planning, Power planning, End Cap Placement,
Placement and Routing.
• Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing, Set-up Fixing on prewired database.
• Hold fixing on prewired database and Optimization, Detailed Routing, DRCs ,LVS
Checks and Antenna fixing ,EinceTimer Timing Fixes.
Project 3:
Description: Cu-45nm Technology, 52 Macros, Standard Cell Count 1.0Million, Initial
Utilization 70.22%, No. Of Ports 5089, Frequency 200MHz, Rectangular Shape (0.0 0.0
4899.94 4800.32)
Role: Block level Physical Design
Responsibilities:
• Involved in Flow from Net List to GDS II, Floor Planning, Place and Route, CTS and
Timing
• Responsible for Block level Floor planning, Power planning, End Cap Placement,
Placement Driven Synthesis.
• Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing ,Set-up Fixing on prewired database.
• Hold fixing on prewired database and Optimization , Detailed Routing,DRCs,LVS
Checks and Antenna fixing ,EinceTimer Timing Fixes.
Project 4:
Description: Cu-65nm Technology, 63 Macros, Standard Cell Count 2M, Initial Utilization
70.9%, No. Of Ports 2004, Frequency 500MHz, Rectangular Shape (0.0 0.0 4980.5 3800.7).
Role: Block level Physical Design.
Responsibilities:
• Responsible for Block level Floor planning, Power planning, De Cap Placement,
Placement Driven Synthesis.
• Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing, Set-up Fixing on prewired database.
• Hold fixing on prewired database and Optimization, Detailed Routing, DRCs,LVS
Checks and Antenna fixing ,EinceTimer Timing Fixes.
Project 5: Oct 2011 – Feb 2013
Description: Cu-65nm Technology, 63 Macros, Standard Cell Count 62k, Initial Utilization
69.5%, No. Of Ports 1704, Frequency 100MHz, Rectangular Shape (0.0 0.0 3980.5 2000.3).
Role: Block level Physical Design.
Responsibilities:
• Responsible for Block level Floor planning, Power planning, De Cap Placement,
Placement Driven Synthesis.
4. • Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing, Set-up Fixing on prewired database.
• Hold fixing on prewired database and Optimization, Detailed Routing, DRCs, LVS
Checks and Antenna fixing, Eince Timer Timing Fixes.
Project 6: Maxim AX64HeadPhone IC Aug 2011 – Oct 2011
Verification Test Environment for HEADPhone-IC and Verify With Cadence-NC Sim.
Scope : Verify the different scenarios of IC’s Features.
Platform : System-Verilog, Verilog and UVM Environment, Cadence Tools.
Description : This project involves the verification of the Max12 Ic’s different scenarios
with various characteristics. With the required specification and features prepare the test plan
and implement the verification environment for test features of headphone IC. To configure the
register set in this project used the Pci and i2c protocol.
Responsibilities:
• Developing the test suit, Performed the functional simulation.
• Performed the code and Functional coverage by writing the coverage groups for each
scenario of headphone Incusing TCL scripts for running regressions.
PERSONAL DETAILS
Name : venkataapparao
Mother Name : Durga
Date of Birth : 15th
May,1984
Languages known : English, Telugu and Hindi.
Nationality : Indian
Permanent Address : Patanucheru,Medak .DIST,
PIN : 502032.
DECLARATION: I hereby declare that the above information is true and correct to the best of
my knowledge.
Date: - venkatag