This document contains the resume of Venkataapparao. It summarizes his professional experience in physical design including floorplanning, placement and routing. It lists his technical skills such as Cadence Encounter and various EDA tools. It also provides details of his educational qualifications and projects undertaken during previous roles focusing on physical implementation from netlist to GDSII.

1. venkatag
M: +91 9010511113
Venkatgantainfo@gmail.com
Professional Summary
Responsible and Expertise in Flow from Net List to GDS II, Floor Planning, Place and Route,
CTS and Timing. Responsible for Block level Floor planning, Power planning, End Cap
Placement, Placement Driven Synthesis. Post placement Timing closure, Clock Tree Synthesis,
Post clock Timing closure, clock slew fixing, Set-up Fixing on prewired database. Hold fixing
on prewired database, Detailed Routing, Fixing DRCs Checks, Timing Fixes.
TECHNICAL SKILLS
Physical Design: Cadence -SOC Encounter Suit,Innovus,Cadence-ETS and Tempus,
IBM CAD tool suit,Prime Timer,ICC.
Simulation& Synthesis: NC Sim Cadence, Cadence, Xilinx11.1i,ACTIVE- HDL5.7i,
ModelSim9.4i, RTL Compiler.
HDL’s and Script: System Verilog,Verilog,VHDL and TCL scripts
Office Tools: UNIX environment and Windows.
EDUCATIONAL QUALIFICATION
M.Tech in VLSI S D (Dec’2007 – Feb’2010), Hyderabad (JNTUH), A.P. %: 76, 2010
EXPERIENCE
Cyient ,Hydrabad. 2015’Aug- till Date
My role as Senior Physical Design Engineer
• Responsible for Block level Floor planning, Power planning, End Cap Placement,
Placement Driven Synthesis
• Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing ,Late mode optimization (Set-up Fixing on prewired database).
• Early mode optimization (Hold fixing on prewired database), Detailed Routing, Fixing
DRCs Checks, Timing Fixes,Signoff fixes…
Synapse Techno Design Innovations Pvt Ltd,Bangalore. Dec’2014-2015’Aug
My role as Senior Engineer
• Responsible for Block level Floor planning, Power planning, End Cap Placement,
Placement Driven Synthesis
• Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing ,Late mode optimization (Set-up Fixing on prewired database).
• Early mode optimization (Hold fixing on prewired database), Detailed Routing, Fixing
DRCs Checks, Timing Fixes,Signoff fixes…
WEG Hr Services Ltd, Bangalore May’2013 – Nov’2014
The role involves providing complete technical, economical and practical real time consulting
with regards to Floor Planning, Place and Route, CTS and Timing. Responsible for Block level

2. Floor planning, Power planning, End Cap Placement, Placement Driven Synthesis. Post
placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock slew
fixing,Set-up Fixing on prewired database.Hold fixing on prewired database, Detailed Routing,
Fixing DRCs Checks, ETS Timing Fixes.
InfoTech Enterprises Ltd, Hyderabad Aug’2011 – April’2013
My role as Design Engineer
• Responsible for Block level Floor planning, Power planning, End Cap Placement,
Placement Driven Synthesis.
• Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing ,Late mode optimization (Set-up Fixing on prewired database).
• Early mode optimization (Hold fixing on prewired database), Detailed Routing, Fixing
DRCs Checks,Timing Fixes.
PROJECTS
Project 1:
Description: Cu-28nm Technology, 15 Macros, Standard cell Count 480K, Initial Utilization
65.3%, No. Of Ports 2845, Frequency 850MHz, Rectangular Shape (0.0 0.0 4930.0 1889.4)
Role: Block level Physical Design.
Responsibilities:
• Responsible for Net List to GDS II FLOW, Block level Floor planning, Power
planning, Pre-placed cells Placement, Placement and Routing.
• Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing, Set-up Fixing on prewired and postwired database.
• Hold fixing on postwired database and Optimization, Detailed Routing, DRCs
Checks and Antenna fixing ,Timing Fixes and Singoff fixes….
Project 2:
Description: Cu-45nm Technology, 18 Macros, Standard cell Count 69K, Initial Utilization
70.2%, No. Of Ports 2058, Frequency 200MHz, Rectangular Shape (0.0 0.0 3732.0 2302.4)
Role: Block level Physical Design.

3. Responsibilities:
• Responsible for Block level Floor planning, Power planning, End Cap Placement,
Placement and Routing.
• Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing, Set-up Fixing on prewired database.
• Hold fixing on prewired database and Optimization, Detailed Routing, DRCs ,LVS
Checks and Antenna fixing ,EinceTimer Timing Fixes.
Project 3:
Description: Cu-45nm Technology, 52 Macros, Standard Cell Count 1.0Million, Initial
Utilization 70.22%, No. Of Ports 5089, Frequency 200MHz, Rectangular Shape (0.0 0.0
4899.94 4800.32)
Role: Block level Physical Design
Responsibilities:
• Involved in Flow from Net List to GDS II, Floor Planning, Place and Route, CTS and
Timing
• Responsible for Block level Floor planning, Power planning, End Cap Placement,
Placement Driven Synthesis.
• Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing ,Set-up Fixing on prewired database.
• Hold fixing on prewired database and Optimization , Detailed Routing,DRCs,LVS
Checks and Antenna fixing ,EinceTimer Timing Fixes.
Project 4:
Description: Cu-65nm Technology, 63 Macros, Standard Cell Count 2M, Initial Utilization
70.9%, No. Of Ports 2004, Frequency 500MHz, Rectangular Shape (0.0 0.0 4980.5 3800.7).
Role: Block level Physical Design.
Responsibilities:
• Responsible for Block level Floor planning, Power planning, De Cap Placement,
Placement Driven Synthesis.
• Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing, Set-up Fixing on prewired database.
• Hold fixing on prewired database and Optimization, Detailed Routing, DRCs,LVS
Checks and Antenna fixing ,EinceTimer Timing Fixes.
Project 5: Oct 2011 – Feb 2013
Description: Cu-65nm Technology, 63 Macros, Standard Cell Count 62k, Initial Utilization
69.5%, No. Of Ports 1704, Frequency 100MHz, Rectangular Shape (0.0 0.0 3980.5 2000.3).
Role: Block level Physical Design.
Responsibilities:
• Responsible for Block level Floor planning, Power planning, De Cap Placement,
Placement Driven Synthesis.

4. • Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock
slew fixing, Set-up Fixing on prewired database.
• Hold fixing on prewired database and Optimization, Detailed Routing, DRCs, LVS
Checks and Antenna fixing, Eince Timer Timing Fixes.
Project 6: Maxim AX64HeadPhone IC Aug 2011 – Oct 2011
Verification Test Environment for HEADPhone-IC and Verify With Cadence-NC Sim.
Scope : Verify the different scenarios of IC’s Features.
Platform : System-Verilog, Verilog and UVM Environment, Cadence Tools.
Description : This project involves the verification of the Max12 Ic’s different scenarios
with various characteristics. With the required specification and features prepare the test plan
and implement the verification environment for test features of headphone IC. To configure the
register set in this project used the Pci and i2c protocol.
Responsibilities:
• Developing the test suit, Performed the functional simulation.
• Performed the code and Functional coverage by writing the coverage groups for each
scenario of headphone Incusing TCL scripts for running regressions.
PERSONAL DETAILS
Name : venkataapparao
Mother Name : Durga
Date of Birth : 15th
May,1984
Languages known : English, Telugu and Hindi.
Nationality : Indian
Permanent Address : Patanucheru,Medak .DIST,
PIN : 502032.
DECLARATION: I hereby declare that the above information is true and correct to the best of
my knowledge.
Date: - venkatag