Amit Vijay Patil is an embedded OS professional with 8 years of experience in automotive embedded systems. He is currently a senior software design engineer working on head-up display projects. His experience includes working on ISO 26262 standards, diverse microcontroller architectures, functional requirement implementations, driver development, memory management, OS scheduling, communication protocols, and signal processing algorithms. He holds an MS in advanced embedded systems and aims to take on more ambitious embedded projects that utilize his skills in embedded OS and signal processing design.

1. Amit Vijay Patil
Phone: +91 97 6441 5616
Email: amitpatz@gmail.com
Embedded OS Professional - 8 years of experience in Embedded Systems
(automotive).
Career Profile
Aiming to be an architect and design an ambitious in-depth challenging project in core embedded field
which will explore and utilize my development skills and research in Embedded OS and signal
processing designing. I am, willing to play a key role for an organizational growth.
Key Responsibilities
• Working on ISO-26262 ASIL A for Head-Up Displays (HUD)
• Worked on diverse Micro controller Architectures. Presently working on Renesas V850.
• Module design with Class and Object diagram, Sequence and interface design UML.
• Functional Requirement based implementation and configuration of Autosar modules: NvM, MCAL,
Os-SchM.
• Working on Drivers and Memory Management involving NVM Erase, Write and Tear safety-recovery
design mechanism and wear-leveling, endurance optimizations.
• Expertise of OS Scheduler, EEP, Complex drivers (stepper/DC control) and Hardware-Software
interface, Communication protocols.
• Working exposure on DSP Processor (TI-CCS) for Signal Processing Algorithms.
• Full time Involvement in Rapid Prototyping PoC development for automotive concepts.
Professional Work Experiences
Employer: Visteon Automotive Electronics (Earlier Johnson Controls, Automotive Experience)
I am presently working as a Senior Software Design Engineer for diverse customers in JAPAN, NA and
Emerging Markets handling Driver Information System (Products: Combiner HUD, Windshield HUD,
Instrument Cluster).
Work Period: May 2013 – present
Employer: Robert Bosch Engineering and Business Solutions Limited (RBEI, Bangalore)
I was working as a Senior Embedded Software Engineer for Emerging Markets handling Engine
Management System for multi Power Train Drives. RBEI is largest off-shore development centre
outside Germany.(http://www.boschindia.com)
Work Period: Aug 2011 – May 2013

2. Employer: Giesecke and Devrient India (G&D)
Working as an Embedded Software Engineer for Embedded OS Development under Embedded
Department (Telecommunications) in Pune. The R&D centre in India is integrated with HQ in Munich,
Germany. G&D are leading end-to-end Product based competitors in Note Processing, Card services,
and Government solutions. (www.gi-de.com)
Work Period: April 2008 – Aug 2011
PROJECTS
A. ECU Software responsibility for Head-Up Displays (HUD).
Duration: 8 months Designation: Senior Design Software Engineer
Key Responsibilities:
• Prepare Risk analysis, module breakdown form and decision making forms.
• Responsibility to develop MCAL, EEP and memory services, GFX-TFT Video Input/output driver, IO
abstraction, Boot loader, SWC module and its interface design in UML, Severity level Critical/Catastrophic
issue analysis using 5 Why/Fish bone analysis and its mitigation design proposals.
• Ownership of OS task scheduling and resource utilization with optimization.
• Ownership of Safety design and implementation.
• On-site opportunities for GFX-TFT driver platform knowledge. Travelled to Japan, as System Team guest, to
attend customer meetings and giving technical presentations.
B. ECU Software responsibility for Driver Information cluster.
Duration: 6 months Designation: Staff Software Engineer
Key Responsibilities:
• Based on RFP, prepare a prototype design for an instrument cluster.
• Prepare Risk analysis, module breakdown form and decision making forms.
• Responsibility to develop LCD module driver, MCU, CAN stack integration, power cycles.
C. ECU Software responsibility for Small engine motors and Low Priced Vehicle.
Duration: 8 months Designation: Senior Embedded Software Engineer
Key Responsibilities:
• Writing software for GPTA (Timer array for digital signals) signals mapping by preparing the Thoss’s list
from TriCore datasheet.
• Design and implementation of complex driver gasoline injection capture and compare generation of time
frame and sending it to slave CNG injectors using power stages.
• Algorithm design and implementation for generation of engine speed(no crank sensor) calculation from
averaging of ignition pulse capture.
• Hardware Software Interface requirement implementation and signal quantization to fixed point variables.
• Working with architects and technical brainstorming with function teams.
• Stepper (idle speed actuator)/DC motor (Electronic throttle) control software mechanism software

3. debugging on ECU using UDE.
• Exposure to end to end Gasoline Systems with different variants.
D. OS scheduling for EMS system.
Duration: 4 months Designation: Senior Embedded Software Engineer
Key challenges and Responsibilities:
• Understanding ERCOS real time OS for event based and time based scheduling.
• Analysis of process ordering for critical process and critical data saving based on system state diagram for
current and next driving cycles.
• Improvement of system performance and overheating problem solved with exposure to 8D reports.
• Basic Engine management software and unit hardware testing on simulated car and delivery to calibration
team.
E. Architecture requirements based analysis and development for Embedded OS for 3G
JavacardsTm
.
Duration: 14 months Designation: Embedded Software Engineer
Key challenges and Responsibilities:
• Hardware: Samsung Chip (S3FS9XX) based on ARM 7TDMI 90nm core(32 bit) for SIM Cards.
• Understanding of Memory Management, Garbage Collector (GC) and NVM Driver.
• Implementation of Over the Air Remote files and applet management Concatenated Message buffer
handling
• Discussion with SME’s and decision making on requirements (AURS). Interaction with German Colleagues.
F. Native Embedded OS Porting on CalmRISC based Samsung 90nm architecture.
Duration: 15 months Designation: Embedded Software Engineer
Key challenges and Responsibilities:
• Understanding of design changes and re-design NVM Write-Erase module under memory management
from existing architecture for NVM.
• Secure Write mechanism design proposal based on 90nm architecture (32 bit) for Tear safety-
recovery and wear leveling optimizations.
• Coding in C and assembly using CalmShine16 IDE and C3200 Emulator with Samsung 90nm
CalmRISCTm
board.
• Ring Buffer Implementation (Celltick) for Message buffer to be stored in NVM achieving estimated Life
Cycle with Lint free code, R&D Documentation and Static Analysis, Unit Testing and debugging.
I. Masters Research Study Project: AR Model Spectral Estimation
Title: AR Model Spectral Estimation of real time bio-signals using National Instruments low cost USB
6009 DAQ
Key challenges and Responsibilities: Project Guide: Dr. Srikanth Thyagarajan
• Researching and implementing the spectral estimation techniques in C and Matlab.
• Verifying results with real time input signals like speech using NI USB 6009
• Future Enhancement: Implementing a algorithm on DSP processor TMS320c6416
II. Masters level Mini-Project: Adaptive Filters as Acoustic Noise Cancellers

4. Title: Study and Implementation of Adaptive Filter for Speech Signals
Key challenges and Responsibilities: Project Guide: Dr. Srikanth Thyagarajan
• To understand the Adaptive Filter theory and illustrate using Computer Exercises.
• Simulation of Adaptive filters in C and Matlab using a non-stationary signals: LMS and Kalman methods for
filtering the sine wave out of corrupted sine wave and deriving the inference.
• Speech (recorded signal) enhancement using both Adaptive filters.
III. Other Projects
• I2C interface based on Atmel 89c51.
• Implementation of Direct Cosine Transform algorithm for 2D and 1D signals in C.
• Game programming - Tic Tac Toe in C.
• VADIC: Voice Activated Device Control.
EDUCATIONAL QUALIFICATIONS:
• Master's (MS) degree in Advanced Embedded Systems Design from International
Institute of Information Technology, Pune with 3.6/4.0 CGPA in March 2008
• B.E. in Electronics and Telecomm from Pune University with 68% (distinction) in
September 2005.
• HSC (12th) board with 72.8 and SSC (10th) board with 70.5% score.
PROFESSIONAL SKILL SET:
Design Analysis: 8D, 5-Why, Fish bone
Architecture: UML module design, Autosar 3.1
Language/ Libraries: Strong skills in C, Assembly, UML, VC++, CImg Library, Core Java.
Simulator/Emulator/IDE/Debuggers: Renesase E1/minicube, Green Hills, Lauterbach, Softtune,
Keil, CCS, Dev C++, PCLint, OPENice 3200(Samsung), CalmShine16 and 16+, Visual Studio 8.0,
Eclipse, Rational Rose ClearCase UCM, Easee Version Tool.
Hardware: 89C52, TMS320C55xx / 64xx, ARM 7TDMI, CalmRISC, TriCore and 80251 cores, NI USB
6009 DAQ, Stepper control, H-Bridge, Relays and actuators, sensors.
Sound Subjects: DSP, Embedded DSP processors and Advanced Microcontrollers, C Programming –
Assembly, Operating Systems, Digital Image Processing, Embedded Design Cycle.
ACADEMIC ACHIEVEMENTS & CERTIFICATIONS
• Received Priyadarshini Academy Scholarship, Mumbai at Masters Level in Feb 2008.
• Completed VLSI Design Certification Course in 2004.
• Successfully cleared Entry level Basic language module with Second Division from CSI (Computer Society
of India) during first attempt in November 1998.
• Participated in National Level Project Competition at IIT Techfest 2005 in January
• 2nd in Programming Contest in Graphics in std. VIII at St. Xavier's School Computer Programming
Exhibition.
HOBBIES

5. • Reading Selected Books (fiction and non-fiction)
• Trekking, Rappelling, Astronomy.
• Programming.
• Football.
PERSONAL TRAITS
• Good Listener and quick grasper.
• Good communication and presentation skills.
• Team believer and initiator.
• Skilled and disciplined Working.
PERSONAL DETAILS
Father’s Name: Ex- Capt. Vijay P. Patil
Date of Birth: 5th May 1983
Present Address: Apartment Lotus and Lily, 6/05, Behind Rakshaq chowk, Pimple Nilakh, Pune
Permanent Address: 22, RajLaxmi bungalows, Harni Road, Vadodara (GUJ), India.
Permanent Contact No.: +91-9764415616
Languages Known: English, Hindi, Marathi, and German.
Alternate Email ID: amitpatz@gmail.co.in

6. • Reading Selected Books (fiction and non-fiction)
• Trekking, Rappelling, Astronomy.
• Programming.
• Football.
PERSONAL TRAITS
• Good Listener and quick grasper.
• Good communication and presentation skills.
• Team believer and initiator.
• Skilled and disciplined Working.
PERSONAL DETAILS
Father’s Name: Ex- Capt. Vijay P. Patil
Date of Birth: 5th May 1983
Present Address: Apartment Lotus and Lily, 6/05, Behind Rakshaq chowk, Pimple Nilakh, Pune
Permanent Address: 22, RajLaxmi bungalows, Harni Road, Vadodara (GUJ), India.
Permanent Contact No.: +91-9764415616
Languages Known: English, Hindi, Marathi, and German.
Alternate Email ID: amitpatz@gmail.co.in