This document discusses ripple counters, which are asynchronous counters composed of multiple flip-flops connected in a chain so that the output of each flip-flop triggers the next. It describes how ripple counters can count up or down by complementing outputs or inputs. Control logic gates allow a counter to count up or down based on a command. Objectives cover identifying a basic up-counter, modifying it to count down, and adding control logic for up/down counting.

1. Nathaniel J. Lascano
Bsit 201-B Elex

2. Basic Concepts
1. A ripple counter consists of two or more T
flip=flops inter connected so that the
output of each flip-flop is connected to
the T input of the following flip-flop.
2. The ripple counter is also called an
asynchronous counter since the output
states do not change simultaneously
with a common clock.
3. Ripple counters can be made to count up or
down.

3. Basic Concepts
4. The direction of count can be reversed by
complementing the output of each flip-
flop.
5. The direction of count can also be reversed
by complementing the input of each
flip- flop.

4. Introductory Information
Counters fall into two basic groups: serial and
parallel. The serial counter (or asynchronous
counter) is referred to as a ripple counter since
each flip-flop is triggered one at a time, with
the output of one flip-flop to triggered the next
flip-flop. In a parallel counter (synchronous
counter), all the flip-flops are triggered at the
same time. The parallel counter will be
discussed in a later lesson.

5. Introductory Information
Counters may count each operation in one
area and, after a predetermined number of
operations have been performed (counted), it
could initiate another set of operations in a
different area. Another use of counters is to
control the timing of operation sequences. In
this application, it provides control signals
(commands) to different areas of operations at
predetermined intervals (a set numbers of
counts for each operation).

6. Objective A. Identify the basic digital
ripple counter and it's logic function as
an up-counter.
Preparatory Information . A basic 4-bit
ripple counter is shown in Fig. 11-1 (a). Each
flip-flop is connected to operate as a T flip-
flop (all the J and K inputs must connect to
a HI ) . Notice that the Q output of each
flip-flop is connected to the clock input of
the following flip-flop. In this way, each
flip-flop will triggered by the preceding flip-
flop.

7. Fig.11.1 (b) is a timing diagram showing the
Q output of each flip-flop relative to the
input clock. The flip-flops trigger on the
negative edge of their clock pulse in our
example . Hence, flip-flop A does not
change logic states (toggle) until the input
clock goes from HI to LO (negative edge).
Likewise, flip=flop B, C, and D do not toggle
until the negative edge from the preceding
flip-flop occurs.

8. Objective B. Demonstrate how the basic
ripple counter can be made to function as a
down counter.
Preparatory Information. The binary up-
counter of Fig. 11-2 may be change to a binary
down-counter in either of two ways: (1) by
triggering each flip-flop with the Q output but
using the Q outputs to indicate the binary
count (complementing the Q output of each
flip-flop), Fig. 11.3 (a); or (2) by using the Q
outputs to indicate the binary count but
triggering each flip-flop with the Q output
(complementing the input of each flip-flop),
Fig. 11.3 (b).

9. When changing from up-counter to a down-
counter by a method (2), we can leave the Q
outputs connected to the indicators, as in
the up-counter, but connect the Q outputs
to the clock inputs of each flip-flop. This
method can be analyzed in the same
manner as the up counter. Fig 11.4 is a partial
timing diagram of the four flip-flop Q and
Q outputs.

10. Objective C. Demonstrate how a ripple
counter may be made to count up or down
on command by using control logic gates.
Preparatory Information. With the addition
of control logic gates we can have one counter
circuit that will count up or down upon
command. A 4-bit up-down binary counter is
shown in Fig.11.5 Gates A through J control the
up and down count functions. Remember that
the AND gates any LO output and only when
both inputs are LO will the output be HI.

11. Also remember that for NOR gates any HI
produces a LO output and only when both inputs
are LO will the output be HI. The NOR output will
complement the count sequences described in
objective A or B. In other words, when gates A, D
and G are enable by LO at the up/down input, the
Q outputs are inverted by the NOR gate. Therefore
the Q outputs are effectively connected to the
clock inputs causing the counter to count down. A
HI at the up/down input enables gate B, E, and H
and the Q outputs are also inverted by the NOR
gates. Hence, the Q outputs are effectively
connected to the clock inputs causing the counter
to count up.

12. Post-test
1. The counter discussed in this Laboratory
Exercise :
a. A binary counter
b. A ripple counter
c. An asynchronous counter
d. All of the above
2. A ripple counter can be made to count:
a. Up
b. Down
c Up and Down
d. All of the above

13. 3. A five-stage ripple counter provides a
frequency division of:
a. 16 b. 24
c. 32 d. 36
4. If a binary counter consisted of five flip-
flops, what be the maximum decimal count?
a. 15 b. 16
c. 31 d. 32
5. If it is desired to have a binary counter
capable of attaining a maximum count of 63,
how many flip-flops would be required?
a. 4 b. 5
c. 6 d. 7