2.  Synchronous means :
Working or moving at the
same rate
Having the same period
and phase of oscillation
or cyclic movement.

3.  Circuitmeans:
a route around which an
electrical current can
flow, beginning and
ending at the same point.

4. In this chapter we deal with synchronous
counters. From a functional point of view,
synchronous counters implement finite state
machines. However, we use a syntactic definition
and show that every circuit that obeys these
syntactic rules implements a finite state machine.
Correct functionality of a synchronous counters
requires satisfaction of certain timing constraints.
Most importantly, all data inputs of flip-flops must
be stable during the critical sections. A key
advantage of the model (in which the critical
section and the instability interval of each flip-flop
are disjoint) is that it is possible to satisfy all the
timing constraints if the clock period is sufficiently
long.

6. In the canonic form, a synchronous
counter is decomposed into three parts:
(i) the flip-flops store the state,
(ii) a combinational circuit computes the
output, and
(iii) a combinational circuit computes
the next state.
Finally, we deal with the issue of
initialization. Loosely speaking,
initialization of the circuit means that the
ip-ops output correct and stable values
during the rst clock period.

7. 1. combinational gates
2. nets
3. flip-flops

8. A synchronous circuit is a circuit C
composed of combinational gates, nets,
and flip-flops that satisfies the following
conditions:
1. There is a net called clk that carries a clock signal.
2. The clk net is fed by an input gate.
3. The set of ports that are fed by the clk net equals
the set of clock-inputs of the flip-flops.
4. Define the circuit C0 as follows: The circuit C0 is
obtained by (i) deleting the clk net, (ii) deleting the
input gate that feeds the clk net, and (iii) replacing
each flip-flop with an output gate (instead of the
port D) and an input gate (instead of the port Q).
We require that the circuit C0 is combinational.

10. In parallel (synchronous)
counters the input are pulses (or
levels and pulses) with certain
restrictions on pulse width and
circuit propagation delay.
Therefore synchronous circuits
can be divided into
sequential circuits and
or pulsed sequential
circuits.

11. In a sequential circuit
which has flip-flops or, in some
instances, gated latches, for its
memory elements there is
a(synchronizing) periodic clock
connected to the clock inputs of all the
memory elements of the circuit, to
synchronize all internal changes of
state.

13. On the other hand in an
or pulsed sequential
circuit, such a clock is not present.
Pulse mode circuits require two
consecutive transitions between 0 and
1 - that is a 0-pulseor a 1 pulse to
alter the circuit’s state. A pulse -mode
circuit is designed to respond to
pulses of certain duration; the
constant signals between the pulses
are null or spacer signals, which do
not affect the circuit’s behavior.

15. 1) For pulsed
sequential circuits these occur only for
the duration of the respective input pulse
and in some cases for duration
considerably less. For clocked sequential
circuits these outputs occur for the
duration of the clock pulse.
2) These change state
at the start of the respective input or
clock pulse and remain in that state until
the next state of output is required.

16. A synchronous electric motor is
an in which the rotation of
the shaft is synchronized with the
of the supply current;
the rotation period is exactly equal to
an integral number of AC cycles.
Synchronous motors contain
on the of the
motor that create a
which rotates in time with the
oscillations of the line current. The
turns in step with this field, at the
same rate.