1. Counters are sequential circuits that cycle through a sequence of states upon receiving a clock pulse or other input signal. They are used for applications like counting events, generating timing sequences, and addressing memory. 2. There are two main types of counters: asynchronous/ripple counters where each flip-flop is triggered by the previous one, and synchronous counters where all flip-flops are triggered simultaneously by a clock. Asynchronous counters are simpler but slower while synchronous counters are faster but more complex. 3. Binary counters follow a binary sequence and can count from 0 to 2n-1 for an n-bit counter. Other counter types include up/down, ring, Johnson, and decade counters.

1. 1
COUNTERS

2. Counter
• Counter : A sequential circuit that goes through prescribed
sequence of states upon the application of clock pulse is
called a counter.
• The input pulses are called count pulses, may be clock pulses or
they may originate from an external source or occur at
prescribed intervals or at random.
• In a counter the sequence of states may follow binary count or
any other sequence.
• Counters are found in almost all equipment containing digital
system

3. Binary Counter
• Binary Counter : A counter that follows the binary
sequence is called a Binary counter.
• An n-bit Binary Counter consists of n flipflops and
can count in binary from 0 to 2n-1.
• For eg. Binary counter for two digits is as follows:
Present State
A B
Next State
A B
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0

4. Applications of Counters
• Some of the applications of counters in a sequential circuits are
as follows:
T
ocount the number of occurances
Generating Timing sequences
Count up or down
Increment or decrement count
Sequence events
Divide frequency
Address memory
As temporary memory

5. Two principal categories
• Counters are divided in two categories, these are:
–Asynchronous (Ripple) Counters - the first flip-flop is
clocked by the external clock pulse, and then each
successive flip-flop is clocked by the Q or Q' output of
the previous flip-flop.
–Synchronous Counters - all memory elements are
simultaneously triggered by the same clock.

6. Difference between Asynchronous and Synchronous Counter
Sr.
No
.
Key Synchronous Counter Asynchronous Counter
1 Trigger In case of Synchronous Counter, as the name
suggests all the constituent flip flops are
triggered with same clock simultaneously.
In case of Asynchronous Counter there is
triggering of different flip flops with different
clock.
2 Speed As mentioned above in case of Synchronous
Counter all flip flops are triggered altogether
hence operation speed of counter become faster
as compared to that of Asynchronous counter.
Asynchronous Counter operation speed is
comparatively slower than Synchronous
counter.
3 Complexity As all flip flops are being coordinating with the
clock hence the design and implementation is
complex as compared to that of Asynchronous
Counter.
On other hand as output of one flip flop
performing as input of next flip flop the
design and implementation is quite simple in
case of Asynchronous counter.
4 Sequence Synchronous Counter could be operated in any
desired count sequence as it could get
manipulated by changing the clock sequence.
Asynchronous counter could operate only in
fixed count sequence i.e., UP and DOWN.
5 Delay There is no propagation delay observed in case
of Synchronous Counter.
There is a subsequent propagation delay from
one flip flop to another in case of
Asynchronous Counter

7. Few other categories of counters:
• Apart from synchronous and asynchronous
counters which are the major ones the other
types of counters are as follows:
–Ring counter
–Johnson counter
–Decade counter
–Up–down counter

8. Asynchronous Counters
• Here flipflop output transition serves as a source for
triggering other flip flops.
• This means that the clockpulse is provided to a single
flip flop.
• The change of state of a given flip flop is dependent on
the states of other flipflops.
• In other words the flip flops are not triggered by
simultanous clock pulses but the transitions in other flip
flops.
• Propagation delays in an asynchronous (ripple-clocked)
binary counter.

9. Asynchronous counters: the flip-flops do not change states at
exactly the same time as they do not have a common clock
pulse.
Also known as ripple counters, as the input clock pulse “ripples”
through the counter – cumulative delay is a drawback.
n flip-flops  a MOD (modulus) 2n
counter. (Note: A MOD-x
counter cycles through x states.)
Output of the last flip-flop (MSB) divides the input clock
frequency by the MOD number of the counter, hence a counter
is also a frequency divider.
Asynchronous (Ripple) Counters

11. Two-bit asynchronous counter
• Usually, all the CLEAR inputs are connected together, so that a single
pulse can clear all the flip-flops before counting starts.
• The 2-bit ripple counter circuit above has four different states, each
one corresponding to a count value.
• Similarly, a counter with n flip-flops can have 2N states.
• The number of states in a counter is known as its mod(modulo)
number.

14. Up/down Counter
UP/DOWN Counter
Up counter and down counter is combined together to obtain an
UP/DOWN counter. A mode control (M) input is also provided to select
either up or down mode. A combinational circuit is required to be
designed and used between each pair of flip-flop in order to achieve the
up/down operation.
Type of up/down counters-
•UP/DOWN ripple counters
•UP/DOWN synchronous counter

17.  Larger asynchronous (ripple) counter can be constructed by cascading smaller
ripple counters.
 Connect last-stage output of one counter to the clock input of next counter so
as to achieve higher-modulus operation.
 Example: A modulus-32 ripple counter constructed from a modulus-4 counter
and a modulus-8 counter.
Cascading Asynchronous Counters
J J
Q1
Q0
CLK
Q
Q
C C
Q' Q'
K K
J J
Q3
Q2
J
Q4
Q Q
Q
C C C
Q' Q' Q'
K K K
Modulus-4 counter Modulus-8 counter

26. Synchronous (Parallel) Counters
Synchronous (Parallel) Counters
 Example: Synchronous decade/BCD counter
(cont’d).
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0
1 Q1
Q0
CLK
T
C
Q
Q'
Q
Q'
Q2 Q3
T
C
Q
Q'
Q
Q'
T
C
Q
Q'
Q
Q'
T
C
Q
Q'
Q
Q'