Finite-State Machine The document discusses finite-state machines (FSM), which model sequential logic circuits. It describes two types of FSMs: Mealy and Moore machines. Mealy machines output depends on the present state and input, changing asynchronously with the clock. Moore machines' output depends only on the present state, changing synchronously with state changes and clock. The document provides an example of designing an FSM to output 0 if an even number of 1's have been received on the input, and 1 for odd. It shows solutions as both a Mealy and Moore machine using state transition tables and logic diagrams.

1. Finite-State Machine
Muhammad Irfan Anjum
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2. OUTLINE
•
Introduction
•
Types of Finite State Machines
•
•
•
Mealy State Machine
Moore State Machine
Example
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3. Finite State Machine
• FSMs are different from counters in the sense that they
have external I/Ps, and state transitions are dependent on
these I/Ps and the current state.
• Simple forms of pattern matching.
• Models for sequential logic circuits, of the kind on which
every present-day computer and many device controllers is
based.
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4. Mealy and Moore Machines
External I/Ps
External
I/Ps
m1
External O/Ps
m1
Comb.
Logic
n
FFs
m2
Next State
Comb.
Logic
n even
↓
odd
n
Output
Logic
CLK
m2
FFs
n
CLK
External Outputs
Moore Machine Model
Mealy Machine Model
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5. Difference Between Mealy and Moore Machine
Mealy
(1) O/Ps depend on the present
state and present I/Ps
(2) The O/P change asyn
-chronously with the
enabling clock edge
(3)
(4)
Moore
O/Ps depend only on the
present state
Since the O/Ps change
when the state changes,
and the state change is
synchronous with the
enabling clock edge, O/Ps
change synchronously
with this clock edge
A counter is a Moore
machine
A counter is not a Mealy
machine
A Mealy machine will have
the same # or fewer states
than a Moore machine
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6. Finite State Machine (FSM) Design
Example:
There is a one bit-serial I/P line. Design an FSM that outputs a ‘0’ if an
even # of 1’s have been received on the I/P line and the outputs a ‘1’
otherwise.
x
FSM
O/p y
CLK
CLK
x
# of
1s
even
(0)
odd
(1)
even
(2)
odd
(3)
6
odd
(3)

7. Solution 1: (Mealy)
Solution 2: (Moore)
0
0/0
Reset
Even
Transition
Arc
Input
1/1
1/0
Odd
Reset
Output
Even
Output
[0]
O/P is dependent
on current state and
input in Mealy
1
1
Odd
[1]
0
0/1
Mealy Machine: Output is associated
with the state transition, and appears
before the state transition is completed
(by the next clock pulse).
Input
Output is
dependent only
on current state
Moore Machine: Output is associated
with the state and hence appears
after the state transition take place.
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8. State Transition Table
(Even-Parity Checker)
Even State: 0 ;
Present
State
Input
A
Odd State: 1;
Next
State
x
State Variable A
Mealy
O/P
Moore
O/P
A+
y1
D-FF
Excit.
y2
DA
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
1x
1
0
Input variables
to comb. logic
1
1
DA= A⊕x ;
y1 = A for Moore
y2 = A⊕x for Mealy
Output functions 1
1
y2
0
N.S. & O/P
Logic
Q
A FF
x
N.S.
Logic
Or
Q
DA
CLK
8
0
A
O/P
Logic
FFs
y1
DA

9. Moore M/C Implementation
a) D-FF
0
D
x=1
R
CLK
A
Q
y1
Q
Reset
Moore O/P is synchronized with clock.
Mealy M/C Implementation
y2
0
1
D
x=1
CLK
Q
R
A
Q
Reset
a) D-FF
Mealy O/P is not synchronized with clock.
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10. Moore M/C Implementation
a) D-FF
0
D
x=1
R
CLK
A
Q
y1
Q
Reset
Moore O/P is synchronized with clock.
Mealy M/C Implementation
y2
0
1
D
x=1
CLK
Q
R
A
Q
Reset
a) D-FF
Mealy O/P is not synchronized with clock.
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