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Alona Gradman
Alona Gradman
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Managing High Performance Data Pipeline Execution with an FPGA Processor Presenter: Ben Hor – Xilinx, Inc Authors: Glenn Steiner, Dan Isaacs – Xilinx, Inc. David Pellerin – Impulse Accelerated Technologies
Agenda ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
What is Control Plane / Data Plane Processing and Why Might I Need It?
Challenge Example: HD Video Streaming ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Coprocessing: An Effective Way of Accelerating Software ,[object Object],[object Object],[object Object]
A Look at Coprocessing Architectures ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
What is Control Plane / Data Plane Data In Data Out User Interface Processor Bus or Dedicated Control Channel(s) Control Plane Data Plane Control Plane Processor (OS) Coprocessor Coprocessor Coprocessor
Control / Data Plane Example ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Adapted from: Active correlation between the control and data plane – Z. Morley Mao
FPGA’s Enable Computation Balancing Between a Processor and Application Specific Logic
FPGAs: Ideal for Coprocessing ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
External Processor Challenges ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Implementation of A Control Plane / Data Plane System is Straight Forward
Building The Control Plane / Data Plane System ,[object Object],[object Object],[object Object],[object Object],[object Object]
Assemble the Control Plane Processor
 
 
[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Assemble and Connect the Data Plane
CASE STUDY: HD VIDEO RECOGNITION SYSTEM
The Case Study Problem ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The Architected Solution ,[object Object],[object Object]
Base Processor Reference Design Linux Xilinx MicroBlaze Processor Block RAM SystemAce Compact Flash ICC GPIO LEDs GPIO DIP Switch Debug Module UART Multiport Memory Controller DDR2 Memory GPIO Push Buttons Clock Generator Reset Module
DVI Pass-through Reference Design ,[object Object],DVI Input DVI Output Image Processing
DVI Pass-through Reference Design ,[object Object],Image Processing DVI Input DVI Output ,[object Object],[object Object],[object Object],[object Object],System Generator Custom video accelerator pcore
Integrated Control/Data Plane System DVI The processor is used to dynamically configure filters Processor Local Bus (PLB) DVI Filter control (UART) New Pipeline Element DVI In Gamma In Gamma Out DVI Out Xilinx MicroBlaze Processor System 2D FIR Filter Object Detection
HD Object Detection & Highlighting
Connecting the Embedded Processor to the FPGA with Linux
Control the Pipe with Linux ,[object Object],[object Object],[object Object],[object Object],[object Object]
Configure Linux for the IO Device ,[object Object],[object Object],[object Object],[object Object],[object Object]
Controlling the Data Pipe with the Linux Application ,[object Object],[object Object],[object Object],[object Object],[object Object]
SUMMARY ,[object Object],[object Object],[object Object],[object Object]
Thank You Glenn Steiner, Dan Isaacs – Xilinx, Inc. David Pellerin – Impulse Accelerated Technologies

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Xilinx track g

  • 1. Managing High Performance Data Pipeline Execution with an FPGA Processor Presenter: Ben Hor – Xilinx, Inc Authors: Glenn Steiner, Dan Isaacs – Xilinx, Inc. David Pellerin – Impulse Accelerated Technologies
  • 2.
  • 3. What is Control Plane / Data Plane Processing and Why Might I Need It?
  • 4.
  • 5.
  • 6.
  • 7. What is Control Plane / Data Plane Data In Data Out User Interface Processor Bus or Dedicated Control Channel(s) Control Plane Data Plane Control Plane Processor (OS) Coprocessor Coprocessor Coprocessor
  • 8.
  • 9. FPGA’s Enable Computation Balancing Between a Processor and Application Specific Logic
  • 10.
  • 11.
  • 12. Implementation of A Control Plane / Data Plane System is Straight Forward
  • 13.
  • 14. Assemble the Control Plane Processor
  • 15.  
  • 16.  
  • 17.
  • 18. CASE STUDY: HD VIDEO RECOGNITION SYSTEM
  • 19.
  • 20.
  • 21. Base Processor Reference Design Linux Xilinx MicroBlaze Processor Block RAM SystemAce Compact Flash ICC GPIO LEDs GPIO DIP Switch Debug Module UART Multiport Memory Controller DDR2 Memory GPIO Push Buttons Clock Generator Reset Module
  • 22.
  • 23.
  • 24. Integrated Control/Data Plane System DVI The processor is used to dynamically configure filters Processor Local Bus (PLB) DVI Filter control (UART) New Pipeline Element DVI In Gamma In Gamma Out DVI Out Xilinx MicroBlaze Processor System 2D FIR Filter Object Detection
  • 25. HD Object Detection & Highlighting
  • 26. Connecting the Embedded Processor to the FPGA with Linux
  • 27.
  • 28.
  • 29.
  • 30.
  • 31. Thank You Glenn Steiner, Dan Isaacs – Xilinx, Inc. David Pellerin – Impulse Accelerated Technologies

Editor's Notes

  1. Example of a “real-time” non-frame buffer based processing solution. There are several products that require a specialized streaming processing, and this example provide a quick and easy method for the developer to quickly the existing design with their algorithm. The fully integrated HW-CoSim environment enables a faster validation cycle with the hardware in the loop functionality.
  2. DE Gen - Data Enable Generator - Example of a “real-time” non-frame buffer based processing solution. There are several products that require a specialized streaming processing, and this example provide a quick and easy method for the developer to quickly the existing design with their algorithm. The fully integrated HW-CoSim environment enables a faster validation cycle with the hardware in the loop functionality.