SlideShare a Scribd company logo
FPGA Architecture
Submitted by:-
Rohit Dhongde (B-41)
Sushant Burde (B-48)
Swapnil Dondal (B-49)
Vaibhav Deshmukh (B-52)
Presented to
Prof. P. P. Rane
FPGA – Introduction
• Based on the principle of functional
completeness
• FPGA: Functionally complete elements (Logic
Blocks) placed in an interconnect framework
• Interconnection framework comprises of wire
segments and switches; Provide a means to
interconnect logic blocks
• Circuits are partitioned to logic block size,
mapped and routed
FPGA – Abstract
• Two dimensional array of customizable logic
block placed in an interconnect array
• Like PLDs programmable at users site
• Like MPGAs, implements thousands of gates of
logic in a single device
•
• FPGAs offer the benefit of both MPGAs and
PLDs!
Classification OF FPGAS
Island Cellular
SRAM
Programmed Antifuse Programmed
channeled
EPROM
Programmed
Array
FPGA
Structure Of FPGA
Why FPGA?
• Quest for high capacity; Two choices available
• MPGA (Masked Programmable Logic Devices)
• Customized during fabrication
• Low volume expensive
• Prolonged time-to-market and high financial risk
• FPGA (Field Programmable Logic Devices)
• Customized by end user
• Implements multi-level logic function
• Fast time to market and low risk
• FPGA chips handle dense logic and memory
elements offering very high logic capacity
• Uncommitted logic blocks are replicated in an
FPGA with interconnects and I/O blocks
A Fictitious FPGA Architecture
(WithMultiplexerAsFunctionallyCompleteCell)
• Basic building block
Interconnection Framework
• Granularity and interconnection structure has caused a split in
the industry
 FPGA
– Fine grained
– Variable length
interconnect segments
– Timing in general is not
predictable; Timing
extracted after placement
and route
Technology of Programmable Elements
• Vary from vendor to vendor. All share the
common property: configurable in one of the
two positions – ‘ON’ or ‘OFF’
• Can be classified into three categories:
• SRAM based
• Fuse based
• EPROM/EEPROM/flash based
• Desired properties:
• Minimum area consumption
• Low on resistance; high off resistance
• Low parasitic capacitance to the attached wire
• Reliability in volume production
Anti-fuse Programming Technology
• Though implementation differ, all anti-fuse
programming elements share common property
• Uses materials which normally resides in high
impedance state
• But can be fused irreversibly into low impedance
state by applying high voltage
Anti-fuse Programming
Technology
• Very low ON resistance (faster implementation
of circuits)
• Limited size of anti-fuse elements;
interconnects occupy relatively lesser area
• Offset : larger transistors needed for programming
• One time programmable
• Cannot be re-programmed
• (design changes are not possible)
• Retain configuration after power off
Commercially Available
Devices
• Architecture differs from vendor to vendor
• Characterized by
• Structure and content of logic block
• Structure and content of routing resources
• To examine, look at some of available devices
• FPGA: Xilinx (XC4000)
• CPLD: Altera (MAX 5K)
Xilinx FPGAs
• Symmetric Array based; Array
consists of CLBs with LUTs and
D-Flipflops
• N-input LUTs can implement
any n-input boolean function
• Array embedded within the
periphery of IO blocks
• Array elements interleaved with
routing resources (wire
segments, switch matrix and
single connection points)
• Employs SRAM technology
Generic Xilinx Architecture
Altera’s FPGA Layout
Conclusion
 FPGA is a customize IC.It can implement most digital logic. BUT CPU
perform an operation by instructions.FPGA is more powerful
 Xilinx even have some FPGAs with up to two embedded IBM
PowerPC 405 processors on a small "corner" of the FPGA and up to
20 channels 10 Gbps serial ports. PowerPC processors are as the
name indicates very powerful, Apple uses PowerPCs in their
computers.
 FPGA Is Reconfigurable And Strongly Flexible.
 It can operate at very high clock speeds has ability to carry out very
very big and complex process
 The advantage of fpga is parrallel processing . So it is widely used in
high-speed and real-time processing field .

More Related Content

What's hot

FPGA Architecture Presentation
FPGA Architecture PresentationFPGA Architecture Presentation
FPGA Architecture Presentation
omutukuda
 
Fundamentals of FPGA
Fundamentals of FPGAFundamentals of FPGA
Fundamentals of FPGA
velamakuri
 
Fpga
FpgaFpga
What is FPGA?
What is FPGA?What is FPGA?
What is FPGA?
GlobalLogic Ukraine
 
Implementation of Soft-core processor on FPGA (Final Presentation)
Implementation of Soft-core processor on FPGA (Final Presentation)Implementation of Soft-core processor on FPGA (Final Presentation)
Implementation of Soft-core processor on FPGA (Final Presentation)
Deepak Kumar
 
Field programable gate array
Field programable gate arrayField programable gate array
Field programable gate array
Neha Agarwal
 
SoC FPGA Technology
SoC FPGA TechnologySoC FPGA Technology
SoC FPGA Technology
Siraj Muhammad
 
Introduction to FPGAs
Introduction to FPGAsIntroduction to FPGAs
Introduction to FPGAs
Sudhanshu Janwadkar
 
Lecture syn 024.cpld-fpga
Lecture syn 024.cpld-fpgaLecture syn 024.cpld-fpga
Lecture syn 024.cpld-fpga
Srikanth Pasumarthy
 
FPGA In a Nutshell
FPGA In a NutshellFPGA In a Nutshell
FPGA In a Nutshell
Somnath Mazumdar
 
CPLDs
CPLDsCPLDs
Fpga & VHDL
Fpga & VHDLFpga & VHDL
Fpga & VHDL
Francesco De Canio
 
FPGA Introduction
FPGA IntroductionFPGA Introduction
FPGA Introduction
Kamlesh Kumar
 
Programmable logic device (PLD)
Programmable logic device (PLD)Programmable logic device (PLD)
Programmable logic device (PLD)
Sɐɐp ɐɥɯǝp
 
CPLDs
CPLDsCPLDs
Advance hdl design training on xilinx fpga
Advance hdl design training on xilinx fpgaAdvance hdl design training on xilinx fpga
Advance hdl design training on xilinx fpga
demon_2M
 
FPGA_Overview_Ibr_2014
FPGA_Overview_Ibr_2014FPGA_Overview_Ibr_2014
FPGA_Overview_Ibr_2014
Ibrahim Hejab
 
A review on virtex fpga family from xilinx
A review on virtex fpga family from xilinxA review on virtex fpga family from xilinx
A review on virtex fpga family from xilinx
University of Kassel
 
FPGA Overview
FPGA OverviewFPGA Overview
FPGA Overview
MetalMath
 
Field Programmable Gate Array: Building Blocks and Interconnections
Field Programmable Gate Array: Building Blocks and InterconnectionsField Programmable Gate Array: Building Blocks and Interconnections
Field Programmable Gate Array: Building Blocks and Interconnections
Dr. Saravanakumar Umathurai
 

What's hot (20)

FPGA Architecture Presentation
FPGA Architecture PresentationFPGA Architecture Presentation
FPGA Architecture Presentation
 
Fundamentals of FPGA
Fundamentals of FPGAFundamentals of FPGA
Fundamentals of FPGA
 
Fpga
FpgaFpga
Fpga
 
What is FPGA?
What is FPGA?What is FPGA?
What is FPGA?
 
Implementation of Soft-core processor on FPGA (Final Presentation)
Implementation of Soft-core processor on FPGA (Final Presentation)Implementation of Soft-core processor on FPGA (Final Presentation)
Implementation of Soft-core processor on FPGA (Final Presentation)
 
Field programable gate array
Field programable gate arrayField programable gate array
Field programable gate array
 
SoC FPGA Technology
SoC FPGA TechnologySoC FPGA Technology
SoC FPGA Technology
 
Introduction to FPGAs
Introduction to FPGAsIntroduction to FPGAs
Introduction to FPGAs
 
Lecture syn 024.cpld-fpga
Lecture syn 024.cpld-fpgaLecture syn 024.cpld-fpga
Lecture syn 024.cpld-fpga
 
FPGA In a Nutshell
FPGA In a NutshellFPGA In a Nutshell
FPGA In a Nutshell
 
CPLDs
CPLDsCPLDs
CPLDs
 
Fpga & VHDL
Fpga & VHDLFpga & VHDL
Fpga & VHDL
 
FPGA Introduction
FPGA IntroductionFPGA Introduction
FPGA Introduction
 
Programmable logic device (PLD)
Programmable logic device (PLD)Programmable logic device (PLD)
Programmable logic device (PLD)
 
CPLDs
CPLDsCPLDs
CPLDs
 
Advance hdl design training on xilinx fpga
Advance hdl design training on xilinx fpgaAdvance hdl design training on xilinx fpga
Advance hdl design training on xilinx fpga
 
FPGA_Overview_Ibr_2014
FPGA_Overview_Ibr_2014FPGA_Overview_Ibr_2014
FPGA_Overview_Ibr_2014
 
A review on virtex fpga family from xilinx
A review on virtex fpga family from xilinxA review on virtex fpga family from xilinx
A review on virtex fpga family from xilinx
 
FPGA Overview
FPGA OverviewFPGA Overview
FPGA Overview
 
Field Programmable Gate Array: Building Blocks and Interconnections
Field Programmable Gate Array: Building Blocks and InterconnectionsField Programmable Gate Array: Building Blocks and Interconnections
Field Programmable Gate Array: Building Blocks and Interconnections
 

Viewers also liked

FPGA
FPGAFPGA
Learning Convolutional Neural Networks for Graphs
Learning Convolutional Neural Networks for GraphsLearning Convolutional Neural Networks for Graphs
Learning Convolutional Neural Networks for Graphs
Mathias Niepert
 
Neural Networks: Introducton
Neural Networks: IntroductonNeural Networks: Introducton
Neural Networks: Introducton
Mostafa G. M. Mostafa
 
The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)
The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)
The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)
Peter Breuer
 
Design of vga based pong game using fpga
Design  of vga based pong game using fpgaDesign  of vga based pong game using fpga
Design of vga based pong game using fpga
Ramanan Rajaraman
 
Hybrid LUT/Multiplexer FPGA Logic Architectures
Hybrid LUT/Multiplexer FPGA Logic ArchitecturesHybrid LUT/Multiplexer FPGA Logic Architectures
Hybrid LUT/Multiplexer FPGA Logic Architectures
Pvrtechnologies Nellore
 
Batch no.2
Batch no.2Batch no.2
Batch no.2
lodingthepage440
 
Xilinx Cool Runner Architecture
Xilinx Cool Runner ArchitectureXilinx Cool Runner Architecture
Xilinx Cool Runner Architecture
dragonpradeep
 
Cpld
CpldCpld
[DL輪読会]Learning convolutional neural networks for graphs
[DL輪読会]Learning convolutional neural networks for graphs[DL輪読会]Learning convolutional neural networks for graphs
[DL輪読会]Learning convolutional neural networks for graphs
Deep Learning JP
 
programmable_devices_en_02_2014
programmable_devices_en_02_2014programmable_devices_en_02_2014
programmable_devices_en_02_2014
Svetozar Jovanovic
 
Composicion bidimensional (1)
Composicion bidimensional (1)Composicion bidimensional (1)
Composicion bidimensional (1)
joselizz
 
Wondrous Wise Words
Wondrous Wise Words Wondrous Wise Words
Wondrous Wise Words
OH TEIK BIN
 
Sharman 2015 PhD thesis
Sharman 2015 PhD thesisSharman 2015 PhD thesis
Sharman 2015 PhD thesis
Murray Sharman
 
Latihan 1 tata
Latihan 1 tataLatihan 1 tata
Latihan 1 tata
leehuanthoo
 

Viewers also liked (16)

FPGA
FPGAFPGA
FPGA
 
Learning Convolutional Neural Networks for Graphs
Learning Convolutional Neural Networks for GraphsLearning Convolutional Neural Networks for Graphs
Learning Convolutional Neural Networks for Graphs
 
Neural Networks: Introducton
Neural Networks: IntroductonNeural Networks: Introducton
Neural Networks: Introducton
 
The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)
The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)
The mixed-signal modelling language VHDL-AMS and its semantics (ICNACSA 1999)
 
Design of vga based pong game using fpga
Design  of vga based pong game using fpgaDesign  of vga based pong game using fpga
Design of vga based pong game using fpga
 
Hybrid LUT/Multiplexer FPGA Logic Architectures
Hybrid LUT/Multiplexer FPGA Logic ArchitecturesHybrid LUT/Multiplexer FPGA Logic Architectures
Hybrid LUT/Multiplexer FPGA Logic Architectures
 
Batch no.2
Batch no.2Batch no.2
Batch no.2
 
Xilinx Cool Runner Architecture
Xilinx Cool Runner ArchitectureXilinx Cool Runner Architecture
Xilinx Cool Runner Architecture
 
Cpld
CpldCpld
Cpld
 
[DL輪読会]Learning convolutional neural networks for graphs
[DL輪読会]Learning convolutional neural networks for graphs[DL輪読会]Learning convolutional neural networks for graphs
[DL輪読会]Learning convolutional neural networks for graphs
 
programmable_devices_en_02_2014
programmable_devices_en_02_2014programmable_devices_en_02_2014
programmable_devices_en_02_2014
 
Composicion bidimensional (1)
Composicion bidimensional (1)Composicion bidimensional (1)
Composicion bidimensional (1)
 
Wondrous Wise Words
Wondrous Wise Words Wondrous Wise Words
Wondrous Wise Words
 
Rhoades_logo_color
Rhoades_logo_colorRhoades_logo_color
Rhoades_logo_color
 
Sharman 2015 PhD thesis
Sharman 2015 PhD thesisSharman 2015 PhD thesis
Sharman 2015 PhD thesis
 
Latihan 1 tata
Latihan 1 tataLatihan 1 tata
Latihan 1 tata
 

Similar to Fpga optimus main_print

L12_PROGRAMMABLE+LOGIC+DEVICES+(PLD).ppt
L12_PROGRAMMABLE+LOGIC+DEVICES+(PLD).pptL12_PROGRAMMABLE+LOGIC+DEVICES+(PLD).ppt
L12_PROGRAMMABLE+LOGIC+DEVICES+(PLD).ppt
MikeTango5
 
L12 programmable+logic+devices+(pld)
L12 programmable+logic+devices+(pld)L12 programmable+logic+devices+(pld)
L12 programmable+logic+devices+(pld)
NAGASAI547
 
Cpld and fpga mod vi
Cpld and fpga   mod viCpld and fpga   mod vi
Cpld and fpga mod vi
Agi George
 
VLSI design Dr B.jagadeesh UNIT-5.pptx
VLSI design Dr B.jagadeesh   UNIT-5.pptxVLSI design Dr B.jagadeesh   UNIT-5.pptx
VLSI design Dr B.jagadeesh UNIT-5.pptx
jagadeesh276791
 
nios.ppt
nios.pptnios.ppt
nios.ppt
fahad283209
 
FPGA-Arch (3).ppt
FPGA-Arch (3).pptFPGA-Arch (3).ppt
FPGA-Arch (3).ppt
Arthi579360
 
FPGA-Arch.ppt
FPGA-Arch.pptFPGA-Arch.ppt
FPGA-Arch.ppt
gowri R
 
FPGA-Arch.ppt
FPGA-Arch.pptFPGA-Arch.ppt
FPGA-Arch.ppt
gopikahari7
 
FPGA architecture.ppt
FPGA architecture.pptFPGA architecture.ppt
FPGA architecture.ppt
EcAlwinjolly
 
FPGA-Arch.ppt
FPGA-Arch.pptFPGA-Arch.ppt
FPGA-Arch.ppt
KrishnaChaitanya139768
 
FPGA-Arch.ppt
FPGA-Arch.pptFPGA-Arch.ppt
FPGA-Arch.ppt
Priya Tharsini
 
FPGA-Architecture.ppt
FPGA-Architecture.pptFPGA-Architecture.ppt
FPGA-Architecture.ppt
Priya Tharsini
 
Pld dp
Pld dpPld dp
Pld dp
chandkec
 
Dr.D.RUKMANIDEVI PPT.ppt
Dr.D.RUKMANIDEVI PPT.pptDr.D.RUKMANIDEVI PPT.ppt
Dr.D.RUKMANIDEVI PPT.ppt
RMDAcademicCoordinat
 
Technical Seminar.pptx
Technical Seminar.pptxTechnical Seminar.pptx
Technical Seminar.pptx
VaishnaviRavella
 
FPGA Intro
FPGA IntroFPGA Intro
FPGA Intro
naito88
 
Implementation of Soft-core Processor on FPGA
Implementation of Soft-core Processor on FPGAImplementation of Soft-core Processor on FPGA
Implementation of Soft-core Processor on FPGA
Deepak Kumar
 
FPGA.ppt
FPGA.pptFPGA.ppt
FPGA.ppt
EcAlwinjolly
 
Digital Systems Design
Digital Systems DesignDigital Systems Design
Digital Systems Design
Reza Sameni
 
Fpga
FpgaFpga

Similar to Fpga optimus main_print (20)

L12_PROGRAMMABLE+LOGIC+DEVICES+(PLD).ppt
L12_PROGRAMMABLE+LOGIC+DEVICES+(PLD).pptL12_PROGRAMMABLE+LOGIC+DEVICES+(PLD).ppt
L12_PROGRAMMABLE+LOGIC+DEVICES+(PLD).ppt
 
L12 programmable+logic+devices+(pld)
L12 programmable+logic+devices+(pld)L12 programmable+logic+devices+(pld)
L12 programmable+logic+devices+(pld)
 
Cpld and fpga mod vi
Cpld and fpga   mod viCpld and fpga   mod vi
Cpld and fpga mod vi
 
VLSI design Dr B.jagadeesh UNIT-5.pptx
VLSI design Dr B.jagadeesh   UNIT-5.pptxVLSI design Dr B.jagadeesh   UNIT-5.pptx
VLSI design Dr B.jagadeesh UNIT-5.pptx
 
nios.ppt
nios.pptnios.ppt
nios.ppt
 
FPGA-Arch (3).ppt
FPGA-Arch (3).pptFPGA-Arch (3).ppt
FPGA-Arch (3).ppt
 
FPGA-Arch.ppt
FPGA-Arch.pptFPGA-Arch.ppt
FPGA-Arch.ppt
 
FPGA-Arch.ppt
FPGA-Arch.pptFPGA-Arch.ppt
FPGA-Arch.ppt
 
FPGA architecture.ppt
FPGA architecture.pptFPGA architecture.ppt
FPGA architecture.ppt
 
FPGA-Arch.ppt
FPGA-Arch.pptFPGA-Arch.ppt
FPGA-Arch.ppt
 
FPGA-Arch.ppt
FPGA-Arch.pptFPGA-Arch.ppt
FPGA-Arch.ppt
 
FPGA-Architecture.ppt
FPGA-Architecture.pptFPGA-Architecture.ppt
FPGA-Architecture.ppt
 
Pld dp
Pld dpPld dp
Pld dp
 
Dr.D.RUKMANIDEVI PPT.ppt
Dr.D.RUKMANIDEVI PPT.pptDr.D.RUKMANIDEVI PPT.ppt
Dr.D.RUKMANIDEVI PPT.ppt
 
Technical Seminar.pptx
Technical Seminar.pptxTechnical Seminar.pptx
Technical Seminar.pptx
 
FPGA Intro
FPGA IntroFPGA Intro
FPGA Intro
 
Implementation of Soft-core Processor on FPGA
Implementation of Soft-core Processor on FPGAImplementation of Soft-core Processor on FPGA
Implementation of Soft-core Processor on FPGA
 
FPGA.ppt
FPGA.pptFPGA.ppt
FPGA.ppt
 
Digital Systems Design
Digital Systems DesignDigital Systems Design
Digital Systems Design
 
Fpga
FpgaFpga
Fpga
 

More from Sushant Burde

Dsp ppt
Dsp pptDsp ppt
Dsp ppt
Sushant Burde
 
Appp rrrr
Appp rrrrAppp rrrr
Appp rrrr
Sushant Burde
 
Sushantburde
SushantburdeSushantburde
Sushantburde
Sushant Burde
 
Caooooooooooo
CaoooooooooooCaooooooooooo
Caooooooooooo
Sushant Burde
 
Spread spectrum
Spread spectrumSpread spectrum
Spread spectrum
Sushant Burde
 
Sushant memristor
Sushant memristorSushant memristor
Sushant memristor
Sushant Burde
 
Array antennas
Array antennasArray antennas
Array antennas
Sushant Burde
 
PCI & ISA bus
PCI & ISA busPCI & ISA bus
PCI & ISA bus
Sushant Burde
 

More from Sushant Burde (8)

Dsp ppt
Dsp pptDsp ppt
Dsp ppt
 
Appp rrrr
Appp rrrrAppp rrrr
Appp rrrr
 
Sushantburde
SushantburdeSushantburde
Sushantburde
 
Caooooooooooo
CaoooooooooooCaooooooooooo
Caooooooooooo
 
Spread spectrum
Spread spectrumSpread spectrum
Spread spectrum
 
Sushant memristor
Sushant memristorSushant memristor
Sushant memristor
 
Array antennas
Array antennasArray antennas
Array antennas
 
PCI & ISA bus
PCI & ISA busPCI & ISA bus
PCI & ISA bus
 

Recently uploaded

Executive Directors Chat Leveraging AI for Diversity, Equity, and Inclusion
Executive Directors Chat  Leveraging AI for Diversity, Equity, and InclusionExecutive Directors Chat  Leveraging AI for Diversity, Equity, and Inclusion
Executive Directors Chat Leveraging AI for Diversity, Equity, and Inclusion
TechSoup
 
Main Java[All of the Base Concepts}.docx
Main Java[All of the Base Concepts}.docxMain Java[All of the Base Concepts}.docx
Main Java[All of the Base Concepts}.docx
adhitya5119
 
Digital Artefact 1 - Tiny Home Environmental Design
Digital Artefact 1 - Tiny Home Environmental DesignDigital Artefact 1 - Tiny Home Environmental Design
Digital Artefact 1 - Tiny Home Environmental Design
amberjdewit93
 
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdfANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
Priyankaranawat4
 
C1 Rubenstein AP HuG xxxxxxxxxxxxxx.pptx
C1 Rubenstein AP HuG xxxxxxxxxxxxxx.pptxC1 Rubenstein AP HuG xxxxxxxxxxxxxx.pptx
C1 Rubenstein AP HuG xxxxxxxxxxxxxx.pptx
mulvey2
 
clinical examination of hip joint (1).pdf
clinical examination of hip joint (1).pdfclinical examination of hip joint (1).pdf
clinical examination of hip joint (1).pdf
Priyankaranawat4
 
Liberal Approach to the Study of Indian Politics.pdf
Liberal Approach to the Study of Indian Politics.pdfLiberal Approach to the Study of Indian Politics.pdf
Liberal Approach to the Study of Indian Politics.pdf
WaniBasim
 
Film vocab for eal 3 students: Australia the movie
Film vocab for eal 3 students: Australia the movieFilm vocab for eal 3 students: Australia the movie
Film vocab for eal 3 students: Australia the movie
Nicholas Montgomery
 
Introduction to AI for Nonprofits with Tapp Network
Introduction to AI for Nonprofits with Tapp NetworkIntroduction to AI for Nonprofits with Tapp Network
Introduction to AI for Nonprofits with Tapp Network
TechSoup
 
The basics of sentences session 5pptx.pptx
The basics of sentences session 5pptx.pptxThe basics of sentences session 5pptx.pptx
The basics of sentences session 5pptx.pptx
heathfieldcps1
 
How to Build a Module in Odoo 17 Using the Scaffold Method
How to Build a Module in Odoo 17 Using the Scaffold MethodHow to Build a Module in Odoo 17 Using the Scaffold Method
How to Build a Module in Odoo 17 Using the Scaffold Method
Celine George
 
বাংলাদেশ অর্থনৈতিক সমীক্ষা (Economic Review) ২০২৪ UJS App.pdf
বাংলাদেশ অর্থনৈতিক সমীক্ষা (Economic Review) ২০২৪ UJS App.pdfবাংলাদেশ অর্থনৈতিক সমীক্ষা (Economic Review) ২০২৪ UJS App.pdf
বাংলাদেশ অর্থনৈতিক সমীক্ষা (Economic Review) ২০২৪ UJS App.pdf
eBook.com.bd (প্রয়োজনীয় বাংলা বই)
 
Top five deadliest dog breeds in America
Top five deadliest dog breeds in AmericaTop five deadliest dog breeds in America
Top five deadliest dog breeds in America
Bisnar Chase Personal Injury Attorneys
 
World environment day ppt For 5 June 2024
World environment day ppt For 5 June 2024World environment day ppt For 5 June 2024
World environment day ppt For 5 June 2024
ak6969907
 
MARY JANE WILSON, A “BOA MÃE” .
MARY JANE WILSON, A “BOA MÃE”           .MARY JANE WILSON, A “BOA MÃE”           .
MARY JANE WILSON, A “BOA MÃE” .
Colégio Santa Teresinha
 
How to Fix the Import Error in the Odoo 17
How to Fix the Import Error in the Odoo 17How to Fix the Import Error in the Odoo 17
How to Fix the Import Error in the Odoo 17
Celine George
 
Lapbook sobre os Regimes Totalitários.pdf
Lapbook sobre os Regimes Totalitários.pdfLapbook sobre os Regimes Totalitários.pdf
Lapbook sobre os Regimes Totalitários.pdf
Jean Carlos Nunes Paixão
 
Life upper-Intermediate B2 Workbook for student
Life upper-Intermediate B2 Workbook for studentLife upper-Intermediate B2 Workbook for student
Life upper-Intermediate B2 Workbook for student
NgcHiNguyn25
 
Pride Month Slides 2024 David Douglas School District
Pride Month Slides 2024 David Douglas School DistrictPride Month Slides 2024 David Douglas School District
Pride Month Slides 2024 David Douglas School District
David Douglas School District
 
The basics of sentences session 6pptx.pptx
The basics of sentences session 6pptx.pptxThe basics of sentences session 6pptx.pptx
The basics of sentences session 6pptx.pptx
heathfieldcps1
 

Recently uploaded (20)

Executive Directors Chat Leveraging AI for Diversity, Equity, and Inclusion
Executive Directors Chat  Leveraging AI for Diversity, Equity, and InclusionExecutive Directors Chat  Leveraging AI for Diversity, Equity, and Inclusion
Executive Directors Chat Leveraging AI for Diversity, Equity, and Inclusion
 
Main Java[All of the Base Concepts}.docx
Main Java[All of the Base Concepts}.docxMain Java[All of the Base Concepts}.docx
Main Java[All of the Base Concepts}.docx
 
Digital Artefact 1 - Tiny Home Environmental Design
Digital Artefact 1 - Tiny Home Environmental DesignDigital Artefact 1 - Tiny Home Environmental Design
Digital Artefact 1 - Tiny Home Environmental Design
 
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdfANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
ANATOMY AND BIOMECHANICS OF HIP JOINT.pdf
 
C1 Rubenstein AP HuG xxxxxxxxxxxxxx.pptx
C1 Rubenstein AP HuG xxxxxxxxxxxxxx.pptxC1 Rubenstein AP HuG xxxxxxxxxxxxxx.pptx
C1 Rubenstein AP HuG xxxxxxxxxxxxxx.pptx
 
clinical examination of hip joint (1).pdf
clinical examination of hip joint (1).pdfclinical examination of hip joint (1).pdf
clinical examination of hip joint (1).pdf
 
Liberal Approach to the Study of Indian Politics.pdf
Liberal Approach to the Study of Indian Politics.pdfLiberal Approach to the Study of Indian Politics.pdf
Liberal Approach to the Study of Indian Politics.pdf
 
Film vocab for eal 3 students: Australia the movie
Film vocab for eal 3 students: Australia the movieFilm vocab for eal 3 students: Australia the movie
Film vocab for eal 3 students: Australia the movie
 
Introduction to AI for Nonprofits with Tapp Network
Introduction to AI for Nonprofits with Tapp NetworkIntroduction to AI for Nonprofits with Tapp Network
Introduction to AI for Nonprofits with Tapp Network
 
The basics of sentences session 5pptx.pptx
The basics of sentences session 5pptx.pptxThe basics of sentences session 5pptx.pptx
The basics of sentences session 5pptx.pptx
 
How to Build a Module in Odoo 17 Using the Scaffold Method
How to Build a Module in Odoo 17 Using the Scaffold MethodHow to Build a Module in Odoo 17 Using the Scaffold Method
How to Build a Module in Odoo 17 Using the Scaffold Method
 
বাংলাদেশ অর্থনৈতিক সমীক্ষা (Economic Review) ২০২৪ UJS App.pdf
বাংলাদেশ অর্থনৈতিক সমীক্ষা (Economic Review) ২০২৪ UJS App.pdfবাংলাদেশ অর্থনৈতিক সমীক্ষা (Economic Review) ২০২৪ UJS App.pdf
বাংলাদেশ অর্থনৈতিক সমীক্ষা (Economic Review) ২০২৪ UJS App.pdf
 
Top five deadliest dog breeds in America
Top five deadliest dog breeds in AmericaTop five deadliest dog breeds in America
Top five deadliest dog breeds in America
 
World environment day ppt For 5 June 2024
World environment day ppt For 5 June 2024World environment day ppt For 5 June 2024
World environment day ppt For 5 June 2024
 
MARY JANE WILSON, A “BOA MÃE” .
MARY JANE WILSON, A “BOA MÃE”           .MARY JANE WILSON, A “BOA MÃE”           .
MARY JANE WILSON, A “BOA MÃE” .
 
How to Fix the Import Error in the Odoo 17
How to Fix the Import Error in the Odoo 17How to Fix the Import Error in the Odoo 17
How to Fix the Import Error in the Odoo 17
 
Lapbook sobre os Regimes Totalitários.pdf
Lapbook sobre os Regimes Totalitários.pdfLapbook sobre os Regimes Totalitários.pdf
Lapbook sobre os Regimes Totalitários.pdf
 
Life upper-Intermediate B2 Workbook for student
Life upper-Intermediate B2 Workbook for studentLife upper-Intermediate B2 Workbook for student
Life upper-Intermediate B2 Workbook for student
 
Pride Month Slides 2024 David Douglas School District
Pride Month Slides 2024 David Douglas School DistrictPride Month Slides 2024 David Douglas School District
Pride Month Slides 2024 David Douglas School District
 
The basics of sentences session 6pptx.pptx
The basics of sentences session 6pptx.pptxThe basics of sentences session 6pptx.pptx
The basics of sentences session 6pptx.pptx
 

Fpga optimus main_print

  • 1. FPGA Architecture Submitted by:- Rohit Dhongde (B-41) Sushant Burde (B-48) Swapnil Dondal (B-49) Vaibhav Deshmukh (B-52) Presented to Prof. P. P. Rane
  • 2. FPGA – Introduction • Based on the principle of functional completeness • FPGA: Functionally complete elements (Logic Blocks) placed in an interconnect framework • Interconnection framework comprises of wire segments and switches; Provide a means to interconnect logic blocks • Circuits are partitioned to logic block size, mapped and routed
  • 3. FPGA – Abstract • Two dimensional array of customizable logic block placed in an interconnect array • Like PLDs programmable at users site • Like MPGAs, implements thousands of gates of logic in a single device • • FPGAs offer the benefit of both MPGAs and PLDs!
  • 4. Classification OF FPGAS Island Cellular SRAM Programmed Antifuse Programmed channeled EPROM Programmed Array FPGA
  • 6. Why FPGA? • Quest for high capacity; Two choices available • MPGA (Masked Programmable Logic Devices) • Customized during fabrication • Low volume expensive • Prolonged time-to-market and high financial risk • FPGA (Field Programmable Logic Devices) • Customized by end user • Implements multi-level logic function • Fast time to market and low risk
  • 7. • FPGA chips handle dense logic and memory elements offering very high logic capacity • Uncommitted logic blocks are replicated in an FPGA with interconnects and I/O blocks
  • 8. A Fictitious FPGA Architecture (WithMultiplexerAsFunctionallyCompleteCell) • Basic building block
  • 9. Interconnection Framework • Granularity and interconnection structure has caused a split in the industry  FPGA – Fine grained – Variable length interconnect segments – Timing in general is not predictable; Timing extracted after placement and route
  • 10. Technology of Programmable Elements • Vary from vendor to vendor. All share the common property: configurable in one of the two positions – ‘ON’ or ‘OFF’ • Can be classified into three categories: • SRAM based • Fuse based • EPROM/EEPROM/flash based • Desired properties: • Minimum area consumption • Low on resistance; high off resistance • Low parasitic capacitance to the attached wire • Reliability in volume production
  • 11. Anti-fuse Programming Technology • Though implementation differ, all anti-fuse programming elements share common property • Uses materials which normally resides in high impedance state • But can be fused irreversibly into low impedance state by applying high voltage
  • 12. Anti-fuse Programming Technology • Very low ON resistance (faster implementation of circuits) • Limited size of anti-fuse elements; interconnects occupy relatively lesser area • Offset : larger transistors needed for programming • One time programmable • Cannot be re-programmed • (design changes are not possible) • Retain configuration after power off
  • 13. Commercially Available Devices • Architecture differs from vendor to vendor • Characterized by • Structure and content of logic block • Structure and content of routing resources • To examine, look at some of available devices • FPGA: Xilinx (XC4000) • CPLD: Altera (MAX 5K)
  • 14. Xilinx FPGAs • Symmetric Array based; Array consists of CLBs with LUTs and D-Flipflops • N-input LUTs can implement any n-input boolean function • Array embedded within the periphery of IO blocks • Array elements interleaved with routing resources (wire segments, switch matrix and single connection points) • Employs SRAM technology Generic Xilinx Architecture
  • 16. Conclusion  FPGA is a customize IC.It can implement most digital logic. BUT CPU perform an operation by instructions.FPGA is more powerful  Xilinx even have some FPGAs with up to two embedded IBM PowerPC 405 processors on a small "corner" of the FPGA and up to 20 channels 10 Gbps serial ports. PowerPC processors are as the name indicates very powerful, Apple uses PowerPCs in their computers.  FPGA Is Reconfigurable And Strongly Flexible.  It can operate at very high clock speeds has ability to carry out very very big and complex process  The advantage of fpga is parrallel processing . So it is widely used in high-speed and real-time processing field .