The document discusses various biasing configurations for field-effect transistors (FETs) including MOSFETs and JFETs. It provides examples of fixed bias, self bias, voltage divider bias, and feedback bias configurations. It also covers the differences between n-channel and p-channel devices as well as enhancement-type and depletion-type MOSFETs. Key aspects like the non-linear relationship between drain current and gate-source voltage, bias lines, load lines, capacitors, and transfer curves are examined.

1. FET BIASING
The Relationship of ID and VGS is Non-Linear.

2. Field-Effect Transistor
MOSFET
n-Channel
p-Channel
JFET
DMOSFET EMOSFET
n-Channel
p-Channel
n-Channel
p-Channel

5. p. 450
Summary
JFET Configuration

6. Summary
MOSFET
Configuration
p. 450

7. General Relationships
EMOSFET & EMESFET
JFET & DMOSFET &
DMESFET

8. Fixed-Bias Configuration

9. Fixed Bias Configuration
Shockley’s Equation
Fixed DC Supply Capacitor

10. Fixed Bias Configuration
Solution:

11. Graphical Approach
Solution:
Given Q-point
Output

12. Self-Bias Configuration

13. Self Bias Configuration
Capacitor
Shockley’s Equation Ouput

14. Self Bias Configuration
Solution:
Quadratic Equation
Bias Line
Gate to Source Voltage
IDS VGS
0mA 0V
4mA 4V
8mA 8V
��
2
+
2������−��
��
2������
2
��
2
�� +
��
2
��
2
= 0

15. Self Bias Configuration
Solution:
Quadratic Equation
Bias Line
Gate to Source Voltage
IDS VGS
0mA 0V
4mA 4V
8mA 8V
��
2
+
2������−��
��
2������
2
��
2
�� +
��
2
��
2
= 0

16. Self Bias Configuration
Solution:
Given Q-point
Output

17. Voltalge-Divider Bias Configuration

18. Voltage-Divider Bias Configuration
Capacitor

19. Voltage-Divider Bias Configuration
Bias Line

20. Voltage-Divider Configuration
Solution:
Load Line

21. Voltage-Divider Configuration
Solution:
Capacitor

22. Common Gate Bias Configuration

23. Common Gate Bias Configuration
Load Line
Capacitor

24. Common Gate Bias Configuration
Bias Line
Input
Output

25. Common Gate Configuration
Solution:
Transfer Curve

26. Common Gate Configuration
Solution:
Capacitor

27. JFET (RD = 0Ω) Bias Configuration

28. Special Case (VGSQ = 0 V) Bias Configuration

29. Special Case Bias Configuration
Input
Output

30. Summary
MOSFET
Configuration
p. 450

31. a
Depletion-Type MOSFETs
Positive Values for VGS
ID exceeds IDSS

32. DMOSFET - Fixed-Bias Configuration

33. DMOSFET - Voltage-Divider Bias Configuration

34. DMOSFET - Voltage-Divider Configuration
Bias Line
Capacitor

35. DMOSFET - Voltage-Divider Configuration

36. DMOSFET - Self Bias Configuration
ID exceeds IDSS
Transfer Curve
Bias Line
Capacitor

37. a
Enhancement-Type MOSFETs

38. 4 Coordinates
(VGS, ID)
1. (VTH, 0)
2. (VGSon, IDon)
3. (VGS1, ID1)
• VTH < VGS1 < VGSon
4. (VGS2, ID2)
• VGS2 > VGSon
Enhancement-Type
MOSFETs

39. EMOSFET - Feedback Bias Configuration

40. EMOSFET - Feedback Biasing Arrangement
Load Line
Input and Output
Capacitor

41. EMOSFET - Feedback Biasing Arrangement
Solution:
Identify k
(VGS, ID)
(VTH, 0)
(VGSon, IDon)
(VGS1, ID1)
VTH < VGS1 < VGSon
(VGS2, ID2)
VGS2 > VGSon
(VGS, ID)
(3, 0)
(8, 6)
(VGS1, ID1)
VTH < VGS1 < VGSon
(VGS2, ID2)
VGS2 > VGSon
Capacitor

42. EMOSFET - Feedback Biasing Arrangement
Solution:
Plotting the Transfer Curve
(VGS, ID)
(VTH, 0)
(VGSon, IDon)
(VGS1, ID1)
VTH < VGS1 < VGSon
(VGS2, ID2)
VGS2 > VGSon
(VGS, ID)
(3, 0)
(8, 6)
(6, 2.16)
VTH < VGS1 < VGSon
(10, 11.76)
VGS2 > VGSon

43. EMOSFET - Feedback Biasing Arrangement
Solution:
Bias Line

44. EMOSFET - Voltage-Divider Bias Configuration

45. EMOSFET - Voltage-Divider Arrangement
Input
Output

46. EMOSFET - Voltage-Divider Arrangement
Solution:
Plotting the Device
(VGS, ID)
(VTH, 0)
(VGSon, IDon)
(VGS1, ID1)
VTH < VGS1 < VGSon
(VGS2, ID2)
VGS2 > VGSon
(VGS, ID)
(5, 0)
(10, 3)
(VGS1, ID1)
VTH < VGS1 < VGSon
(VGS2, ID2)
VGS2 > VGSon
Plotting the Transfer Curve

47. EMOSFET - Voltage-Divider Arrangement
Identify k (VGS, ID)
(5, 0)
(10, 3)
(8, ID1)
VTH < VGS1 < VGSon
(20, ID2)
VGS2 > VGSon
Line Line
(5, 0)
(10, 3) ID2=27mA
ID1=1.80mA

48. a
p-CHANNEL FETS
Mirror Image of the Transfer Curves
Current Directions are reversed

49. p-Channel FETS

50. p-Channel
Bias Line