The document describes the implementation of a high-speed and power-efficient reliable multiplier using an adaptive hold technique (AHT). Traditional multipliers experience performance degradation over time due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) effects. The proposed design uses an AHT circuit with a column-bypassing or row-bypassing multiplier, Razor flip-flops, and other components to reduce delays, power consumption, and eliminate timing violations caused by aging effects. Simulation results show the AHT multipliers have significantly lower delay and power compared to traditional array, row-bypassing, and column-bypassing multipliers for both 16-bit and 32-bit designs.
AN ULTRA-LOW POWER ROBUST KOGGESTONE ADDER AT SUB-THRESHOLD VOLTAGES FOR IMPL...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for
ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power
circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold
region minimize the energy per operation, thus providing a better platform for energy
constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust
Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages
which can be used for low power implantable bio-medical devices such as pacemakers. To improve the
performance of these adders in sub-threshold region, forward body bias technique and multi-threshold
transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the
simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is
performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for
temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using
0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing
technique shows an effective improvement compared to high threshold voltage and multi threshold voltage
techniques. The forward biasing technique maintains a balance between delay reduction and increase in
average power, thus reducing the power delay product when compared to the other two techniques.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
Performance analysis of cmos comparator and cntfet comparator designeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
AN ULTRA-LOW POWER ROBUST KOGGESTONE ADDER AT SUB-THRESHOLD VOLTAGES FOR IMPL...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for
ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power
circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold
region minimize the energy per operation, thus providing a better platform for energy
constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust
Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages
which can be used for low power implantable bio-medical devices such as pacemakers. To improve the
performance of these adders in sub-threshold region, forward body bias technique and multi-threshold
transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the
simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is
performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for
temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using
0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing
technique shows an effective improvement compared to high threshold voltage and multi threshold voltage
techniques. The forward biasing technique maintains a balance between delay reduction and increase in
average power, thus reducing the power delay product when compared to the other two techniques.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
Performance analysis of cmos comparator and cntfet comparator designeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
An Optimized Device Sizing of Two-Stage CMOS OP-AMP Using Multi-Objective Gen...ijcisjournal
A novel approach for optimizing the transistor dimensions of two stage CMOS op-amp using MultiObjective
Genetic Algorithm (MOGA) is presented. The proposed approach is used to find the optimal
dimensions of each transistor to improve op-amp performances for analog and mixed signal integrated
circuit design. The aim is to automatically determine the device sizes to meet the given performance
specifications while minimizing the cost function such as power dissipation and a weighted sum of the
active area. This strongly suggests that the approach is capable of determining the globally optimal
solutions to the problem. Exactness of performance prediction in the device sizing program (implemented
in MATLAB) maintained. Here Six parameters are considered i.e., open loop gain, Phase Margin (PM),
Area (A), Bandwidth of unity Gain (UGB), Power Consumption (P) and Slew Rate (SR). The circuit is
simulated in cadence(Virtuoso Spectre) 0.18um CMOS technology.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Na...IOSR Journals
Abstract: Power and delay optimization is a very crucial issue in low voltage applications. In this paper, we present a design of Full Adder circuit using AVL techniques for low power operation. The approach for the design is based on XOR/XNOR & Transmission gate for single bit as hybrid design .By using this approach Full Adder is being designed using 12 transistors. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which supply potential is increased. The main aim of the design is to investigate the power, Propagation Delay and Power delay Product for low voltage Full Adder for the proposed design style. The simulation results show that there is a significant reduction in power consumption for this proposed cell with the AVL technique. The circuit is designed using 65 nanometer CMOS technology and simulated using MicroWind and DSCH Ver. 3.1 Keywords: Full Adder, AVL Techniques, Low Power, VLSI, High Performance
Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
This paper investigates about the possibility to reduce power consumption in Neural Network using approximated computing techniques. Authors compare a traditional fixed-point neuron with an approximated neuron composed of approximated multipliers and adder. Experiments show that in the proposed case of study (a wine classifier) the approximated neuron allows to save up to the 43% of the area, a power consumption saving of 35% and an improvement in the maximum clock frequency of 20%.
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption u...iosrjce
In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
We present this work by two steps. In the first one, the new structure proposed of the FP-HEMTs device (Field plate High Electron Mobility Transistor) with a T-gate on an 4H-SIC substrate to optimize these electrical performances, multiple field-plates were used with aluminum oxide to split the single electric field peak into several smaller peaks, and as passivation works to reduce scaling leakage current. In the next, we include a modeling of a simulation in the Tcad-Silvaco Software for realizing the study of the influence of negative voltage applied to gate T-shaped in OFF state time and high power with ambient temperature, the performance differences between the 3FP and the SFP devices are discussed in detail.
Conducted EMI Reduction Accomplished via IEEE 1588 PTP for Grid Connected Par...idescitation
This paper introduces a distributed approach for
interleaving paralleled power converter to reduce EMI and
voltage ripple, accomplished via IEEE 1588 Precision time
protocol. An open source software stack of IEEE 1588v2 named
PTPd-2.2.0 is used to implement software stack over stellaris
series microcontroller from Texas Instruments (TI). A general
methodology for achieving distributed interleaving is proposed,
along with a specific software based implementation approach
using the PTPdv2. The effectiveness of such methods in terms
of EMI reduction is experimentally validated in grid connected
Paralleled Solar Power Inverters.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Adiabatic Logic Based Low Power Carry Select Adder for future TechnologiesIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation of XOR Based Pad Generation Mutual Authentication Protocol for...IOSR Journals
In RF link, without security the messages exchange between the two devices are monitoring by an
eavesdropper. So the exclusive-OR (XOR) based pad generation protocol is used to safely transfer the data to
the other point with necessary security and it maintaining confidentiality. This protocol produce the cover
coding pad to mask the access password before the datas are transmitted. A specially designed pad generation
will be implemented in digital domain to solve the insecurity problem in data communication RF link. This
protocol developed under regulation of ISO 18000 – 6 type C protocol also known as EPC C1G2 RFID
protocol. The linear feed back shift register (LFSR) generate the pseudo random binary sequence (PRBS) and it
is used as data source to the pad generation function. The Xilinx 13.x software is used for synthesize and
modelsim SE6.0 is used for simulating the result. The pad generation algorithm has been implemented in FPGA
Spartan 3 PQ208-4 board to verify the result
An Optimized Device Sizing of Two-Stage CMOS OP-AMP Using Multi-Objective Gen...ijcisjournal
A novel approach for optimizing the transistor dimensions of two stage CMOS op-amp using MultiObjective
Genetic Algorithm (MOGA) is presented. The proposed approach is used to find the optimal
dimensions of each transistor to improve op-amp performances for analog and mixed signal integrated
circuit design. The aim is to automatically determine the device sizes to meet the given performance
specifications while minimizing the cost function such as power dissipation and a weighted sum of the
active area. This strongly suggests that the approach is capable of determining the globally optimal
solutions to the problem. Exactness of performance prediction in the device sizing program (implemented
in MATLAB) maintained. Here Six parameters are considered i.e., open loop gain, Phase Margin (PM),
Area (A), Bandwidth of unity Gain (UGB), Power Consumption (P) and Slew Rate (SR). The circuit is
simulated in cadence(Virtuoso Spectre) 0.18um CMOS technology.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Na...IOSR Journals
Abstract: Power and delay optimization is a very crucial issue in low voltage applications. In this paper, we present a design of Full Adder circuit using AVL techniques for low power operation. The approach for the design is based on XOR/XNOR & Transmission gate for single bit as hybrid design .By using this approach Full Adder is being designed using 12 transistors. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which supply potential is increased. The main aim of the design is to investigate the power, Propagation Delay and Power delay Product for low voltage Full Adder for the proposed design style. The simulation results show that there is a significant reduction in power consumption for this proposed cell with the AVL technique. The circuit is designed using 65 nanometer CMOS technology and simulated using MicroWind and DSCH Ver. 3.1 Keywords: Full Adder, AVL Techniques, Low Power, VLSI, High Performance
Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
This paper investigates about the possibility to reduce power consumption in Neural Network using approximated computing techniques. Authors compare a traditional fixed-point neuron with an approximated neuron composed of approximated multipliers and adder. Experiments show that in the proposed case of study (a wine classifier) the approximated neuron allows to save up to the 43% of the area, a power consumption saving of 35% and an improvement in the maximum clock frequency of 20%.
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption u...iosrjce
In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
We present this work by two steps. In the first one, the new structure proposed of the FP-HEMTs device (Field plate High Electron Mobility Transistor) with a T-gate on an 4H-SIC substrate to optimize these electrical performances, multiple field-plates were used with aluminum oxide to split the single electric field peak into several smaller peaks, and as passivation works to reduce scaling leakage current. In the next, we include a modeling of a simulation in the Tcad-Silvaco Software for realizing the study of the influence of negative voltage applied to gate T-shaped in OFF state time and high power with ambient temperature, the performance differences between the 3FP and the SFP devices are discussed in detail.
Conducted EMI Reduction Accomplished via IEEE 1588 PTP for Grid Connected Par...idescitation
This paper introduces a distributed approach for
interleaving paralleled power converter to reduce EMI and
voltage ripple, accomplished via IEEE 1588 Precision time
protocol. An open source software stack of IEEE 1588v2 named
PTPd-2.2.0 is used to implement software stack over stellaris
series microcontroller from Texas Instruments (TI). A general
methodology for achieving distributed interleaving is proposed,
along with a specific software based implementation approach
using the PTPdv2. The effectiveness of such methods in terms
of EMI reduction is experimentally validated in grid connected
Paralleled Solar Power Inverters.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Adiabatic Logic Based Low Power Carry Select Adder for future TechnologiesIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation of XOR Based Pad Generation Mutual Authentication Protocol for...IOSR Journals
In RF link, without security the messages exchange between the two devices are monitoring by an
eavesdropper. So the exclusive-OR (XOR) based pad generation protocol is used to safely transfer the data to
the other point with necessary security and it maintaining confidentiality. This protocol produce the cover
coding pad to mask the access password before the datas are transmitted. A specially designed pad generation
will be implemented in digital domain to solve the insecurity problem in data communication RF link. This
protocol developed under regulation of ISO 18000 – 6 type C protocol also known as EPC C1G2 RFID
protocol. The linear feed back shift register (LFSR) generate the pseudo random binary sequence (PRBS) and it
is used as data source to the pad generation function. The Xilinx 13.x software is used for synthesize and
modelsim SE6.0 is used for simulating the result. The pad generation algorithm has been implemented in FPGA
Spartan 3 PQ208-4 board to verify the result
Encephalization – An Evolutionary Predisposition to Diabetes: A “Large Brain ...IOSR Journals
Primates have proportionately three times larger brain as compared to that of other mammals of comparable size and humans, in turn, have three times larger brain as compared to that of all other primates of similar size. So we need to meet higher energy demands because brain is energetically expensive. This has a significant impact on our dietary patterns in addition to shaping of our body composition. Here we propose that our dietary patterns to meet our higher energy demands have been ultimately set by the instinct of higher energy intake and our larger brains have a stress effect on our metabolic organs (organs involved in energy metabolism like gut, liver, pancreas etc.). We discuss these two points from evolutionary (Evolutionary instinct) and physiological (Metabolic stress) point of view and argue that these two points explain the manifestation of diabetes primarily as a human disease and enhance our understanding of its mechanism.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high performance multipliers. In this paper, we propose an aging-aware multiplier design with novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed architecture with 16 ×16 and 32 ×32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement, respectively, compared with 16×16 and 32×32 fixed-latency column-bypassing multipliers. Furthermore, our proposed architecture with 16 × 16 and 32 × 32 row-bypassing multipliers can achieve up to 80.17% and 69.40% performance improvement as compared with 16×16 and 32 × 32 fixed-latency row-bypassing multipliers.
Digital world multipliers are the most critical arithmetic functional units. The overall
performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias
temperature instability effect occurs when a pMOS transistor is under negative bias increasing the
threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive
bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade
transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is
important to design reliable high-performance multipliers. In this paper, we propose an aging-aware
multiplier design with a razor based multiplier circuit. The multiplier is able to provide higher throughput
through the variable latency and can adjust the razor flip flop circuit to mitigate performance degradation
that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or rowbypassing multiplier. The experimental results show that our proposed architecture with 16 × 16 and 32 ×
32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement,
respectively, compared with 16×16 and 32×32 fixed-latency column-bypassing multipliers. Furthermore,
our proposed architecture with 16 × 16 and 32 × 32 row-bypassing multipliers can achieve up to 80.17%
and 69.40% performance improvement as compared with 16× 16 and 32 × 32 fixed-latency row-bypassing
multipliers.
An Ultra-Low Power Robust Koggestone Adder at Sub-Threshold Voltages for Impl...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold region minimize the energy per operation, thus providing a better platform for energy constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages which can be used for low power implantable bio-medical devices such as pacemakers. To improve the performance of these adders in sub-threshold region, forward body bias technique and multi-threshold transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using 0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing technique shows an effective improvement compared to high threshold voltage and multi threshold voltage techniques. The forward biasing technique maintains a balance between delay reduction and increase in average power, thus reducing the power delay product when compared to the other two techniques.
GENERIC SYSTEM VERILOG UNIVERSAL VERIFICATION METHODOLOGY BASED REUSABLE VERI...VLSICS Design
In this paper, we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient verification of Image Signal Processing IP’s/SoC’s. With the tight schedules on all projects it is important to have a strong verification methodology which contributes to First Silicon Success. Deploy methodologies which enforce full functional coverage and verification of corner cases through pseudo random test scenarios is required. Also, standardization of verification flow is needed. Previously, inside imaging group of ST, Specman (e)/Verilog based Verification Environment for IP/Subsystem level verification and C/C++/Verilog based Directed Verification Environment for SoC Level Verification was used for Functional Verification. Different Verification Environments were used at IP
level and SoC level. Different Verification/Validation Methodologies were used for SoC Verification across multiple sites. Verification teams were also looking for the ways how to catch bugs early in the design cycle? Thus, Generic System Verilog Universal Verification Methodology (UVM) based Reusable Verification Environment is required to avoid the problem of having so many methodologies and provides a standard unified solution which compiles on all tools.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
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International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
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UiPath Test Automation using UiPath Test Suite series, part 5
F010632733
1. IOSR Journal of Electronics and Communication Engineering (IOSR-JECE)
e-ISSN: 2278-2834,p- ISSN: 2278-8735.Volume 10, Issue 6, Ver. III (Nov - Dec .2015), PP 27-33
www.iosrjournals.org
DOI: 10.9790/2834-10632733 www.iosrjournals.org 27 | Page
Implementation of a High Speed and Power Efficient Reliable
Multiplier Using Adaptive Hold Technique
Padala.Abhishek.T.S.1
, Dr. Shaik.Mastan Vali, M.E, Ph.D2
1
M.Tech.Student, Department of ECE, MVGR College of Engineering, Vizianagaram, India.
2
Professor, Department of ECE, MVGR College of Engineering, Vizianagaram, India.
Abstract: Digital multipliers, the most important part which is used to implement most of the digital processing
and arithmetic applications such as Filters, FFT’s, etc. As the rapid developments in technology required, many
researchers are going to design multipliers which offers an efficient design aspects with respect to the speed
and power consumption. Digital multipliers are one of the most essential arithmetic functional units. The
overall performance of these systems depends on the multiplier’s throughput. The negative bias temperature
instability (NBTI) effect occurs when a pMOS transistor is under negative bias (Vgs = −Vdd), which results the
increase in the threshold voltage of the pMOS transistor, hence the delay in the multiplier is increased. In the
same way, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both
the temperature effects decreases the transistor speed, in the long run, the system may fail due to timing
violations. Hence, there is a need to design a high speed and power efficient multiplier to increase the
performance of the device. In this paper Design of Multiplier circuit using Adaptive Hold Technique is
proposed. By using AHT circuit we can reduce the NBTI & PBTI effects, hence performance in terms of delay
will be increased and the aging effects will be reduced.
Keywords: Adaptive hold Technique (AHT), Metal oxide semiconductor (MOS), Negative bias temperature
instability (NBTI), positive bias temperature instability (PBTI).
I. Introduction
A multiplier is one of the most important unit which plays a vital role among most of the critical
arithmetic functional units in many applications such as Discrete cosine transforms (DCTs), digital filtering,
Fourier transform (FTs), The rate of production of these application devices depends on multipliers. If the
multipliers have high delay then the overall performance of the device will be reduced.
Moreover, there are some temperature instability effects such as NBTI (Negative bias temperature
instability) and PBTI (Positive bias temperature instability) occurs at the harsh environment in some
applications like aerospace applications, chemical industries and in various nuclear applications. The NBTI
occurs when a pMOS transistor is under negative bias (Vgs=−Vdd). In this situation, the interaction between
inversion layer holes and hydrogen- passivated Si atoms breaks the Si–H bond generated during the oxidation
process, generating H or H2 molecules. When these molecules get diffused, there will be incorporate traps will
be left. These traps between silicon and the gate oxide lead to increase in threshold voltage (Vth) and
automatically show an impact on reducing the speed in circuit switching. When the biased voltage is removed,
the reverse reaction occurs, and then NBTI effect will be reduced. However, the reverse reaction does not
eliminate all the interface traps generated during the stress phase, and Vth is increased in the long term. Hence, it
is important to design a more reliable high-performance multiplier which must have reduced threshold voltage
so, that NBTI can be reduced.
The similar effect on an nMOS transistor is PBTI, which occurs when an nMOS transistor is under
positive bias. Compared with the NBTI effect, the PBTI effect is much smaller on oxide/polygate transistors,
and therefore is usually ignored. Whereas, for high-k/metal-gate nMOS transistors with significant charge
trapping, the PBTI effect can no longer be ignored. In open literature it is shown that the PBTI effect is more
significant than the NBTI effect on 32-nm high-k/metal-gate processes [2].
A traditional method to mitigate the aging effect is overdesign [3], including such things as guard-
banding and gate over sizing; however, this approach are area and power inefficient. To avoid this problem,
many NBTI-aware methodologies have been proposed. An NBTI-aware technology mapping technique was
proposed by Yang etal., Calmera.A etal,.[3-6] to guarantee the performance of the circuit during its lifetime.
B.C.Paul, etal designed an NBTI-aware sleep transistor [7] to reduce the aging effects on pMOS sleep-
transistors, and the lifetime stability of the power-gated circuits under consideration was improved. Y Y. Chen
et al [8] proposed a joint logic restructuring and pin reordering method, which is based on detecting functional
symmetries and transistor stacking effects. They also proposed an NBTI optimization method that considered
path sensitization. Y.Lee etal., M.Basoglu etal., [9, 10] proposed dynamic voltage scaling and body-basing
2. Implementation of a High Speed and Power Efficient Reliable Multiplier Using Adaptive...
DOI: 10.9790/2834-10632733 www.iosrjournals.org 28 | Page
techniques to reduce power or extend circuit life. However, these techniques require circuit modifications or
optimization in specific circuits.
Traditional circuits use critical path delay as the overall circuit clock cycle in order to perform
correctly. However, the probability that the critical paths are activated is low. In most cases, the path delay is
shorter than the critical path. For these noncritical paths, using the critical path delay as the overall cycle period
will result in significant timing waste. Hence, the proposed adaptive hold multiplier is designed to reduce the
delay as well as to eliminate the temperature instabilities.
II. Existing Methods
2.1. Array Multiplier
The Array multiplier is well known due to its regular structure. Multiplier circuit is based on add and
shift algorithm. Each partial product is generated by the multiplication of the multiplicand with one multiplier
bit. The partial product are shifted according to their bit orders and then added. The addition can be performed
with normal carry propagate adder. N-1 adders are required where N is the multiplier length.
Fig.1 Multiplication Process
The AM is a fast parallel multiplier and the multiplication process is as shown in Fig. 1, and Fig.2
shows the block diagram of Array Multiplier. It consists of (n−1) rows of carry save adder (CSA), in which each
row contains (n − 1) full adder (FA) cells. Each FA in the CSA array has two outputs: 1) the sum bit goes down
and 2) the carry bit goes to the lower left FA. The last row is a ripple adder for carry propagation. The FAs in
the AM are always active regardless of input. In the results 16bit, 32bit array multipliers is designed and
compared.
Fig.2 Array Multiplier
2.2 Column Bypassing Multiplier
A column-bypassing multiplier is an advanced multiplier when compared to the traditional array
multiplier (AM). A low-power column-bypassing multiplier design is proposed to reduce power and delay as
well. According to Column Bypasing Multiplier the FA operations are disabled with the corresponding bit in the
multiplicand is 0. Fig.3 shows the architecture of 4×4 column-bypassing multiplier. In open literature the
column-bypassing multiplier is available [11] it is given by M.C.Wen, etal.
3. Implementation of a High Speed and Power Efficient Reliable Multiplier Using Adaptive...
DOI: 10.9790/2834-10632733 www.iosrjournals.org 29 | Page
Fig.3 Column Bypassing Multiplier
2.3 Row-Bypassing Multiplier
A low-power row-bypassing multiplier [13]
is also proposed to reduce the activity power of the AM. The
internal Architecture of the Row bypassing multiplier is as shown in the Fig.4. The operation of the low-power
row-bypassing multiplier is nearer as that of the low-power column-bypassing multiplier, but the difference is
the selector of the multiplexers and the tristate gates. The inputs are bypassed to FAs in the second rows, and the
tristate gates turn off the input paths to the FAs. Therefore, no switching activities occur in the first-row FAs; in
return, power consumption is reduced. Similarly, because b2 is 0, no switching activities will occur in the
second-row FAs. However, the FAs must be active in the third row because the b3 is not zero.
More detailed information for the row-bypassing multiplier is given in the open literature [12] by J.Ohban etal.
Fig.3 Row-bypassing multiplier.
III. Proposed Technique
The aging-aware reliable multiplier is designed by interlinking the Adaptive Hold Technique to the
either Row-bypassing or Column- bypassing multipliers. The proposed AHT Architecture consists of different
blocks such as of two m-bit inputs (m is a positive number), one 2m-bit output, one column or row-bypassing
multiplier, 2m 1-bit Razor flip-flops, and an AHT circuit. The overall architecture of the Aging Multiplier is as
shown in Fig.4.
As the two aging-aware multipliers can be implemented using similar architecture, and the difference
between the two bypassing multipliers lies in the input signals of the AHT. According to the bypassing selection
in the column or row-bypassing multiplier, the input signal of the AHT in the architecture with the column-
bypassing multiplier is the multiplicand (Md), whereas that of the row-bypassing multiplier is the multiplicator
4. Implementation of a High Speed and Power Efficient Reliable Multiplier Using Adaptive...
DOI: 10.9790/2834-10632733 www.iosrjournals.org 30 | Page
(mr). Razor flip-flops can be used to detect whether timing violations occur before the next input pattern arrives.
The functioning of the each module in the proposed multiplier is illustrated as follows:
Fig.4 Architecture of Aging Aware Multiplier
3.1 Razor flip flop
Razor flip-flops can be used to detect whether timing violations occur before the next input pattern
arrives. A 1-bit Razor flip-flop contains a main flip-flop, shadow latch, XOR gate, and multiplexer. The main
flip-flop catches the execution result for the combination circuit using a normal clock signal, and the shadow
latch catches the execution result using a delayed clock signal, which is slower than the normal clock signal. If
the latched bit of the shadow latch is different from that of the main flip-flop, this means the path delay of the
current operation exceeds the cycle period, and the main flip-flop catches an incorrect result. If errors occur, the
Razor flip-flop will set the error signal to 1 to notify the system to reexecute the operation and notify the AHL
circuit that an error has occurred.
Fig.5 Razor Flip-flop
3.2 Adaptive hold Technique
The Adaptive Hold Technique circuit is the key component of variable-latency multiplier. The AHL
circuit contains decision block, MUX and a D flip-flop. If the cycle period is too short, the column-bypassing
multiplier is not able to complete these operations successfully, causing timing violations. These timing
violations will be caught by the Razor flip-flops, which generate error signals. If errors happen frequently, it
means the circuit has suffered significant timing degradation due to the aging effect.
The overall flow of the proposed architecture is as follows: when input pattern is arrived to the column
or row bypassing multiplier, the AHT circuit execute simultaneously. According to the number of zeros in the
multiplicand or multiplicator, the AHT circuit will decides whether the input patterns require one or two cycles.
If the input pattern requires two cycles to complete, the AHT will output 0 to disable the clock signal of the flip-
flops. Otherwise, the AHT will output 1 for normal operations. When the column or row bypassing multiplier
finishes the operation, the result will be passed to the Razor flip-flops. The Razor flip-flops check whether there
is the path delay timing violation. If timing violations occur, it means the cycle period is not long enough for the
current operation to complete and that the execution result of the multiplier is incorrect. Thus, the Razor flip-
flops will output an error to inform the system that the current operation needs to be reexecuted using two cycles
to ensure the operation is correct. In this situation, the extra reexecution cycles caused by timing violation incurs
a penalty to overall average latency. However, the proposed AHT circuit can accurately predict whether the
input patterns require one or two cycles in most cases. Only a few input patterns may cause a timing variation
5. Implementation of a High Speed and Power Efficient Reliable Multiplier Using Adaptive...
DOI: 10.9790/2834-10632733 www.iosrjournals.org 31 | Page
when the AHT circuit judges incorrectly. In this case, the extra reexecution cycles did not produce significant
timing degradation.
Fig.6 Internal Architecture of AHT circuit
IV. Results
The traditional multipliers and proposed multiplier with 16bit, 32bit are designed in Verilog using
Xilinx tool 14.1 version and the simulations are observed with ISE simulator. Xilinx Synthesizer is used to
analyse the delay and the Xpower analyzer is used to analyse the Static and Dynamic power. Fig.7- Fig.11 are
the simulation results for 16 bit multipliers, Fig.12 - Fig.16 are simulation results for 32 bit multipliers. Table.1
and Table.2 are the synthesis results of 16 and 32bit multipliers respectively.
4.1 Simulations results
Fig.7 16x16 Array Multiplier
Fig.8 16x16 Row bypassing
Fig.9 16x16 Column bypassing
Fig.10 16x16 AHT using row bypassing
Fig.11 16x16 AHT using column bypassing
6. Implementation of a High Speed and Power Efficient Reliable Multiplier Using Adaptive...
DOI: 10.9790/2834-10632733 www.iosrjournals.org 32 | Page
Fig.12 32x32 Array Multiplier
Fig.13 32*32 Row bypassing
Fig.14 32*32 Column bypassing
Fig.15 32*32 AHT using row bypassing
Fig.16 32*32 AHT using column bypassing.
4.2 Synthesis results
Table.1 Comparison table of 16*16 multipliers
NAME
DELAY in
ns
POWER
(W)
AREA
Quiescent Power
(W)
Dynamic Power
(W)
Total Power
(W)
LUTs FFs SLICES
Array 41.821 0.081 0.12 0.201 701 - 389
Row
Bypassing
32.162 0.081 0.061 0.142 857 - 476
Column
Bypassing
30.872 0.081 0.04 0.121 726 - 409
AHT Row 6.420 0.081 0.008 0.089 1375 130 712
AHT Column 6.420 0.081 0.005 0.085 1199 132 626
7. Implementation of a High Speed and Power Efficient Reliable Multiplier Using Adaptive...
DOI: 10.9790/2834-10632733 www.iosrjournals.org 33 | Page
Table.2 Comparison table of 32*32 Multipliers
V. Conclusion
In this paper the proposed Technique for multiplier design has three important features. First, its Delay
is very less when compared to the Traditional Multipliers. Second, it can provide reliable operations even after
the aging effect occurs. The Razor flip-flops detect the timing violations and re-execute the operations using two
cycles. Last but not least, the AHT architecture is power efficient and it can also adjust the percentage of one-
cycle patterns to minimize performance degradations due to the aging effect. When the circuit is aged, and many
errors occur, the AHT circuit uses the second judging block to decide if an input is one cycle or two cycles and
hence the timing errors can also be eliminated and can perform the error free operations. As the AHT Technique
can be implemented by using both Row and Column bypassing multipliers, the 32bit AHT row bypassing
multiplier can perform its task with decrease of 47.004ns delay and 79milli-watts power dissipation when
compared to normal row multiplier. Similarly, the AHT column by passing multipliers can perform its task with
decrease of 45.507ns delay and 70milli-watts power dissipation when compared to normal column multiplier.
The proposed AHT architecture has a disadvantage in terms of size as the number of LUTs and Slices are more
in addition the Flip-flops are also used in order to increase the speed. But the AHT Multipliers has a great
advantage in the both Power and Delay as well but and hence, it can be stated as the reliable multiplier
technique which can be used in harsh environment mostly in aerospace applications etc.
References
[1] Lin.I.C., Cho.Y.H. and Yang.Y.M., Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic, IEEE Transactions
on Very Large Scale Integration(VLSI) Systems, 23(3), 2015, 544-556.
[2] S.Zafar, A. Kumar, E. Gusev, and E. Cartier, Threshold voltage instabilities in high-k gate dielectric stack,IEEE Trans. Device
Mater, 5(1), 2005, 45–64.
[3] Yang, Hao.I, Shyh.Chyiyang, Wei Hwang and Ching Te Chuang, Impacts of NBTI/PBTI on Timing Control Circuits and
Degradation Tolerant Design in Nanoscale CMOS SRAM, IEEE Transactions on Circuits and Systems I, 58(6), 2011, 1239-1251.
[4] Calimera.A, Macii.E. and Poncino.M., Design Techniques for NBTI-Tolerant Power-Gating Architectures, IEEE Transactions on
Circuits and Systems II, 59(4),2012,249- 253.
[5] Paul.B.C., Kunhyuk Kang, Kufluoglu.H., Alam.M.A. and Roy.K., Impact of NBTI on the temporal performance degradation of
digital circuits, IEEE Transactions on Electron Device Letters, 26(8), 2005, 560-562.
[6] B.C.Paul, K.Kang, H.Kufluoglu, M.A.Alam and K.Roy, Negative bias temperature instability: Estimation and design for improved
reliability of nanoscale circuit, IEEE Transaction on Computer Aided Design and Integrated Circuits Systems, 26(4), 2007, 743–
751.
[7] Olivieri.N, Design of synchronous and asynchronous variable-latency pipelined multipliers, IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, 9(2), 2001, 365-376.
[8] Y.Y.Chen, Variable-latency adder (VL-Adder) designs for low power and NBTI tolerance, IEEE Transaction on Very Large Scale
Integration (VLSI) Systems, 18(11), 2010, 1621–1624.
[9] M.Basoglu, M.Orshansky and M.Erez, NBTI-aware DVFS, A new approach to saving energy and increasing processor lifetime:
Proc.ACM/IEEE ISLPED, 2010, 253–258.
[10] D.Mohapatra, G.Karakonstantis and K.Roy, Low-power process variation tolerant arithmetic units using input-based elastic
clocking: Proc.ACM/IEEE ISLPED, 2007, 74–79.
[11] M.C.Wen, S.J.Wang and Y.N.Lin, Low power parallel multiplier with column bypassing: Proc. of IEEE ISCAS, 2005,1638–1641.
[12] J.Ohban, V.G.Moshnyaga and K.Inoue, Multiplier energy reduction through bypassing of partial products: Proc. APCCAS, 2002.
NAME
DELAY
in ns
POWER
(W)
AREA
Quiescent
Power (W)
Dynamic
Power (W)
Total
Power
(W)
LUTs FFs SLICES
Array 73.619 0.081 0.142 0.223 2963 - 1647
Row
Bypassing
53.467 0.081 0.088 0.169 3640 - 2018
Column
Bypassing
51.973 0.081 0.075 0.156 3063 - 1720
AHT Row 6.463 0.081 0.009 0.09 5153 259 2653
AHT
Column
6.466 0.081 0.005 0.086 4852 271 2676