In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
This paper aims to use a three-phase quasi-Z-source indirect matrix converter (QZSIMC) to expand the voltage gain for application in a Permanent Magnet Synchronous Motor (PMSM) drives. In this converter, a unique quasi-Z-source network (QZSN) connects the three-phase input voltage to conventional indirect matrix converter (IMC) in order to boost the supply voltage for PMSM because of limited voltage gain of IMC. Dual space vector modulation (SVM) is utilized to control the QZSIMC. The amplitude of output voltage for quasi-Z-source network is raised by the shoot-through of the rectifier stage, so the system voltage gain becomes greater. Through selecting the optimized value of shoot through duty ratio (D) and modulation index of the rectifier stage (), the drive system can automatically regulate the output voltage of QZSIMC during conditions of voltage sag , step change in load torque and reference speed change when the required voltage gain of QZSIMC is more than 0.866 depending on input voltage and required output voltage.The vector control technique based on closed loop speed control is proposed to control speed of the motor from zero to rated speed which is combined with the proposed converter to obtain the motor drive. The simulation results with MATLAB /Simulink 2015 are obtained to validate performance of PMSM drive.
2011 Protection of a 3.3V Domain and Switchable 1.8V/3.3V I/O in 40nm and 28n...Sofics
2011 Japan RCJ symposium
Today’s advanced technologies’ overdrive transistors cannot always meet the signal speeds of existing standards. This paper describes the issues, solutions and results to build the necessary protection for HBM, MM, CDM and latch-up for a 3.3V domain and 1.8V/3.3V I/O, based only on 1.8V transistors, in a 40nm process. Results of the design ported to 28nm are also presented.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
This paper aims to use a three-phase quasi-Z-source indirect matrix converter (QZSIMC) to expand the voltage gain for application in a Permanent Magnet Synchronous Motor (PMSM) drives. In this converter, a unique quasi-Z-source network (QZSN) connects the three-phase input voltage to conventional indirect matrix converter (IMC) in order to boost the supply voltage for PMSM because of limited voltage gain of IMC. Dual space vector modulation (SVM) is utilized to control the QZSIMC. The amplitude of output voltage for quasi-Z-source network is raised by the shoot-through of the rectifier stage, so the system voltage gain becomes greater. Through selecting the optimized value of shoot through duty ratio (D) and modulation index of the rectifier stage (), the drive system can automatically regulate the output voltage of QZSIMC during conditions of voltage sag , step change in load torque and reference speed change when the required voltage gain of QZSIMC is more than 0.866 depending on input voltage and required output voltage.The vector control technique based on closed loop speed control is proposed to control speed of the motor from zero to rated speed which is combined with the proposed converter to obtain the motor drive. The simulation results with MATLAB /Simulink 2015 are obtained to validate performance of PMSM drive.
2011 Protection of a 3.3V Domain and Switchable 1.8V/3.3V I/O in 40nm and 28n...Sofics
2011 Japan RCJ symposium
Today’s advanced technologies’ overdrive transistors cannot always meet the signal speeds of existing standards. This paper describes the issues, solutions and results to build the necessary protection for HBM, MM, CDM and latch-up for a 3.3V domain and 1.8V/3.3V I/O, based only on 1.8V transistors, in a 40nm process. Results of the design ported to 28nm are also presented.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
CELL STABILITY ANALYSIS OF CONVENTIONAL 6T DYNAMIC 8T SRAM CELL IN 45NM TECHN...VLSICS Design
A SRAM cell must meet requirements for operation in submicron/nano ranges. The scaling of CMOS technology has significant impact on SRAM cell -- random fluctuation of electrical characteristics and substantial leakage current. In this paper we present dynamic column based power supply 8T SRAM cell and comparing the proposed SRAM cell with respect to conventional SRAM 6T in various aspects. To verify read stability and write ability analysis we use N-curve metric. Simulation results affirmed that proposed 8T SRAM cell achieved improved read stability, read current, and leakage current in 45nm Technology comparing with conventional 6T SRAM using cadence virtuoso tool.
Active matrix organic light emitting diode
(AMOLED) displays are considerably attractive for high
brightness, high efficiency and fast response time. Active
matrix employing thin Film Transistors (TFTs) allows
OLED displays to be larger in size, higher in resolution
and lower in power consumption than passive matrix.
Especially, low temperature polycrystalline silicon
(LTPS) TFT employing excimer laser annealing (ELA) is
widely used due to high mobility and high stability. A
number of TFT active matrix pixel circuits have been
developed in order to compensate for TFT parameter
variations due to the fluctuation of excimer laser energy.
We discuss various compensation schemes of LTPS TFT
pixel circuits.
Keywords: AMOLED; poly-Si TFT; pixel
In present days of electrical industries, adjustable speed controlled induction
motor drives are very common due to its versatile features. For the speed control of induction
motor, variable frequency sources are the heart of such drives. To attain variable frequency
and variable voltage supply a power electronics device; single phase matrix converter is
proposed.
In this paper, the single phase matrix converter is modeled in MATLAB Simulink
environment; controlled with sinusoidal pulse width modulation technique, control scheme is
implemented in a Xilinx system generator environment and interfaced with power circuit in
MATLAB Simulink. Analyses this SPMC with different type of loads in both frequency step
up and step down modes. Based on simulation results, this converter is suitable for variable
frequency power supplies, varying load conditions and variable speed electrical drives.
FPGA control is best suitable for controlling a circuit like SPMC, consists of more
controlled elements to attain fast operation.
Implementation of a High Speed and Power Efficient Reliable Multiplier Using ...iosrjce
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Solid-State Transformer (S2T) also known as Power Electronic Transformer (PET) is applied in various industrial fields compared to the conventional transformer due to it flexible voltage transfer ratio, high power density, and low harmonic distortion. This paper presents the S2T of Single Phase Matrix Converter (SPMC) that acts as cyclo-converter. A 1kHz frequency was synthesized on the primary side of the transformer using Pulse Width Modulation (PWM) technique, whilst, the output converted by the SPMC that produces the 50Hz frequency. A part of AC to AC operation, the switching algorithm for safe-commutation technique is also presented to solve the commutation problem caused by the usage of inductive load. Minimization of size, losses and optimal efficiency are the advantages of this approach. The proposed model was simulated by using MATLAB/Simulink (MLS).
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
International Journal of VLSI design & Communication Systems (VLSICS) VLSICS Design
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much necessary to see to it that the clock signals are properly received specially in receiver circuits where data sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew, interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy. The design is simple and the power consumption is 1.01mW.
Variable frequency drive optimization using torque ripple control and self-Tu...IJECEIAES
Drive’s output power must be restricted for the prevention of stresses over higher components in the input power system while utilizing a three-phase Variable Frequency Drive (VFD) which has powered from a single-phase AC source. To resolve this problem, we introduced a novel motor q-axis current (M-QAC) with torque ripple control (TRC) of an induction motor and self-tuning PI controller with particle swarm optimization (STP-PSO) for mitigating the stress over induction motor by the torque ripple elimination and controlling. Our proposed approach has an information related to the different parts stresses of the VFD which includes the terminal block and the diodes in the input side, DC bus capacitors, torque ripple, harmonics in the current and active performance for sudden changes in the speed and load. Our proposed model is simulated in MATLAB/Simulink environment. In this paper the standard dc-bus voltage ripple-based fold- back, q-axis average current fold-back and q-axis ripple current fold-back methods are utilized for the comparative analysis. Also the comparative analysis of proposed M-QAC, TRC and STP-PSO methodologies are provide with respect to steady-state values of peak-to-peak dc voltage (Vdc), peak-to-peak input current (IINPUT), input RMS current (IRMS), motor speed and the output power. Extensive simulated performance show that the STP-PSO obtained superior results over conventional standard dc-bus voltage ripple-based fold-back method, M-QAC and TRC schemes.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
ChipStart is a global semiconductor intellectual property (IP) solutions company headquartered in Palo Alto, California. ChipStart provides sales, marketing, and support engagement solutions for companies that commerce third party semiconductor intellectual property. ChipStart is also a developer of high-quality, highly-differentiated, pre-verified IP subsystem solutions, macros, analog/mixed-signal (AMS) foundry services, and related design services for ASIC and fabless semiconductor companies.
“Power and Temperature Analysis of 12T CMOS SRAM Designed With Short Channel ...iosrjce
This paper focuses mainly on dynamic power dissipations at different temperature for both read and
write operations of 12T SRAM. In the proposed 12T structure virtual vdd concept is employed because of this
leakage current will reduce. Hence reduction in leakage current causes reduction in dynamic power. Power
dissipation of the proposed SRAM cell have been determined and compared to those of some other existing
memory cells. Proposed cell is a short channel BSIM4 model. It is observed that power dissipation of 12T
SRAM for read operation at 40̊
̊
is 44.7nw and for write operation it is 38.79nw. The proposed SRAM cell
dissipates less power. Simulation has been done in Tanner-13 EDA tool for 50nm.
Built-in Self Repair for SRAM Array using RedundancyIDES Editor
In this paper, a built-in self repair technique for
word-oriented two-port SRAM memories is presented. The
technique is implemented by additional hardware design
instead of traditional software diagnostic procedures and the
computation time is minimized. A built-in self-test (BIST) is
used to detect the faulty locations which are isolated
immediately after detection. Therefore, the redirection process
can be executed as soon as possible. Spare rows are used to
replace the faulty rows. The hardware overhead of the
automatic fault isolation design depends on size of memory
system. All the repairs using BISR circuit are done at power
on.
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is an open access journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
CELL STABILITY ANALYSIS OF CONVENTIONAL 6T DYNAMIC 8T SRAM CELL IN 45NM TECHN...VLSICS Design
A SRAM cell must meet requirements for operation in submicron/nano ranges. The scaling of CMOS technology has significant impact on SRAM cell -- random fluctuation of electrical characteristics and substantial leakage current. In this paper we present dynamic column based power supply 8T SRAM cell and comparing the proposed SRAM cell with respect to conventional SRAM 6T in various aspects. To verify read stability and write ability analysis we use N-curve metric. Simulation results affirmed that proposed 8T SRAM cell achieved improved read stability, read current, and leakage current in 45nm Technology comparing with conventional 6T SRAM using cadence virtuoso tool.
Active matrix organic light emitting diode
(AMOLED) displays are considerably attractive for high
brightness, high efficiency and fast response time. Active
matrix employing thin Film Transistors (TFTs) allows
OLED displays to be larger in size, higher in resolution
and lower in power consumption than passive matrix.
Especially, low temperature polycrystalline silicon
(LTPS) TFT employing excimer laser annealing (ELA) is
widely used due to high mobility and high stability. A
number of TFT active matrix pixel circuits have been
developed in order to compensate for TFT parameter
variations due to the fluctuation of excimer laser energy.
We discuss various compensation schemes of LTPS TFT
pixel circuits.
Keywords: AMOLED; poly-Si TFT; pixel
In present days of electrical industries, adjustable speed controlled induction
motor drives are very common due to its versatile features. For the speed control of induction
motor, variable frequency sources are the heart of such drives. To attain variable frequency
and variable voltage supply a power electronics device; single phase matrix converter is
proposed.
In this paper, the single phase matrix converter is modeled in MATLAB Simulink
environment; controlled with sinusoidal pulse width modulation technique, control scheme is
implemented in a Xilinx system generator environment and interfaced with power circuit in
MATLAB Simulink. Analyses this SPMC with different type of loads in both frequency step
up and step down modes. Based on simulation results, this converter is suitable for variable
frequency power supplies, varying load conditions and variable speed electrical drives.
FPGA control is best suitable for controlling a circuit like SPMC, consists of more
controlled elements to attain fast operation.
Implementation of a High Speed and Power Efficient Reliable Multiplier Using ...iosrjce
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Solid-State Transformer (S2T) also known as Power Electronic Transformer (PET) is applied in various industrial fields compared to the conventional transformer due to it flexible voltage transfer ratio, high power density, and low harmonic distortion. This paper presents the S2T of Single Phase Matrix Converter (SPMC) that acts as cyclo-converter. A 1kHz frequency was synthesized on the primary side of the transformer using Pulse Width Modulation (PWM) technique, whilst, the output converted by the SPMC that produces the 50Hz frequency. A part of AC to AC operation, the switching algorithm for safe-commutation technique is also presented to solve the commutation problem caused by the usage of inductive load. Minimization of size, losses and optimal efficiency are the advantages of this approach. The proposed model was simulated by using MATLAB/Simulink (MLS).
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
International Journal of VLSI design & Communication Systems (VLSICS) VLSICS Design
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much necessary to see to it that the clock signals are properly received specially in receiver circuits where data sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew, interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy. The design is simple and the power consumption is 1.01mW.
Variable frequency drive optimization using torque ripple control and self-Tu...IJECEIAES
Drive’s output power must be restricted for the prevention of stresses over higher components in the input power system while utilizing a three-phase Variable Frequency Drive (VFD) which has powered from a single-phase AC source. To resolve this problem, we introduced a novel motor q-axis current (M-QAC) with torque ripple control (TRC) of an induction motor and self-tuning PI controller with particle swarm optimization (STP-PSO) for mitigating the stress over induction motor by the torque ripple elimination and controlling. Our proposed approach has an information related to the different parts stresses of the VFD which includes the terminal block and the diodes in the input side, DC bus capacitors, torque ripple, harmonics in the current and active performance for sudden changes in the speed and load. Our proposed model is simulated in MATLAB/Simulink environment. In this paper the standard dc-bus voltage ripple-based fold- back, q-axis average current fold-back and q-axis ripple current fold-back methods are utilized for the comparative analysis. Also the comparative analysis of proposed M-QAC, TRC and STP-PSO methodologies are provide with respect to steady-state values of peak-to-peak dc voltage (Vdc), peak-to-peak input current (IINPUT), input RMS current (IRMS), motor speed and the output power. Extensive simulated performance show that the STP-PSO obtained superior results over conventional standard dc-bus voltage ripple-based fold-back method, M-QAC and TRC schemes.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
ChipStart is a global semiconductor intellectual property (IP) solutions company headquartered in Palo Alto, California. ChipStart provides sales, marketing, and support engagement solutions for companies that commerce third party semiconductor intellectual property. ChipStart is also a developer of high-quality, highly-differentiated, pre-verified IP subsystem solutions, macros, analog/mixed-signal (AMS) foundry services, and related design services for ASIC and fabless semiconductor companies.
“Power and Temperature Analysis of 12T CMOS SRAM Designed With Short Channel ...iosrjce
This paper focuses mainly on dynamic power dissipations at different temperature for both read and
write operations of 12T SRAM. In the proposed 12T structure virtual vdd concept is employed because of this
leakage current will reduce. Hence reduction in leakage current causes reduction in dynamic power. Power
dissipation of the proposed SRAM cell have been determined and compared to those of some other existing
memory cells. Proposed cell is a short channel BSIM4 model. It is observed that power dissipation of 12T
SRAM for read operation at 40̊
̊
is 44.7nw and for write operation it is 38.79nw. The proposed SRAM cell
dissipates less power. Simulation has been done in Tanner-13 EDA tool for 50nm.
Built-in Self Repair for SRAM Array using RedundancyIDES Editor
In this paper, a built-in self repair technique for
word-oriented two-port SRAM memories is presented. The
technique is implemented by additional hardware design
instead of traditional software diagnostic procedures and the
computation time is minimized. A built-in self-test (BIST) is
used to detect the faulty locations which are isolated
immediately after detection. Therefore, the redirection process
can be executed as soon as possible. Spare rows are used to
replace the faulty rows. The hardware overhead of the
automatic fault isolation design depends on size of memory
system. All the repairs using BISR circuit are done at power
on.
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is an open access journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
Static-Noise-Margin Analysis of Modified 6T SRAM Cell during Read Operationidescitation
As modern technology is spreading fast, it is very
important to design low power, high performance, fast
responding SRAM(Static Random Access Memory) since they
are critical component in high performance processors. In
this paper we discuss about the noise effect of different SRAM
circuits during read operation which hinders the stability of
the SRAM cell. This paper also represents a modified 6T
SRAM cell which increases the cell stability without
increasing transistor count.
Simulated Analysis and Enhancement of Blowfish Algorithmiosrjce
This paper represents or analyzes the security of system based on Blowfish. Blowfish mainly focuses
on the encrypt and decrypt techniques and algorithms apply for cryptanalysis. It describe the algorithms for
encryption as well as decryption algorithms and also give the sufficient description of key generation, key
expansion, function and working principle of Blowfish cipher with proper explanations. Taking the current era,
Most of the famous systems which offer security for a network or web or to a data are vulnerability to attacks and
they are broken at some point of time by effective cryptanalysis methods, irrespective of its complex algorithmic
design. In the general, today’s cryptography world is bounded to an interpretive of following any one or multi
encryption scheme and that too for a single iteration on a single file only. This is evident in the maximum of the
encryption-decryption cases. It also describes the comparisons between older blowfish and enhances blowfish. It
also shows enhance Blowfish algorithm for encryption and decryption of data. It is also give the proper simulated
analysis of encryption and decryption time for different file formats using a windows application. It describe
feature of application and its process and efficiency as well as calculation of time and throughput.
This paper presents a spin-transfer torque- magnetic
tunnel junction (STT-MTJ) based non-volatile 9-transistor
(9T) SRAM cell. The cell achieves low power dissipation due
to its series connected MTJ elements and read buffer which
offer stacking effect. The paper studies the impact of PVT
(process, voltage, and temperature) variations on the design
metric of the SRAM cell such as write delay and compares the
results with non-volatile 8T SRAM cell (NV8T). The proposed
design consumes lower leakage power and exhibits narrower
spread in write delay compared with NV8T.
An Examination of Effectuation Dimension as Financing Practice of Small and M...iosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
250nm Technology Based Low Power SRAM Memoryiosrjce
High integration density, low power and fastperformance are all critical parameters in designing of
memory blocks. Static Random Access Memories (SRAMs)’s focusing on optimizing dynamic power concept of
virtual source transistors is used for removing direct connection between VDD and GND.
Also stacking effect can be reduced by switching off the stacktransistors when the memory is ideal and the
leakage current using SVL techniques This paper discusses the evolution of 9t SRAM circuits in terms of low
power consumption, The whole circuit verification is done on the Tanner tool, Schematic of the
SRAM cell is designed on the S-Edit and net list simulation done by using T-spice and waveforms are analyzed
through the W-edit
Energy optimization of 6T SRAM cell using low-voltage and high-performance in...IJECEIAES
The performance of the cell deteriorates, when static random access memory (SRAM) cell is operated below 1V supply voltage with continuous scale down of the complementary metal oxide semiconductor (CMOS) technology. The conventional 6T, 8T-SRAM cells suffer writeability and read static noise margins (SNM) at low-voltages leads to degradation of cell stability. To improve the cell stability and reduce the dynamic power dissipation at low- voltages of the SRAM cell, we proposed four SRAM cells based on inverter structures with less energy consumption using voltage divider bias current sink/source inverter and NOR/NAND gate using a pseudo-nMOS inverter. The design and implementation of SRAM cell using proposed inverter structures are compared with standard 6T, 8T and ST-11T SRAM cells for different supply voltages at 22-nm CMOS technology exhibit better performance of the cell. The read/write static noise margin of the cell significantly increases due to voltage divider bias network built with larger cell-ratio during read path. The load capacitance of the cell is reduced with minimized switching transitions of the devices during high-to-low and low- to-high of the pull-up and pull-down networks from VDD to ground leads to on an average 54% of dynamic power consumption. When compared with the existing ones, the read/write power of the proposed cells is reduced to 30%. The static power gets reduced by 24% due to stacking of transistors takes place in the proposed SRAM cells as compare to existing ones. The layout of the proposed cells is drawn at a 45-nm technology, and occupies an area of 1.5 times greater and 1.8 times greater as compared with 6T-SRAM cell.
Power analysis of 4 t sram by stacking technique using tanner tooleSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
Design & Implementation of Subthreshold Memory Cell design based on the prima...IOSRJVSP
As there is a demand for portable electronic systems or devices, there is an incremental growth in the technology in the past few decades and also technology is cumulative at a random rate, devices are consuming large amount of power due to this the life of the battery is draining fast. so there must be a alternative devices or circuits which can reduce the power by efficiently maintaining the area and performance, therefore life of battery can be increased. As SRAM is the heart of block in all the electronic design, where the power consumption is maximum there by analyzing, estimating & modifying or changing the logic, will be able to reduce the power and performance can be greatly achieved. This proposal describes under the principle of ultra-low power logic approach which operates under subthreshold voltage operating which leads to lower power and also efficient in functionality along with secondary constraints.
Implementation of High Reliable 6T SRAM Cell Designiosrjce
Memory can be formed with the integration of large number of basic storing element called cells.
SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit.
Modified read and write circuits were proposed in this paper to address incorrect read and write operations in
conventional 6T SRAM cell design available in open literature. Design of a new highly reliable 6T SRAM cell
design is proposed with reliable read, write operations and negative bit line voltage (NBLV). Simulations are
carried out using MENTOR GRAPHICS
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power
clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in
contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
IMPLEMENTATION OF LOW POWER ADIABATIC SRAMVLSICS Design
In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power
clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM
variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.
FPGA IMPLEMENTATION OF LOW POWER SRAM BASED PROCESSOR IN 8T USING HETTSEditor IJMTER
In MOSFETs lower limit sub threshold swing (60mv/decade) restricts the low power
operation. Low voltage operation is enabled by low Vth while maintaining performance. Hence steep
sub threshold slopes provide power-efficient operation without any loss of performance. To obtain
sub threshold swings of less than 30mV/decade with large ON current, Si/SiGe heterojunction
tunneling transistor uses gate controlled modulation. To overcome the impact of HETT
characteristics on SRAM, seven transistors HETT based SRAM design is introduced. Compared to
CMOS this new 8T HETT SRAM achieves reduction in leakage power.
Average and Static Power Analysis of a 6T and 7T SRAM Bit-Cell at 180nm, 90nm...idescitation
A lot of consideration has been given to problems arising due to power dissipation.
Different ideas have been proposed by many researchers from the device level to the
architectural level and above. However, there is no universal way to avoid tradeoffs between
the power, delay and area. This is why; the designers are required to choose appropriate
techniques that satisfy application and product needs. Another important component of
power which contributes to power dissipation is Dynamic Power. This power is increasing
due to prolonged use of the electronic equipments. This is due to the fact that now-a-days
people are working on electronic systems from morning till night; it may be a mobile phone
or a laptop or any other equipment. This paper deals with the estimation of two components
of power i.e. static power (when device is in the standby mode) and the average power
(average amount of energy consumed with respect to time) of a 6T and 7T SRAM (Static
Random Access Memory) bit-cell at 180nm, 90nm, and 45nm CMOS Technology. This is
done in order to estimate the power required for a high speed operation of 6T and 7T
SRAM bit-cell.
DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHN...VLSICS Design
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor
sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.
Design of Low Write-Power Consumption SRAM Cell Based on CNTFET at 32nm Techn...VLSICS Design
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.
Does Goods and Services Tax (GST) Leads to Indian Economic Development?iosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Childhood Factors that influence success in later lifeiosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Emotional Intelligence and Work Performance Relationship: A Study on Sales Pe...iosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Customer’s Acceptance of Internet Banking in Dubaiiosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
A Study of Employee Satisfaction relating to Job Security & Working Hours amo...iosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Consumer Perspectives on Brand Preference: A Choice Based Model Approachiosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Student`S Approach towards Social Network Sitesiosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Broadcast Management in Nigeria: The systems approach as an imperativeiosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
A Study on Retailer’s Perception on Soya Products with Special Reference to T...iosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
A Study Factors Influence on Organisation Citizenship Behaviour in Corporate ...iosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Consumers’ Behaviour on Sony Xperia: A Case Study on Bangladeshiosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Design of a Balanced Scorecard on Nonprofit Organizations (Study on Yayasan P...iosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Public Sector Reforms and Outsourcing Services in Nigeria: An Empirical Evalu...iosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Media Innovations and its Impact on Brand awareness & Considerationiosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Customer experience in supermarkets and hypermarkets – A comparative studyiosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Social Media and Small Businesses: A Combinational Strategic Approach under t...iosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Secretarial Performance and the Gender Question (A Study of Selected Tertiary...iosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Implementation of Quality Management principles at Zimbabwe Open University (...iosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Organizational Conflicts Management In Selected Organizaions In Lagos State, ...iosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Impact of education on innovation performance: evidence from Azerbaijan const...iosrjce
IOSR Journal of Business and Management (IOSR-JBM) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of business and managemant and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications inbusiness and management. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Cancer cell metabolism: special Reference to Lactate PathwayAADYARAJPANDEY1
Normal Cell Metabolism:
Cellular respiration describes the series of steps that cells use to break down sugar and other chemicals to get the energy we need to function.
Energy is stored in the bonds of glucose and when glucose is broken down, much of that energy is released.
Cell utilize energy in the form of ATP.
The first step of respiration is called glycolysis. In a series of steps, glycolysis breaks glucose into two smaller molecules - a chemical called pyruvate. A small amount of ATP is formed during this process.
Most healthy cells continue the breakdown in a second process, called the Kreb's cycle. The Kreb's cycle allows cells to “burn” the pyruvates made in glycolysis to get more ATP.
The last step in the breakdown of glucose is called oxidative phosphorylation (Ox-Phos).
It takes place in specialized cell structures called mitochondria. This process produces a large amount of ATP. Importantly, cells need oxygen to complete oxidative phosphorylation.
If a cell completes only glycolysis, only 2 molecules of ATP are made per glucose. However, if the cell completes the entire respiration process (glycolysis - Kreb's - oxidative phosphorylation), about 36 molecules of ATP are created, giving it much more energy to use.
IN CANCER CELL:
Unlike healthy cells that "burn" the entire molecule of sugar to capture a large amount of energy as ATP, cancer cells are wasteful.
Cancer cells only partially break down sugar molecules. They overuse the first step of respiration, glycolysis. They frequently do not complete the second step, oxidative phosphorylation.
This results in only 2 molecules of ATP per each glucose molecule instead of the 36 or so ATPs healthy cells gain. As a result, cancer cells need to use a lot more sugar molecules to get enough energy to survive.
Unlike healthy cells that "burn" the entire molecule of sugar to capture a large amount of energy as ATP, cancer cells are wasteful.
Cancer cells only partially break down sugar molecules. They overuse the first step of respiration, glycolysis. They frequently do not complete the second step, oxidative phosphorylation.
This results in only 2 molecules of ATP per each glucose molecule instead of the 36 or so ATPs healthy cells gain. As a result, cancer cells need to use a lot more sugar molecules to get enough energy to survive.
introduction to WARBERG PHENOMENA:
WARBURG EFFECT Usually, cancer cells are highly glycolytic (glucose addiction) and take up more glucose than do normal cells from outside.
Otto Heinrich Warburg (; 8 October 1883 – 1 August 1970) In 1931 was awarded the Nobel Prize in Physiology for his "discovery of the nature and mode of action of the respiratory enzyme.
WARNBURG EFFECT : cancer cells under aerobic (well-oxygenated) conditions to metabolize glucose to lactate (aerobic glycolysis) is known as the Warburg effect. Warburg made the observation that tumor slices consume glucose and secrete lactate at a higher rate than normal tissues.
Introduction:
RNA interference (RNAi) or Post-Transcriptional Gene Silencing (PTGS) is an important biological process for modulating eukaryotic gene expression.
It is highly conserved process of posttranscriptional gene silencing by which double stranded RNA (dsRNA) causes sequence-specific degradation of mRNA sequences.
dsRNA-induced gene silencing (RNAi) is reported in a wide range of eukaryotes ranging from worms, insects, mammals and plants.
This process mediates resistance to both endogenous parasitic and exogenous pathogenic nucleic acids, and regulates the expression of protein-coding genes.
What are small ncRNAs?
micro RNA (miRNA)
short interfering RNA (siRNA)
Properties of small non-coding RNA:
Involved in silencing mRNA transcripts.
Called “small” because they are usually only about 21-24 nucleotides long.
Synthesized by first cutting up longer precursor sequences (like the 61nt one that Lee discovered).
Silence an mRNA by base pairing with some sequence on the mRNA.
Discovery of siRNA?
The first small RNA:
In 1993 Rosalind Lee (Victor Ambros lab) was studying a non- coding gene in C. elegans, lin-4, that was involved in silencing of another gene, lin-14, at the appropriate time in the
development of the worm C. elegans.
Two small transcripts of lin-4 (22nt and 61nt) were found to be complementary to a sequence in the 3' UTR of lin-14.
Because lin-4 encoded no protein, she deduced that it must be these transcripts that are causing the silencing by RNA-RNA interactions.
Types of RNAi ( non coding RNA)
MiRNA
Length (23-25 nt)
Trans acting
Binds with target MRNA in mismatch
Translation inhibition
Si RNA
Length 21 nt.
Cis acting
Bind with target Mrna in perfect complementary sequence
Piwi-RNA
Length ; 25 to 36 nt.
Expressed in Germ Cells
Regulates trnasposomes activity
MECHANISM OF RNAI:
First the double-stranded RNA teams up with a protein complex named Dicer, which cuts the long RNA into short pieces.
Then another protein complex called RISC (RNA-induced silencing complex) discards one of the two RNA strands.
The RISC-docked, single-stranded RNA then pairs with the homologous mRNA and destroys it.
THE RISC COMPLEX:
RISC is large(>500kD) RNA multi- protein Binding complex which triggers MRNA degradation in response to MRNA
Unwinding of double stranded Si RNA by ATP independent Helicase
Active component of RISC is Ago proteins( ENDONUCLEASE) which cleave target MRNA.
DICER: endonuclease (RNase Family III)
Argonaute: Central Component of the RNA-Induced Silencing Complex (RISC)
One strand of the dsRNA produced by Dicer is retained in the RISC complex in association with Argonaute
ARGONAUTE PROTEIN :
1.PAZ(PIWI/Argonaute/ Zwille)- Recognition of target MRNA
2.PIWI (p-element induced wimpy Testis)- breaks Phosphodiester bond of mRNA.)RNAse H activity.
MiRNA:
The Double-stranded RNAs are naturally produced in eukaryotic cells during development, and they have a key role in regulating gene expression .
Professional air quality monitoring systems provide immediate, on-site data for analysis, compliance, and decision-making.
Monitor common gases, weather parameters, particulates.
Nutraceutical market, scope and growth: Herbal drug technologyLokesh Patil
As consumer awareness of health and wellness rises, the nutraceutical market—which includes goods like functional meals, drinks, and dietary supplements that provide health advantages beyond basic nutrition—is growing significantly. As healthcare expenses rise, the population ages, and people want natural and preventative health solutions more and more, this industry is increasing quickly. Further driving market expansion are product formulation innovations and the use of cutting-edge technology for customized nutrition. With its worldwide reach, the nutraceutical industry is expected to keep growing and provide significant chances for research and investment in a number of categories, including vitamins, minerals, probiotics, and herbal supplements.
A brief information about the SCOP protein database used in bioinformatics.
The Structural Classification of Proteins (SCOP) database is a comprehensive and authoritative resource for the structural and evolutionary relationships of proteins. It provides a detailed and curated classification of protein structures, grouping them into families, superfamilies, and folds based on their structural and sequence similarities.
Comparing Evolved Extractive Text Summary Scores of Bidirectional Encoder Rep...University of Maribor
Slides from:
11th International Conference on Electrical, Electronics and Computer Engineering (IcETRAN), Niš, 3-6 June 2024
Track: Artificial Intelligence
https://www.etran.rs/2024/en/home-english/
Richard's aventures in two entangled wonderlandsRichard Gill
Since the loophole-free Bell experiments of 2020 and the Nobel prizes in physics of 2022, critics of Bell's work have retreated to the fortress of super-determinism. Now, super-determinism is a derogatory word - it just means "determinism". Palmer, Hance and Hossenfelder argue that quantum mechanics and determinism are not incompatible, using a sophisticated mathematical construction based on a subtle thinning of allowed states and measurements in quantum mechanics, such that what is left appears to make Bell's argument fail, without altering the empirical predictions of quantum mechanics. I think however that it is a smoke screen, and the slogan "lost in math" comes to my mind. I will discuss some other recent disproofs of Bell's theorem using the language of causality based on causal graphs. Causal thinking is also central to law and justice. I will mention surprising connections to my work on serial killer nurse cases, in particular the Dutch case of Lucia de Berk and the current UK case of Lucy Letby.
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption using MTCMOS Technique
1. IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)
Volume 5, Issue 1, Ver. I (Jan - Feb. 2015), PP 42-49
e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197
www.iosrjournals.org
DOI: 10.9790/4200-05114249 www.iosrjournals.org 42 | Page
A Novel Low Power Energy Efficient SRAM Cell With Reduced
Power Consumption using MTCMOS Technique
S. Mohan Das1
, K. S. Kiran Kumar2
, A.Madhulatha3
1
(Associate Professor, ECE Department, AVR&SVR CET, Nandyal, Kurnool, Andhra Pradesh, India)
2
(Assistant Professor, ECE Department, AVR&SVR CET, Nandyal, Kurnool, Andhra Pradesh, India)
3
(P.G. Student, ECE Department, AVR&SVR CET Nandyal, Kurnool, Andhra Pradesh, India)
Abstract: In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
Keywords: CMOS, 6T SRAM cell, 8T SRAM cell, 9T SRAM cell, MTCMOS, Low Power Consumption.
I. Introduction
Development of digital Integrated Circuits is challenged by high power consumption and greater
threshold leakages. Higher clock speed combination with greater integration functionality and smaller process
geometries contributed to significant growth in power density. Scaling improves functionality and density of
transistors on a chip. Scaling helps to increase operation speed and performance of IC designs. As voltages scale
down with geometries, Vth- threshold voltages must also decrease to gain the performance advantages of new
technology, but leakage current increases exponentially.
Low power and high-stability have been the main issues of SRAM designs as the demand of the
portable electronic market constantly urges for less power-hungry architectures [1]. Many techniques have been
introduced to fulfill this requirement such as scaling the supply voltage, using Multi threshold CMOS process to
minimize the leakage, dividing the SRAM macro into multiple sub-macros to enhance its stability and to reduce
dynamic power. The second challenge in designing a robust SRAM is to ensure a reasonable noise margin,
which is normally measured by the Static Noise Margin (SNM).[2]. According to, these design factors degrade
when threshold voltage variation increases and are also linearly dependent on the reduction of the supply
voltage. As a result, it is extremely difficult to maintain the cell stability as technology enters less than 100 nm
regime. Several more-than-6T SRAM cell designs are given in [3], to improve the stability and power
dissipation. In these papers separate Read and Write ports are employed and hence the cell’s SNM can be
optimized.
Sub threshold leakage current is much larger than the other leakage current and is calculated by using
the following equation.
IDS=K (1-℮V
DS/V
T) ℮ (VGS-VT +αVDS/αVT).
Technique used for minimization of static and dynamic power dissipations in SRAM cell during
write/read operation is MTCMOS. MTCMOS technology provides low leakage and high performance operation
by utilizing high speed, low threshold voltage (Vthl) transistors during active mode and low leakage, high
threshold voltage (VthH) transistors during sleep mode. This technology, also called as power gating, the wake
up latency and power plane integrity are key issues. Several researchers have proposed methods for optimal
sizing of sleep transistors in a given circuit to meet a performance constraint.
In this paper a novel 9T MTCMOS SRAM cell is proposed.[8]. A charge recycling technique is used to
minimize the leakage currents and static energy dissipation during the mode transitions. The total power
dissipations at different temperatures and supply voltages for assessing stability at different pullup ratios have
been determined for the proposed SRAM cell and compared with those of the other existing SRAM cells.
2. A Novel Low Power Energy Efficient SRAM Cell with Reduced Power Consumption
DOI: 10.9790/4200-05114249 www.iosrjournals.org 43 | Page
This paper mainly focuses on reduction of power consumption at higher performance with MTCMOS
technique. Section-II describes the design of conventional 1-bit SRAM cells (existing cells)[9]. Section-III
describes the design of Proposed MTCMOS SRAM cell. Section-IV presents the simulation results of proposed
SRAM cell. Section-V concludes this paper.
II. Conventional SRAM
A. Conventional 6T SRAM cell:
Fig. 1 shows the circuit diagram of a conventional SRAM cell. Word line (WL) is used for enabling the
access transistors T2 and T5 for write operations [3]. Bit lines BL and BL bar are used to store the data and its
compliment. For writing operation, one bit line is high and the other bit line is low. For writing “0”, BL is low
and BL bar is high. When the word line (WL) is asserted high, transistors T2 and T5 are ON and any charge
stored in the BL goes through T2-T3 path to ground. Due to zero value on Q bar, the transistor T4 is ON and T6
is OFF. So the charge is stored at Q bar line. Similarly in the write “1” operation, BL is high and BL bar is low,
due to this T6 is ON and the charge stored on Q bar is discharged through the T5-T6 path and due to this low
value on the Q bar , T1 is ON and T3 is OFF, so the charge is stored on the Q.
Fig 1. Conventional 6T SRAM Cell.
Before the read operation of “1” at Q (for example) begins, BL and BL bar are pre-charged to as high
as Vdd. When the WL is selected, the access transistors T2 and T5 are turned ON. Because of the pull-up
transistor T1 ON and pull down transistor T3 OFF, voltage of BL will be nearly Vdd. On the other side, current
will flow from the pre-charged BL bar to ground, thus discharging BL bar line through T5-T6 path to ground;
T4 being OFF. Thus, a differential voltage develops between BL and BL bar lines. This small potential
difference between the bit lines is sensed and amplified by the sense amplifier at the data output
B. Conventional 8T SRAM cell:
8T SRAM cell [4] is shown in Figure 2. This cell uses the same 6T SRAM structure for the writing
operation. For reading, it uses a separate bit line, RBL with RWL as its control signal. During writing, the
PMOS and NMOS transistors of the inverters can be maintained at the minimum width as the read operation is
separated. The RBL is read according to the value stored at the storage nodes when RWL is high.
Fig2. Conventional 8T SRAM Cell.
3. A Novel Low Power Energy Efficient SRAM Cell with Reduced Power Consumption
DOI: 10.9790/4200-05114249 www.iosrjournals.org 44 | Page
C. Conventional 9T SRAM cell:
The 9T SRAM [8] is shown in Fig. 3. “Write” occurs just as in the 6T SRAM cell. “Read” occurs
separately through N5, N6 and N7 controlled by the Read Signal RD going high. This design has the problem of
the high bit line capacitance with more pass transistors on the bit line and it can be minimized by placing sleep
transistors on bit line which was explained in section- III.
Fig 3. Conventional 9T SRAM Cell.
III. Proposed MTCMOS SRAM Cell
Low-power and high performance design requirements of modern VLSI technology can be achieved by
using MTCMOS technology. This technique uses low, normal and high threshold voltage transistors in designing
a CMOS circuit. Supply and threshold voltages are reduced with the scaling of CMOS technologies. Lowering of
threshold voltages leads to an exponential increase in the sub threshold leakage current. The low-threshold (Vtl)
transistors which have high performance are used to reduce the propagation delay in the critical path. High-
threshold (Vth) transistors which have less power consumption are used to reduce the power consumption in the
shortest path.
The multi threshold CMOS technology has two main parts. First, “active” and “sleep” operational
modes are associated with MTCMOS technology, for efficient power management. Second, two different
threshold voltages are used for N channel and P channel MOSFET in a single chip. These apply on between the
low threshold voltage (low-Vt) gates from the power supply and the ground line via cut-off high threshold
voltage (high-Vt) sleep transistors is also known as “power gating”. Schematic of power gating technique is
shown in below Fig. 4. And transistor level circuit is shown in Fig. 5 [8].
Fig 4. MTCMOS Technique.
4. A Novel Low Power Energy Efficient SRAM Cell with Reduced Power Consumption
DOI: 10.9790/4200-05114249 www.iosrjournals.org 45 | Page
Operation of 9T MTCMOS SRAM cell is same as conventional 9T SRAM cell as mentioned in section
II – C, there it is having large power dissipation because of high bit line capacitance due to more switching
transitions at bit line node and it can be reduced by placing high threshold transistors (pmos & nmos) between
supply and ground, so that the unwanted and more transitions can be decreased by controlling switching
transistors (Vth) which are placed between power supply and ground.[5],[6].
Fig.5 Proposed MTCMOS SRAM Cell.
IV. Simulation Results
In this section, the total write power dissipations at different voltage levels and static noise margins
(SNM) are calculated and the simulation results are compared to those of other SRAM cells. Analog and
schematic simulations have been done in 65nm environment with the help of Microwind 3.1 by using BSimM4
model.[10].
A. Power Dissipation Analysis:
Table I shows the comparison of total power dissipations (static power dissipation plus dynamic power
dissipation together) of existing SRAM cells and the proposed SRAM cell for write operations in 90nm and
Table II shows results in 65nm. The proposed cell dissipates lesser power than the other existing SRAM cells
even at higher temperatures.
Fig.6 Layout of Proposed MTCMOS SRAM Cell.
5. A Novel Low Power Energy Efficient SRAM Cell with Reduced Power Consumption
DOI: 10.9790/4200-05114249 www.iosrjournals.org 46 | Page
Fig7. Waveform of Proposed 9T MTCMOS SRAM Cell (V vs T).
Fig.8 Waveform Of Proposed 9T MTCMOS SRAM Cell (V Vs I).
Fig9. Id/Vd Characteristics Of Nmos Devices In Low Leakage Mode At Room Temperature.
6. A Novel Low Power Energy Efficient SRAM Cell with Reduced Power Consumption
DOI: 10.9790/4200-05114249 www.iosrjournals.org 47 | Page
Fig10. Id/Vd Characteristics Of Pmos Devices In Low Leakage Mode At Room Temperature.
Fig11. Id/Vd Characteristics Of Nmos Devices In High Speed Mode At Room Temperature.
Fig12. Id/Vd Characteristics Of Pmos Devices In High Speed Mode At Room Temperature.
7. A Novel Low Power Energy Efficient SRAM Cell with Reduced Power Consumption
DOI: 10.9790/4200-05114249 www.iosrjournals.org 48 | Page
Table I. Simulation Results of Different Types of SRAM Cells in 90NM/27o
C
TECHNIQUES AREA
(µm2
)
POWER in
(µw)
DELAY
in (ps)
PDP VALUE (µw
X ns)
Conventional 6T SRAM CELL 180 254 300 76.20
Conventional 8T SRAM CELL 210 256 340 87.04
Conventional 9T SRAM CELL 220 263 330 86.79
Proposed MTCMOS SRAM CELL 360 88.22 475 41.90
Table II. Simulation Results of Different Types of SRAM Cells in 65NM/27o
C
TECHNIQUES AREA
(µm2
)
POWER in
(µw)
DELAY
in (ps)
PDP VALUE (µw
X ns)
Conventional 6T SRAM CELL 112 41.47 228 9.455
Conventional 8T SRAM CELL 128 41.58 262 10.89
Conventional 9T SRAM CELL 136 42.88 240 10.29
Proposed MTCMOS SRAM CELL 252 5.876 370 2.174
Table III. Transistors Required For Implementing SRAM Cell
No.of MOS Transistors Pmos Nmos Total
Conventional 6T SRAM CELL 3 5 8
Conventional 8T SRAM CELL 3 7 10
Conventional 9T SRAM CELL 3 8 11
9T MTCMOS SRAM CELL 5 10 15
Table IV. Power Consumption of 9T MTCMOS SRAM Cell at Various Voltage Levels in 65nm at 27o
C
9T MTCMOS SRAM CELL POWER in (µw)
0.7 V 5.876
1.2 V 218.0
1.8 V 749.0
2.5 V 1584.0
3.3 V 2635.0
5.0 V 5199.0
B. Noise Analysis:
Here Output of 9T MTCMOS SRAM cell is analysed by adding noise at input. Table.V gives the
analysis report between power consumption and noise at various noise levels in 65 nm technology.
Table V. Noise vs Power consumption analysis of 9T MTCMOS SRAM cell in 65nm technology
Noise Level in
(mv)
POWER in (μw)
at VDD=0.7v
10 5.876
20 5.878
30 5.888
40 5.921
50 6.031
60 6.253
70 6.707
80 7.341
90 8.222
100 9.377
From the above table V it is observed that after 50mv of noise input, output starts affecting with noise.
Hence the noise margin for the proposed SRAM cell is 50mv.
C. Graphical Analysis in 90 nm technology:
8. A Novel Low Power Energy Efficient SRAM Cell with Reduced Power Consumption
DOI: 10.9790/4200-05114249 www.iosrjournals.org 49 | Page
D. .Graphical Analysis in 65 nm technology:
V. Conclusion
In this paper, reduction in power consumption which leads to reduction in leakage current and power
dissipation as well as Power Delay product is analyzed for conventional and modified 1-bit SRAM cell using
Microwind / DSCH tool in 90nm and 65nm technologies. It is found that total power consumption of proposed
design with MTCMOS is reduced when compared to other SRAM cells. Hence the proposed SRAM cell with
MTCMOS is Energy Efficient as it`s PDP value is less when compared to other conventional designs. Future
work is carrying out in designing 32Kb RAM with the proposed model.
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