This document discusses the implementation of low power integrators and differentiators using memristors. It presents the mathematical models of memristors and describes how memristor-based integrator and differentiator circuits were designed and simulated. The results show that the memristor-based circuits achieve much lower power consumption in the nano-watt range compared to traditional op-amp based implementations, demonstrating the potential of memristors for low power analog circuit applications.
Implementation of a High Speed and Power Efficient Reliable Multiplier Using ...iosrjce
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Analysis and Comparison of CMOS Comparator At 90 NM TechnologyIJERA Editor
In this paper, A CMOS comparator with low power dissipation is presented. The preamplifier latch comparator is compared with conventional double tail comparator. The comparators designed and simulated in 90nm Cadence virtuoso environment technology. The particular preamplifier latch comparator will be mix of a good amplifier and a latch comparator can easily effect higher velocity and also low electric power dissipation. The proposed circuit topology improves kickback noise and reduces power dissipation compared with a conventional double tail comparator.Analysis are testified and compared with conventional comparator and enhancements are detected in this paper.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
NanoScale TiO2 based Memory Storage Circuit Element:- MemristorAM Publications
four fundamental circuit variable in which relation between charge and flux linkage first introduce by
Prof. Leon Chua in his Research Proposal at IEEE Transaction on circuit theory based on the symmetric
background. However, using this relation he predicted fourth fundamental element which is known as Memristor.
The first NanoScale TiO2 based physical model of Memristor is proposed by Hewlett-Packard Laboratories. Therefore
new research field emerged out “Analog and Digital circuit designing using Memristor”. Still many faults in physical
model of Memristor which has proposed by HP Laboratories. So many challenging researches going on for making
perfect physical model of Memristor. In this paper we review properties of Memristor, the physics behind fourth
fundamental circuit element as well as we discussed first physical model of Memristor introduced by HP. Some
potential application also discussed here and last we proposed major challenges for Memristor development and
which future work can be carried out using Memristor.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Implementation of a High Speed and Power Efficient Reliable Multiplier Using ...iosrjce
IOSR Journal of Electronics and Communication Engineering(IOSR-JECE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of electronics and communication engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in electronics and communication engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Analysis and Comparison of CMOS Comparator At 90 NM TechnologyIJERA Editor
In this paper, A CMOS comparator with low power dissipation is presented. The preamplifier latch comparator is compared with conventional double tail comparator. The comparators designed and simulated in 90nm Cadence virtuoso environment technology. The particular preamplifier latch comparator will be mix of a good amplifier and a latch comparator can easily effect higher velocity and also low electric power dissipation. The proposed circuit topology improves kickback noise and reduces power dissipation compared with a conventional double tail comparator.Analysis are testified and compared with conventional comparator and enhancements are detected in this paper.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
NanoScale TiO2 based Memory Storage Circuit Element:- MemristorAM Publications
four fundamental circuit variable in which relation between charge and flux linkage first introduce by
Prof. Leon Chua in his Research Proposal at IEEE Transaction on circuit theory based on the symmetric
background. However, using this relation he predicted fourth fundamental element which is known as Memristor.
The first NanoScale TiO2 based physical model of Memristor is proposed by Hewlett-Packard Laboratories. Therefore
new research field emerged out “Analog and Digital circuit designing using Memristor”. Still many faults in physical
model of Memristor which has proposed by HP Laboratories. So many challenging researches going on for making
perfect physical model of Memristor. In this paper we review properties of Memristor, the physics behind fourth
fundamental circuit element as well as we discussed first physical model of Memristor introduced by HP. Some
potential application also discussed here and last we proposed major challenges for Memristor development and
which future work can be carried out using Memristor.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
Design of a high frequency low voltage CMOS operational amplifierVLSICS Design
A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.50 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.
A coupled-line balun for ultra-wideband single-balanced diode mixerTELKOMNIKA JOURNAL
A multi-section coupled-line balun design for an ultra-wideband diode mixer is presented in this paper. The multi-section coupled-line balun was used to interface with the diode mixer in which it can deliver a good impedance matching between the diode mixer and input/output ports. The mixer design operates with a Local Oscillator (LO) power level of 10 dBm, Radio Frequency (RF) power level of -20 dBm and Intermediate Frequency (IF) of 100 MHz with the balun characteristic of 180° phase shift over UWB frequency (3.1 to 10.6 GHz), the mixer design demonstrated a good conversion loss of -8 to -16 dB over the frequency range from 3.1 to 10.6 GHz. Therefore, the proposed multi-section coupled-line balun for application of UWB mixer showed a good isolation between the mixer’s ports.
Analysis and Control of Wind Driven Self-Excited Induction Generator for Isol...IDES Editor
For isolated applications, the 3- self-excited
induction generator driven by wind energy source is more
suitable, where the minimum excitation capacitance required
for self-excitation of 3- induction generator is taken up in
this work and the detailed analysis is carried out to determine
the range of wind speed variation and consumer demand for
the designed capacitance value. An electronic load controller
is designed to maintain the load voltage constant for these
variations. The excess power resulting as a consequence of
rise in load voltage due to variation in load is pumped to dump
load along with battery storage. Simulation for battery feeding
the consumer load in the absence of wind power has been
undergone. Exhaustive simulations have been carried out for
such a scheme and the results have been presented in this
paper.
Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Ap...IJERA Editor
In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18μm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318μw. In addition we have verified present results with schematic view design and also compared these results with earlier reported work and got improvement in this reported work.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A Novel Structure of a Wideband Zero-bias Power Limiter for ISM BandTELKOMNIKA JOURNAL
In this paper, a new broadband microwave microstrip power limiter is designed and realized. The
Power Limiter is based on microstrip technology integrating a Zero Bias commercial Schottky diodes
HSMS2820.The power limiter is optimized and validated in two steps. The enhanced and achieved circuit
is obtained by concatenating two basic structures. The final circuit was validated into simulation by using
ADS solver. Finally this circuit was realized and tested. Simulation and measurement results are in a good
agreement. The final circuit achieves a limiting rate of 14 dB with a threshold input power level of 0 dBm
until a maximum input power level of 30 dBm.
Wireless power transfer (WPT) is a technique introduced to transfer power wirelessly. Generally, WPT systems are characterized by low efficiency and low output power. Since WPT process depends mainly on mutual coupling between transmitting and receiving coils in addition to load requirements, it is focused in this work toward enhancing the mutual coupling and conditioning the receiving circuit so as to optimally satisfy the load demand. The mutual coupling between transmitting and receiving nodes is enhanced via inserting three resonating circuits along with energy transmission path and conditioning the receiving circuit such that it accomplishes delivering maximum power to the load node. In this work, an adaptive efficient WPT system is introduced. This system is carried out on PSpice and validated experimentally. Both simulative and experimental WPT systems have accomplished significant enhancement in efficiency. The proposed WPT system has three resonators and three parallel connected identical receiving coils located at 6.61m from the power transmitter. The efficiency enhancement approaches thousands of times the efficiency of a conventional WPT system having similar power transmitter located at the same distance from the receiving circuit, which has a single coil identical to those in the proposed efficient WPT system.
Learn more about Master Bond's outstanding epoxy compound featuring excellent chemical resistance. Epoxy system EP62-1 is sure to meet the needs of your challenging application.
Master Bond's Commitment to SustainabilityMaster Bond
Our Research & Development department continuously explores developing new lines of products that are environmentally friendly and offer more value for our customers—more durable, lighter, higher performance.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
Design of a high frequency low voltage CMOS operational amplifierVLSICS Design
A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.50 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.
A coupled-line balun for ultra-wideband single-balanced diode mixerTELKOMNIKA JOURNAL
A multi-section coupled-line balun design for an ultra-wideband diode mixer is presented in this paper. The multi-section coupled-line balun was used to interface with the diode mixer in which it can deliver a good impedance matching between the diode mixer and input/output ports. The mixer design operates with a Local Oscillator (LO) power level of 10 dBm, Radio Frequency (RF) power level of -20 dBm and Intermediate Frequency (IF) of 100 MHz with the balun characteristic of 180° phase shift over UWB frequency (3.1 to 10.6 GHz), the mixer design demonstrated a good conversion loss of -8 to -16 dB over the frequency range from 3.1 to 10.6 GHz. Therefore, the proposed multi-section coupled-line balun for application of UWB mixer showed a good isolation between the mixer’s ports.
Analysis and Control of Wind Driven Self-Excited Induction Generator for Isol...IDES Editor
For isolated applications, the 3- self-excited
induction generator driven by wind energy source is more
suitable, where the minimum excitation capacitance required
for self-excitation of 3- induction generator is taken up in
this work and the detailed analysis is carried out to determine
the range of wind speed variation and consumer demand for
the designed capacitance value. An electronic load controller
is designed to maintain the load voltage constant for these
variations. The excess power resulting as a consequence of
rise in load voltage due to variation in load is pumped to dump
load along with battery storage. Simulation for battery feeding
the consumer load in the absence of wind power has been
undergone. Exhaustive simulations have been carried out for
such a scheme and the results have been presented in this
paper.
Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Ap...IJERA Editor
In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18μm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318μw. In addition we have verified present results with schematic view design and also compared these results with earlier reported work and got improvement in this reported work.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A Novel Structure of a Wideband Zero-bias Power Limiter for ISM BandTELKOMNIKA JOURNAL
In this paper, a new broadband microwave microstrip power limiter is designed and realized. The
Power Limiter is based on microstrip technology integrating a Zero Bias commercial Schottky diodes
HSMS2820.The power limiter is optimized and validated in two steps. The enhanced and achieved circuit
is obtained by concatenating two basic structures. The final circuit was validated into simulation by using
ADS solver. Finally this circuit was realized and tested. Simulation and measurement results are in a good
agreement. The final circuit achieves a limiting rate of 14 dB with a threshold input power level of 0 dBm
until a maximum input power level of 30 dBm.
Wireless power transfer (WPT) is a technique introduced to transfer power wirelessly. Generally, WPT systems are characterized by low efficiency and low output power. Since WPT process depends mainly on mutual coupling between transmitting and receiving coils in addition to load requirements, it is focused in this work toward enhancing the mutual coupling and conditioning the receiving circuit so as to optimally satisfy the load demand. The mutual coupling between transmitting and receiving nodes is enhanced via inserting three resonating circuits along with energy transmission path and conditioning the receiving circuit such that it accomplishes delivering maximum power to the load node. In this work, an adaptive efficient WPT system is introduced. This system is carried out on PSpice and validated experimentally. Both simulative and experimental WPT systems have accomplished significant enhancement in efficiency. The proposed WPT system has three resonators and three parallel connected identical receiving coils located at 6.61m from the power transmitter. The efficiency enhancement approaches thousands of times the efficiency of a conventional WPT system having similar power transmitter located at the same distance from the receiving circuit, which has a single coil identical to those in the proposed efficient WPT system.
Learn more about Master Bond's outstanding epoxy compound featuring excellent chemical resistance. Epoxy system EP62-1 is sure to meet the needs of your challenging application.
Master Bond's Commitment to SustainabilityMaster Bond
Our Research & Development department continuously explores developing new lines of products that are environmentally friendly and offer more value for our customers—more durable, lighter, higher performance.
Two Component Epoxy Meets UL 94V-0 Specifications for Flame RetardancyMaster Bond
Featuring a non-halogen filler, Master Bond EP21FRNS-2 passes UL 94V-0 testing for flame retardancy in potting, encapsulation and casting applications. It produces very low smoke levels and is well suited for the computer, aerospace and related industries. EP21FRSN-2 is a room temperature curing two component epoxy system that resists high temperatures up to 90°C.
Can your thermally conductive epoxy do this?Master Bond
Master Bond’s Supreme 10AOHT-LO features high peel and shear strengths, superior electrical insulation properties and a thermal conductivity of 9-10 BTU/in/ft²/hr/°F. It has a service temperature range of 4K to +400°F. This one part system is resistant to impact, thermal shock, vibration and stress fatigue cracking while meeting NASA low outgassing requirements. It is used in applications ranging from optoelectronic assemblies to satellite assembly and repair.
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Master Bond offers its extensive product line in a variety of convenient standard and specialty packing options. Standard options include cans, tubes, jars, pails and bottles. Specialty packaging consists of syringes, cartridges, bubble packs, gun applicators, premixed and frozen syringes, semkits and preforms.
Get to know the facts on EP21TCHT-1, a cryogenically serviceable epoxy that can withstand temperatures from 4K to +400°F. This non-drip system also passes NASA low outgassing tests and offers superior resistance to chemicals, especially acids and bases.
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Coating Compounds for EMI/RFI Shielding ApplicationsMaster Bond
Prevent malfunctions of electronic devices with conductive coatings for EMI/RFI shielding applications developed by Master Bond. From epoxy adhesives and sealants to silicones and sodium silicates, we have a wide range of formulations to meet the ever changing needs of devices requiring EMI/RFI shielding.
Master Bond Milestones Through the Decades - Part 2Master Bond
Take a walk down memory lane as Master Bond as we celebrate our 40th anniversary and the important achievements we’ve had over the years. From formulating our first product in the 1970s to the introduction of 28 USP Class VI approved adhesives in the 2010s, learn more about how our company and products have evolved.
What is Green Finance? How to structure a market to attrach green investments? Which are the instruments and mechanism to make it succesfull operative and monitorable?
Distortion Analysis of Differential AmplifierIOSR Journals
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-μm CMOS process technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-channel effects, small signal analysis, transient analysis.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of High-Speed Dynamic Double-Tail ComparatorIJERDJOURNAL
ABSTRACT:- The analog-to-digital converters which are of ultra low-power, area efficient, and high speed converters are made of dynamic regenerative comparators. These comparators can maximize speed and power efficiency. The delay and power dissipation of dynamic comparators are analyzed in this paper. The delays and tradeoff can be explored. The circuit of a conventional double tail comparator in this analysis is modified for fast operation even in different supply voltages. By using power gating technique and adding few transistors, the positive feedback during the regeneration is strengthened in the proposed comparator structure. The delay time can be reduced by providing positive feedback instead of adding few transistors. The analysis results are going to be confirmed on the basis of 0.25-µm CMOS technology. The power consumption and delay time can be significantly reduced based on this analysis. All the simulation are made using TANNER TOOLS, Generic 250nm. The schematic are drawn in the T-SPICE schematic editor.
A Novel Design of a Microstrip Microwave Power Amplifier for DCS Application ...IJECEIAES
This paper presents a 1.80GHz class-A Microwave power amplifier (PA). The proposed power amplifier is designed with single-stage architecture. This power amplifier consists of a bipolar transistor and improved by Collector-Feedback Biasing fed with a single power supply. The aim of this work is to improve the performance of this amplifier by using simple stubs with 50Ω microstrip transmissions lines. The proposed PA is investigated and optimized by utilizing Advanced Design System (ADS) software. The simulation results show that the amplifier achieves a high power gain of 13dB, output power rise up to 21dBm and good impedances matching ;For the input reflection coefficient (S11) is below than - 46.39dB. Regarding the output reflection coefficient (S22) is below than -29.898dB, with an overall size of about 93 x 59mm². By the end; we find that this power amplifier offers an excellent performance for DCS applications.
Design of 6 bit flash analog to digital converter using variable switching vo...VLSICS Design
This paper presents the design of 6-bit flash analog to digital Converter (ADC) using the new variable
switching voltage (VSV) comparator. In general, Flash ADCs attain the highest conversion speed at the
cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits
significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation
result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of
1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral
nonlinearities (DNL and INL) of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
Carbon nano tube based delay model for high speed energy efficient on chip da...elelijjournal
Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect.The inductive effect is dominant at lower technology node is modelled into an equivalent resistance. In this model first order transfer function is designed using finite difference equation, and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. Using CNIA tool (carbon nanotube interconnect analyzer) the interconnect line parameters has been estimated at 45nm technology node. The novel proposed current mode model superiority has been validated for CNT type of material. It superiority factor remains to 66.66% as compared to voltage mode signalling. And current mode dissipates 0.015pJ energy where as VM consume 0.045pJ for a single bit transmission across the interconnect over CNT
material. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
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journal of engineering, online Submission
A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
In this paper a Double Cross Coupled Inductor capacitor based Voltage Control Oscillator (LC-VCO) is designed. In the proposed circuit the phase noise, tuning range with respect to control voltage, output power and the power dissipation of the circuit is analysed. Phase noise of approximate -96 dBc/Hz at frequency of 1MHz, frequency tuning range of 4.8 to 8.3 GHz (corresponding to 53.0% tuning range) obtained by varying the control voltage from 0 to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm resistance terminal and the power consumption of Circuit is 3.8 mW. This VCO are designed for 5.5 GHz. The circuit is designed on the UMC 180nm CMOS technology and all the simulation results are obtained using cadence SPECTRE Simulator.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.