Quantum-dot cellular automata are a prominent part of the nanoscale regime. They
use a quantum cellular based architecture which enables rapid information process with high
device density. This paper targets the two kinds of novel error control circuits such as Hamming
code, parity generator and checker. To design the HG-PP (HG = Hamming gate, PP = parity
preserving), NG-PP (NG = new gate) are proposed for optimising the circuits. Based on the
proposed gates and a few existing gates, the Hamming code and parity generator and checker
circuits are constructed. The proposed gates have been framed and verified in QCA. The
simulation outcomes signify that their framed circuits are faultless. In addition to verification,
physical reversible is done. The reversible major metrics such as gate count, quantum cost, unit
delay, and garbage outputs, uses best optimisation results compared to counterparts. They can be utilised as a low power error control circuit applied in future communication systems.
A novel vedic divider based crypto-hardware for nanocomputing paradigm: An ex...VIT-AP University
Restoring and non-restoring divider has become widely applicability in the era of digital computing application due to its computation speed. In this paper, we have proposed the design of divider of different architecture for the computation of Vedic sutra based. The design of divider in the Vedic mode results in
high computation throughput due to its replica architecture, where latency is minimized in each of the replica stages. The proposed novel divider based symmetric key crypto-hardware architecture for lightweight embedded devices and the results obtained for this architecture by the analysis using the QCADesigner tool. For the physical environment in QCA computing paradigm are achieved through optimization the
architecture of cell by using the robust design computing architecture. For the extended perspective of lower
divider to higher divider and to synthesize, target outcomes by using efficient architecture.
A modular approach for testable conservative reversible multiplexer circuit f...VIT-AP University
Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent
part of any system-level design. In this article, the significant module of a multiplexer, an extended to n:1 is framed with
prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm,
which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing
framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative
reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters
in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count,
quantum cost and unit delay are optimal.
IMPLEMENTATION OF EFFICIENT ADDER USING MULTI VALUE LOGIC TECHNIQUEJournal For Research
The digital logic circuits are restricted for the requirement of interconnections. This difficulty overcomes by using a big set of signals over the same chip area. Multiple-valued logic (MVL) designs contain more importance from that perspective. This paper gives the fabrication of a multiple-valued half adder and full adder circuits. This technique advantageous for large scale circuits due to which large power dissipation with increased speed can lead to the development of extremely low energy circuit’s use for the high performance required for number of applications. Multiple-valued logic (MVL) designs are gaining more advantageous from the design of a multiple-valued half adder and full adder circuits. The presented adders are design in Multiple-Valued voltage-Mode Logic (MV-VML). In quaternary half adder, quaternary logic levels are exploited for the intention of addition. Addition operation is executed with minimum number of gates and less depth of net. The design is targeted for the 0.18 μm CMOS technology. Circuit is design by using Advanced Design System software {ADS software}. In this paper we try to find area, power and speed of the design HAq / FAq without any need of conversion, and compare to existing binary circuits [HAb / FAb].
Adiabatic technique based low power synchronous counter designIJECEIAES
The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in synchronous counters, and its high-power consumption impacts the overall effectiveness of the system. This paper calculates the power dissipation (PD), power delay product (PDP), and latency of the presented T flip-flop. To create a 2-bit synchronous counter based on the novel T flip-flops, a performance matrix such as PD, latency, and PDP is analyzed. The analysis is carried out at 100 and 10 MHz frequencies with varying temperatures and operating voltages. It is observed that the presented counter design has a lesser power requirement and PDP compared to the existing counter architectures. The proposed T-flip-flop design at the 45 nm technology node shows an improvement of 30%, 76%, and 85% in latency, PD, and PDP respectively to the 180 nm node at 10 MHz frequency. Similarly, the proposed counter at the 45 nm technology node shows 96% and 97% improvement in power dissipation, delay, and PDP respectively compared to the 180 nm at 10 MHz frequency.
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Envi...VIT-AP University
Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
Design of magnetic dipole based 3D integration nano-circuits for future elect...VIT-AP University
Nano Magnetic Logic (NML) has been attracting application in optical computing, nanodevice formation, and low power. In this paper nanoscale architecture such as the decoder, multiplexer, and comparator are implemented on perpendicular-nano magnetic logic (pNML) technology. All these architectures with the superiority of minimum complexity and minimum delay are pointed. The proposed architectures have been designed using pNML in MagCAD tool, simulated with modelsim platform and correctness shown by simulation waveform. The correctness of these designs can be verified easily when Verilog code is generated from MagCAD tool. The performance of the proposed comparator towards default parameters shows the area of 2.4336 μm2 and critical path of 1.5E-7 sec. As a higher order, the realization of a 4-to-1 multiplexer in NML has also been included in this work.
A novel vedic divider based crypto-hardware for nanocomputing paradigm: An ex...VIT-AP University
Restoring and non-restoring divider has become widely applicability in the era of digital computing application due to its computation speed. In this paper, we have proposed the design of divider of different architecture for the computation of Vedic sutra based. The design of divider in the Vedic mode results in
high computation throughput due to its replica architecture, where latency is minimized in each of the replica stages. The proposed novel divider based symmetric key crypto-hardware architecture for lightweight embedded devices and the results obtained for this architecture by the analysis using the QCADesigner tool. For the physical environment in QCA computing paradigm are achieved through optimization the
architecture of cell by using the robust design computing architecture. For the extended perspective of lower
divider to higher divider and to synthesize, target outcomes by using efficient architecture.
A modular approach for testable conservative reversible multiplexer circuit f...VIT-AP University
Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent
part of any system-level design. In this article, the significant module of a multiplexer, an extended to n:1 is framed with
prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm,
which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing
framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative
reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters
in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count,
quantum cost and unit delay are optimal.
IMPLEMENTATION OF EFFICIENT ADDER USING MULTI VALUE LOGIC TECHNIQUEJournal For Research
The digital logic circuits are restricted for the requirement of interconnections. This difficulty overcomes by using a big set of signals over the same chip area. Multiple-valued logic (MVL) designs contain more importance from that perspective. This paper gives the fabrication of a multiple-valued half adder and full adder circuits. This technique advantageous for large scale circuits due to which large power dissipation with increased speed can lead to the development of extremely low energy circuit’s use for the high performance required for number of applications. Multiple-valued logic (MVL) designs are gaining more advantageous from the design of a multiple-valued half adder and full adder circuits. The presented adders are design in Multiple-Valued voltage-Mode Logic (MV-VML). In quaternary half adder, quaternary logic levels are exploited for the intention of addition. Addition operation is executed with minimum number of gates and less depth of net. The design is targeted for the 0.18 μm CMOS technology. Circuit is design by using Advanced Design System software {ADS software}. In this paper we try to find area, power and speed of the design HAq / FAq without any need of conversion, and compare to existing binary circuits [HAb / FAb].
Adiabatic technique based low power synchronous counter designIJECEIAES
The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in synchronous counters, and its high-power consumption impacts the overall effectiveness of the system. This paper calculates the power dissipation (PD), power delay product (PDP), and latency of the presented T flip-flop. To create a 2-bit synchronous counter based on the novel T flip-flops, a performance matrix such as PD, latency, and PDP is analyzed. The analysis is carried out at 100 and 10 MHz frequencies with varying temperatures and operating voltages. It is observed that the presented counter design has a lesser power requirement and PDP compared to the existing counter architectures. The proposed T-flip-flop design at the 45 nm technology node shows an improvement of 30%, 76%, and 85% in latency, PD, and PDP respectively to the 180 nm node at 10 MHz frequency. Similarly, the proposed counter at the 45 nm technology node shows 96% and 97% improvement in power dissipation, delay, and PDP respectively compared to the 180 nm at 10 MHz frequency.
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Envi...VIT-AP University
Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
Design of magnetic dipole based 3D integration nano-circuits for future elect...VIT-AP University
Nano Magnetic Logic (NML) has been attracting application in optical computing, nanodevice formation, and low power. In this paper nanoscale architecture such as the decoder, multiplexer, and comparator are implemented on perpendicular-nano magnetic logic (pNML) technology. All these architectures with the superiority of minimum complexity and minimum delay are pointed. The proposed architectures have been designed using pNML in MagCAD tool, simulated with modelsim platform and correctness shown by simulation waveform. The correctness of these designs can be verified easily when Verilog code is generated from MagCAD tool. The performance of the proposed comparator towards default parameters shows the area of 2.4336 μm2 and critical path of 1.5E-7 sec. As a higher order, the realization of a 4-to-1 multiplexer in NML has also been included in this work.
Efficient architecture for arithmetic designs using perpendicular NanoMagneti...VIT-AP University
As the process of scaling down continues at a rapid pace, there is a growing need for an alternative semiconductor device to replace CMOS. One of the alternatives that attracted a lot of attention is called nanomagnetic logic (NML). This is because NML delivers a high device density in addition to a non-volatility of stored information, beyond-CMOS technologies, and device work at room temperature. It is necessary to lower the circuit density and increase the speed of circuits like adders. Using emerging NML logic, we created a full-adder, and ripple carry adder (RCA) with a minimum area. As a result, the invented multilayer-based decimal design makes use of RCA, and full-adder, for innovative 3D topology. We used an NML framework built with perpendicular nanomagnetic (pNML) layers to simulate the characteristics of these devices. With the adder designs that have been offered the latency values are relatively low while performing exhaustive testing. Using pNML technology, a decimal adder has been constructed for the first time in the literature. In addition, simulations are carried out with the help of the Modelsim simulator. During the process of nanomagnetic designing consideration is given to both of these aspects as latency and area. To create an NML circuit, the tool MagCAD is employed. Results are better using the pNML environment-based full adder, RCA and decimal adder.
Approach to design a high performance fault-tolerant reversible ALUVIT-AP University
In the digital circuit design, the primary factors are low power and a high packing density. The reversible logic circuit in quantum-dot cellular
automata (QCA) framework is hoped to be effective in addressing the factor of power consumption at nanoscale regime. Fault tolerant circuits are suited of interruption of errors at the outputs. This manuscript focuses the design of ALU in QCA-based and propose new parity preserving gate. It has been introduced that new reversible gate, namely, universal parity preserving gate (UPPG), to
optimise the ALU circuits. An algorithm and lemmas are shown in designing ALU. The ALU generates a number of arithmetic and logical function with using only less architectural complexity. Most importantly circuit design
focuses on optimising the gate count and quantum cost. In addition to optimisation, the workability of UPPG gate is tested by QCA and the simulation result obtained ensures the correctness of the design.
High Performance Binary to Gray Code Converter using Transmission GATE IJEEE
This paper gives an idea to improve power efficiency and effective area of binary to gray code converter using very popular transmission gate technology. Some sensors send information in gray code. So this must be important to convert a given binary stream into its equivalent gray code. In this paper the binary to gray code converter has been developed using gate, circuit level. The conversion has been done using conventional and transmission gate level and comparing these two in terms of power, number of transistors used and last but not the least area. The simulation result shows that binary to gray code converter using transmission gate has improved power efficiency and area by 76.22% and 72.3% respectively .This paper gives the true comparison between transmission gate and conventional gate implemented binary to gray code converter in many aspects like power, area, and number of transistors used for fully automatic and semicustom layout design.
EEIT2-F: energy-efficient aware IT2-fuzzy based clustering protocol in wirel...IJECEIAES
Improving the network lifetime is still a vital challenge because most wireless sensor networks (WSNs) run in an unreached environment and offer almost impossible human access and tracking. Clustering is one of the most effective methods for ensuring that the relevant device process takes place to improve network scalability, decrease energy consumption and maintain an extended network lifetime. Many researches have been developed on the numerous effective clustering algorithms to address this problem. Such algorithms almost dominate on the cluster head (CH) selection and cluster formation; using the intelligent type1 fuzzy-logic (T1-FL) scheme. In this paper, we suggest an interval type2 FL (IT2-FL) methodology that assumes uncertain levels of a decision to be more efficient than the T1-FL model. It is the so-called energy-efficient interval type2 fuzzy (EEIT2-F) low energy adaptive clustering hierarchical (LEACH) protocol. The IT2-FL system depends on three inputs of the residual energy of each node, the node distance from the base station (sink node), and the centrality of each node. Accordingly, the simulation results show that the suggested clustering protocol outperforms the other existing proposals in terms of energy consumption and network lifetime.
Dynamic resource allocation for opportunistic software-defined IoT networks: s...IJECEIAES
Several wireless technologies have recently emerged to enable efficient and scalable Internet-of-Things (IoT) networking. Cognitive radio (CR) technology, enabled by software-defined radios, is considered one of the main IoT-enabling technologies that can provide opportunistic wireless access to a large number of connected IoT devices. An important challenge in this domain is how to dynamically enable IoT transmissions while achieving efficient spectrum usage with a minimum total power consumption under interference and traffic demand uncertainty. Toward this end, we propose a dynamic bandwidth/channel/power allocation algorithm that aims at maximizing the overall network’s throughput while selecting the set of power resulting in the minimum total transmission power. This problem can be formulated as a two-stage binary linear stochastic programming. Because the interference over different channels is a continuous random variable and noting that the interference statistics are highly correlated, a suboptimal sampling solution is proposed. Our proposed algorithm is an adaptive algorithm that is to be periodically conducted over time to consider the changes of the channel and interference conditions. Numerical results indicate that our proposed algorithm significantly increases the number of simultaneous IoT transmissions compared to a typical algorithm, and hence, the achieved throughput is improved.
Regular clocking scheme based design of cost-efficient comparator in QCAnooriasukmaningtyas
Quantum-dot cellular automata (QCA) gained a notable attraction in the emerging nanotechnology to get the better of power consumption, density, nano-scale design, the performance of the present CMOS technology. Many designs had been proposed in QCA for an arithmetic circuit like adder, divider, parity checker and comparator etc. Most of the designs have been facing the challenges of cost efficiency, power dissi-pation, device density etc. However, consideration of design automation, underlying clocking layout and integration of the sub modules are the most important which has a direct impact on the fabrication of the design. This work proposed a novel cost ef-fective and power aware comparator design, which is an essential segment in central processing unit (CPU). The noticeable novelty of the design was the use of underlying regular clocking scheme. A new scalable, regular clocking scheme has been utilized in the coplanar design of the comparator which enables regular or uniform cell layout of QCA circuit. It also exhibited the significant improvement over existing counterparts having irregular clocking in terms of area and latency. QCADesigner was used to test and verify the functionality of the circuit and by using QCAPro the power dissipation has been analyzed.
Wireless communication without pre shared secrets using spread spectrum techn...eSAT Journals
Abstract
The wireless communication using spread spectrum relies on the assumption that some secret is shared among source and
destination node before communication or transmission has started. This problem is called the circular dependency problem
(CDP). This CDP exists in large networks, where nodes frequently join and leaves the network. In this work we have introduced
an efficient and reliable mechanism called Advanced Encryption Standard (AES) Algorithm, to overcome circular dependency
problem (CDP). This is an efficient algorithm to make successful transmission of data without pre-sharing any secret key. We
have evaluated this by simulation in Matrix Laboratory (MATLAB).
Keywords: -Spread spectrum, CDP, AES and MATLAB.
Study and Performance Analysis of MOS Technology and Nanocomputing QCAVIT-AP University
One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based
information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits
and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.
PARALLEL BIJECTIVE PROCESSING OF REGULAR NANO SYSTOLIC GRIDS VIA CARBON FIELD...ijcsit
New implementations for parallel processing applications using reversible systolic networks and the
corresponding nano and field-emission controlled-switching components is introduced. The extensions of
implementations to many-valued field-emission systolic networks using the introduced reversible systolic
architectures are also presented. The developed implementations are performed in the reversible domain to
perform the required parallel computing. The introduced systolic systems utilize recent findings in field
emission and nano applications to implement the function of the basic reversible systolic network using
nano controlled-switching. This includes many-valued systolic computing via carbon nanotubes and carbon
field-emission techniques. The presented realization of reversible circuits can be important for several
reasons including the reduction of power consumption, which is an important specification for the system
design in several future and emerging technologies, and also achieving high performance realizations. The
introduced implementations for non-classical systolic computation are new and interesting for the design
within modern technologies that require optimal design specifications of high speed, minimum power and
minimum size, which includes applications in adiabatic low-power signal processing.
Intrusion Detection and Countermeasure in Virtual Network Systems Using NICE ...IJERA Editor
The cloud computing has increased in many organizations. It provides many benefits in terms of low cost and accessibility of data. Ensuring the security of cloud computing is a major factor in the cloud computing environment, as users often store sensitive information with cloud storage providers but these providers may be untrusted. In this project we propose anIntrusion Detection and Countermeasure in Virtual Network Systems mechanism called NICE to prevent vulnerable virtual machines from being compromised in the cloud. NICE detects and mitigates collaborative attacks in the cloud virtual networking environment. The system performance evaluation demonstrates the feasibility of NICE and shows that the proposed solution can significantly reduce the risk of the cloud system from being exploited and abused by internal and external attackers.
Miniaturization, cost, functionality, complexity and power dissipation are important and necessary design traits which need attention in circuit designing. There is a trade off between miniaturization and power dissipation. Smart technology is always searching for new paradigms to continue improve power dissipation. Reversible logic is one of smart computing deployed to avoid power dissipation. Researchers have proposed many reversible logic-based arithmetic and logic units (ALU). However, the research in the area of fault tolerant ALU is still under progress. The aim of this paper is to bridge the knowledge gap for a new researcher in area of fault tolerance using parity preserving logic gates rather than searching huge data through various sources. This paper also presents a high functionality based novel fault tolerant arithmetic and logic unit architecture. A comparison on optimization aspects is presented in tabular form and results shows that proposed ALU architecture is optimum balance in terms of all aspects of reversible logic synthesis. The proposed ALU architecture is coded in Verilog HDL and simulated using Xilinx ISE design suit 14.2 tool. The quantum cost of all gates used in proposed architecture is verified using RCViewer + tool.
The increasing demand for faster, robust, and efficient device development of enabling technology to mass production of industrial research in circuit design deals with challenges like size, efficiency, power, and scalability. This paper, presents a design and analysis of low power high speed full adder using negative capacitance field effecting transistors. A comprehensive study is performed with adiabatic logic and reversable logic. The performance of full adder is studied with metal oxide field effect transistor (MOSFET) and negative capacitance field effecting (NCFET). The NCFET based full adder offers a low power and high speed compared with conventional MOSFET. The complete design and analysis are performed using cadence virtuoso. The adiabatic logic offering low delay of 0.023 ns and reversable logic is offering low power of 7.19 mw.
The impact of quantum computing has been widely recognised in the engineering domain. The age of quantum computing has arrived, and with it comes the ability to easily solve exponential problems. This book is written by me to meet current academic demands. The book is designed to address the most important aspects of the subject of Quantum Computing. The publication of the book "Quantum Computing" is the culmination of numerous years of research and teaching in academia. It is given in a way that is straightforward to comprehend. The undergraduates, and graduate students may all benefit from reading this book. We have given our very best effort to bring you accurate book material.
The book explains the fundamentals of this topic in simple, straightforward language. The most efficient approach to go through this book is to grasp the underlying fundamental as well as mathematical concepts. The chapters are meant to stand on their own. This book is not intended to be theoretical; rather, it will serve to familiarise you with the fundamental of quantum computing, like applications, multiple-qubit systems, quantum state transformations, quantum gates and quantum circuits, tools for quantum computing, bell states, quantum Parallelism, quantum Algorithms: Shor’s Algorithm, Grover’s Algorithm, Quantum Hardware and software, Quantum Cryptography and Security, Quantum Error Rates and Quantum Noise, Quantum Fourier Transform, Quantum Machine Learning and so on.
The model questions and multiple-choice questions that are provided at the end of the book have been chosen to improve readers' understanding, as well as their performance in exams and key employment.
We warmly welcome and would be very appreciative of any comments or recommendations, that will help us enhance the overall quality of the book.
Cost-effective architecture of decoder circuits and futuristic scope in the e...VIT-AP University
The goal of Very Large Scale Integration (VLSI) over the past several decades has been the miniaturisation of chip size, along with increased computing speed and decreased power consumption. Miniaturization of size, high computing speed, and low power consumption does not appear to be able to meet the demand of consumers at this time. Quantum dot cellular automata is a more promising methodology that has the potential to optimise power, speed, and area at the nano-computing scale. In the field of nanocomputing, combinational circuit design has seen a significant amount of research and development effort. This article presents a comprehensive review as well as a proposed design of a decoder that has an accurate clocking mechanism and the best design. In terms of cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost, the novel 2-to-4 decoder achieves values of 87, 0.10, 0.0281, 28.1, 2.5, 0.625, 0.25, which is better than the prior work. Comparing the 2-to-4 decoder design to a standard design, the improvement is 72.64 %, 80 %, 72.71 %, 28.1 %, 64.28 %, 97,44 and 92.85 % in cell count, total area, cell area, area coverage, latency, QCA cost, and Quantum cost, respectively.
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Efficient architecture for arithmetic designs using perpendicular NanoMagneti...VIT-AP University
As the process of scaling down continues at a rapid pace, there is a growing need for an alternative semiconductor device to replace CMOS. One of the alternatives that attracted a lot of attention is called nanomagnetic logic (NML). This is because NML delivers a high device density in addition to a non-volatility of stored information, beyond-CMOS technologies, and device work at room temperature. It is necessary to lower the circuit density and increase the speed of circuits like adders. Using emerging NML logic, we created a full-adder, and ripple carry adder (RCA) with a minimum area. As a result, the invented multilayer-based decimal design makes use of RCA, and full-adder, for innovative 3D topology. We used an NML framework built with perpendicular nanomagnetic (pNML) layers to simulate the characteristics of these devices. With the adder designs that have been offered the latency values are relatively low while performing exhaustive testing. Using pNML technology, a decimal adder has been constructed for the first time in the literature. In addition, simulations are carried out with the help of the Modelsim simulator. During the process of nanomagnetic designing consideration is given to both of these aspects as latency and area. To create an NML circuit, the tool MagCAD is employed. Results are better using the pNML environment-based full adder, RCA and decimal adder.
Approach to design a high performance fault-tolerant reversible ALUVIT-AP University
In the digital circuit design, the primary factors are low power and a high packing density. The reversible logic circuit in quantum-dot cellular
automata (QCA) framework is hoped to be effective in addressing the factor of power consumption at nanoscale regime. Fault tolerant circuits are suited of interruption of errors at the outputs. This manuscript focuses the design of ALU in QCA-based and propose new parity preserving gate. It has been introduced that new reversible gate, namely, universal parity preserving gate (UPPG), to
optimise the ALU circuits. An algorithm and lemmas are shown in designing ALU. The ALU generates a number of arithmetic and logical function with using only less architectural complexity. Most importantly circuit design
focuses on optimising the gate count and quantum cost. In addition to optimisation, the workability of UPPG gate is tested by QCA and the simulation result obtained ensures the correctness of the design.
High Performance Binary to Gray Code Converter using Transmission GATE IJEEE
This paper gives an idea to improve power efficiency and effective area of binary to gray code converter using very popular transmission gate technology. Some sensors send information in gray code. So this must be important to convert a given binary stream into its equivalent gray code. In this paper the binary to gray code converter has been developed using gate, circuit level. The conversion has been done using conventional and transmission gate level and comparing these two in terms of power, number of transistors used and last but not the least area. The simulation result shows that binary to gray code converter using transmission gate has improved power efficiency and area by 76.22% and 72.3% respectively .This paper gives the true comparison between transmission gate and conventional gate implemented binary to gray code converter in many aspects like power, area, and number of transistors used for fully automatic and semicustom layout design.
EEIT2-F: energy-efficient aware IT2-fuzzy based clustering protocol in wirel...IJECEIAES
Improving the network lifetime is still a vital challenge because most wireless sensor networks (WSNs) run in an unreached environment and offer almost impossible human access and tracking. Clustering is one of the most effective methods for ensuring that the relevant device process takes place to improve network scalability, decrease energy consumption and maintain an extended network lifetime. Many researches have been developed on the numerous effective clustering algorithms to address this problem. Such algorithms almost dominate on the cluster head (CH) selection and cluster formation; using the intelligent type1 fuzzy-logic (T1-FL) scheme. In this paper, we suggest an interval type2 FL (IT2-FL) methodology that assumes uncertain levels of a decision to be more efficient than the T1-FL model. It is the so-called energy-efficient interval type2 fuzzy (EEIT2-F) low energy adaptive clustering hierarchical (LEACH) protocol. The IT2-FL system depends on three inputs of the residual energy of each node, the node distance from the base station (sink node), and the centrality of each node. Accordingly, the simulation results show that the suggested clustering protocol outperforms the other existing proposals in terms of energy consumption and network lifetime.
Dynamic resource allocation for opportunistic software-defined IoT networks: s...IJECEIAES
Several wireless technologies have recently emerged to enable efficient and scalable Internet-of-Things (IoT) networking. Cognitive radio (CR) technology, enabled by software-defined radios, is considered one of the main IoT-enabling technologies that can provide opportunistic wireless access to a large number of connected IoT devices. An important challenge in this domain is how to dynamically enable IoT transmissions while achieving efficient spectrum usage with a minimum total power consumption under interference and traffic demand uncertainty. Toward this end, we propose a dynamic bandwidth/channel/power allocation algorithm that aims at maximizing the overall network’s throughput while selecting the set of power resulting in the minimum total transmission power. This problem can be formulated as a two-stage binary linear stochastic programming. Because the interference over different channels is a continuous random variable and noting that the interference statistics are highly correlated, a suboptimal sampling solution is proposed. Our proposed algorithm is an adaptive algorithm that is to be periodically conducted over time to consider the changes of the channel and interference conditions. Numerical results indicate that our proposed algorithm significantly increases the number of simultaneous IoT transmissions compared to a typical algorithm, and hence, the achieved throughput is improved.
Regular clocking scheme based design of cost-efficient comparator in QCAnooriasukmaningtyas
Quantum-dot cellular automata (QCA) gained a notable attraction in the emerging nanotechnology to get the better of power consumption, density, nano-scale design, the performance of the present CMOS technology. Many designs had been proposed in QCA for an arithmetic circuit like adder, divider, parity checker and comparator etc. Most of the designs have been facing the challenges of cost efficiency, power dissi-pation, device density etc. However, consideration of design automation, underlying clocking layout and integration of the sub modules are the most important which has a direct impact on the fabrication of the design. This work proposed a novel cost ef-fective and power aware comparator design, which is an essential segment in central processing unit (CPU). The noticeable novelty of the design was the use of underlying regular clocking scheme. A new scalable, regular clocking scheme has been utilized in the coplanar design of the comparator which enables regular or uniform cell layout of QCA circuit. It also exhibited the significant improvement over existing counterparts having irregular clocking in terms of area and latency. QCADesigner was used to test and verify the functionality of the circuit and by using QCAPro the power dissipation has been analyzed.
Wireless communication without pre shared secrets using spread spectrum techn...eSAT Journals
Abstract
The wireless communication using spread spectrum relies on the assumption that some secret is shared among source and
destination node before communication or transmission has started. This problem is called the circular dependency problem
(CDP). This CDP exists in large networks, where nodes frequently join and leaves the network. In this work we have introduced
an efficient and reliable mechanism called Advanced Encryption Standard (AES) Algorithm, to overcome circular dependency
problem (CDP). This is an efficient algorithm to make successful transmission of data without pre-sharing any secret key. We
have evaluated this by simulation in Matrix Laboratory (MATLAB).
Keywords: -Spread spectrum, CDP, AES and MATLAB.
Study and Performance Analysis of MOS Technology and Nanocomputing QCAVIT-AP University
One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based
information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits
and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.
PARALLEL BIJECTIVE PROCESSING OF REGULAR NANO SYSTOLIC GRIDS VIA CARBON FIELD...ijcsit
New implementations for parallel processing applications using reversible systolic networks and the
corresponding nano and field-emission controlled-switching components is introduced. The extensions of
implementations to many-valued field-emission systolic networks using the introduced reversible systolic
architectures are also presented. The developed implementations are performed in the reversible domain to
perform the required parallel computing. The introduced systolic systems utilize recent findings in field
emission and nano applications to implement the function of the basic reversible systolic network using
nano controlled-switching. This includes many-valued systolic computing via carbon nanotubes and carbon
field-emission techniques. The presented realization of reversible circuits can be important for several
reasons including the reduction of power consumption, which is an important specification for the system
design in several future and emerging technologies, and also achieving high performance realizations. The
introduced implementations for non-classical systolic computation are new and interesting for the design
within modern technologies that require optimal design specifications of high speed, minimum power and
minimum size, which includes applications in adiabatic low-power signal processing.
Intrusion Detection and Countermeasure in Virtual Network Systems Using NICE ...IJERA Editor
The cloud computing has increased in many organizations. It provides many benefits in terms of low cost and accessibility of data. Ensuring the security of cloud computing is a major factor in the cloud computing environment, as users often store sensitive information with cloud storage providers but these providers may be untrusted. In this project we propose anIntrusion Detection and Countermeasure in Virtual Network Systems mechanism called NICE to prevent vulnerable virtual machines from being compromised in the cloud. NICE detects and mitigates collaborative attacks in the cloud virtual networking environment. The system performance evaluation demonstrates the feasibility of NICE and shows that the proposed solution can significantly reduce the risk of the cloud system from being exploited and abused by internal and external attackers.
Miniaturization, cost, functionality, complexity and power dissipation are important and necessary design traits which need attention in circuit designing. There is a trade off between miniaturization and power dissipation. Smart technology is always searching for new paradigms to continue improve power dissipation. Reversible logic is one of smart computing deployed to avoid power dissipation. Researchers have proposed many reversible logic-based arithmetic and logic units (ALU). However, the research in the area of fault tolerant ALU is still under progress. The aim of this paper is to bridge the knowledge gap for a new researcher in area of fault tolerance using parity preserving logic gates rather than searching huge data through various sources. This paper also presents a high functionality based novel fault tolerant arithmetic and logic unit architecture. A comparison on optimization aspects is presented in tabular form and results shows that proposed ALU architecture is optimum balance in terms of all aspects of reversible logic synthesis. The proposed ALU architecture is coded in Verilog HDL and simulated using Xilinx ISE design suit 14.2 tool. The quantum cost of all gates used in proposed architecture is verified using RCViewer + tool.
The increasing demand for faster, robust, and efficient device development of enabling technology to mass production of industrial research in circuit design deals with challenges like size, efficiency, power, and scalability. This paper, presents a design and analysis of low power high speed full adder using negative capacitance field effecting transistors. A comprehensive study is performed with adiabatic logic and reversable logic. The performance of full adder is studied with metal oxide field effect transistor (MOSFET) and negative capacitance field effecting (NCFET). The NCFET based full adder offers a low power and high speed compared with conventional MOSFET. The complete design and analysis are performed using cadence virtuoso. The adiabatic logic offering low delay of 0.023 ns and reversable logic is offering low power of 7.19 mw.
Similar to Novel conservative reversible error control circuits based on molecular QCA (20)
The impact of quantum computing has been widely recognised in the engineering domain. The age of quantum computing has arrived, and with it comes the ability to easily solve exponential problems. This book is written by me to meet current academic demands. The book is designed to address the most important aspects of the subject of Quantum Computing. The publication of the book "Quantum Computing" is the culmination of numerous years of research and teaching in academia. It is given in a way that is straightforward to comprehend. The undergraduates, and graduate students may all benefit from reading this book. We have given our very best effort to bring you accurate book material.
The book explains the fundamentals of this topic in simple, straightforward language. The most efficient approach to go through this book is to grasp the underlying fundamental as well as mathematical concepts. The chapters are meant to stand on their own. This book is not intended to be theoretical; rather, it will serve to familiarise you with the fundamental of quantum computing, like applications, multiple-qubit systems, quantum state transformations, quantum gates and quantum circuits, tools for quantum computing, bell states, quantum Parallelism, quantum Algorithms: Shor’s Algorithm, Grover’s Algorithm, Quantum Hardware and software, Quantum Cryptography and Security, Quantum Error Rates and Quantum Noise, Quantum Fourier Transform, Quantum Machine Learning and so on.
The model questions and multiple-choice questions that are provided at the end of the book have been chosen to improve readers' understanding, as well as their performance in exams and key employment.
We warmly welcome and would be very appreciative of any comments or recommendations, that will help us enhance the overall quality of the book.
Cost-effective architecture of decoder circuits and futuristic scope in the e...VIT-AP University
The goal of Very Large Scale Integration (VLSI) over the past several decades has been the miniaturisation of chip size, along with increased computing speed and decreased power consumption. Miniaturization of size, high computing speed, and low power consumption does not appear to be able to meet the demand of consumers at this time. Quantum dot cellular automata is a more promising methodology that has the potential to optimise power, speed, and area at the nano-computing scale. In the field of nanocomputing, combinational circuit design has seen a significant amount of research and development effort. This article presents a comprehensive review as well as a proposed design of a decoder that has an accurate clocking mechanism and the best design. In terms of cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost, the novel 2-to-4 decoder achieves values of 87, 0.10, 0.0281, 28.1, 2.5, 0.625, 0.25, which is better than the prior work. Comparing the 2-to-4 decoder design to a standard design, the improvement is 72.64 %, 80 %, 72.71 %, 28.1 %, 64.28 %, 97,44 and 92.85 % in cell count, total area, cell area, area coverage, latency, QCA cost, and Quantum cost, respectively.
An in-depth study of the electrical characterization of supercapacitors for r...VIT-AP University
The Energy Storage System (ESS) is geared toward sophisticated systems with increased operating time for a variety of real-time applications such as an electric vehicle, a WSN (Wireless Sensor Network), a Capa bus, and so
on. Its primary focus is on supplying these kinds of systems with additional capacity in recent development, and
this will continue to be its primary focus. Because of their exceptionally high specific power, rapid charging, and
low ESR (Effective Series Resistance), electric double-layer (EDLC) capacitors or supercapacitors are encouraged
for use because they can be integrated more easily with battery technology that can be used in electric vehicles
and other electronic devices. The supercapacitor calls for a precise and accurate characterization in order to
facilitate the development of improved applications and more effective energy storage devices and technologies.
In this article, we studied various supercapacitor electrode components, electrolytic solutions, analogous circuit
models, electrical energy storage properties, and some real-time supercapacitor applications in the automotive,
manufacturing, construction, and consumer electronics industries. In addition, we have discussed on hybrid
material that was just recently developed with the goal of enhancing the conductivity and effectiveness of supercapacitors. Aside from this, we have discussed about the behaviour of supercapacitors in terms of how their behaviour is dependent on current and voltage with detailed analysis.
Agenda
1. Algorithm of Reading Scientific Research Article
2. Importance of ORCID ID
3. Benefit of ORCiD
4. Process of Connecting Scopus database to ORCiD iD
5. Registration of ORCiD iD Account
6. Scopus Database connected to ORCiD iD
7. BibTeX Entry to add all the publication at the same time in ORCiD iD
8. Process of importing BibTex into ORCiD Database
9. Using Bibtex include all the research article in one time
Content Addressable Memory Design in 3D pNML for Energy-Aware Sustainable Com...VIT-AP University
As the semiconductor industry strives for downsizing and high speed, it is confronted with
increasing scaling uncertainty as devices decrease to the nanoscale. Nano-magnetic logic (NML) is an alternative approach to synthesize the digital logic circuits with high-density and lowpower
consumption. We introduced an optimal design of content addressable memory (CAM)
memory based on perpendicular nano-magnetic logic (pNML). The main aim of this implementation
is to synthesize CAM memory in terms of latency and other design parameters. The implementation of the design is a multilayer approach, which is optimal. The synthesis approach
and optimization are perfectly scalable across layout construction of designs. Here a new logic gate in pNML technology is designed which is mainly used for matching of two input numbers. According to insight, both memory unit and a matching unit in the pNML are introduced in the state-of-the-artwork for the ¯rst time to synthesize design in high-speed pNML application. MAGCAD tool is used for the design of all the proposed pNML layouts.
Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...VIT-AP University
For design methodology of CRC or cyclic redundancy check is very used technique for error checking and shows the transmission reliability we are using the HDLC block. HDLC block is very useful in data communication these block operated in data link layer. For design methodology of CRC is to generate the CRC polynomial using XOR’s gate and shift register these polynomial are implement on software Xilinx Plan Ahead 13.1 and verify for simulation result for random testing of CRC bit on receiver side same result are obtained to show that it is more reliable.
Sensor Energy Optimization Using Fuzzy Logic in Wireless Sensor NetworkingVIT-AP University
Wireless sensor networks is challenging in that it requires an enormous breadth of knowledge from an enormous variety of disciplines. A lot of study has been done to minimize the energy used in routing and number of protocols has been developed. These protocols can be classified as - Hierarchical, data centric, location based and Network flow protocols. In this paper, we are particularly focusing on hierarchical protocols. In such types of protocols, the energy efficient clusters are formed with a hierarchy of cluster heads. Each cluster has its representative cluster head which is responsible for collecting and aggregating the data from its respective cluster and then transmitting this data to the Base Station either directly or through the hierarchy of other cluster heads. Fuzzy logic has been successfully applied in various areas including communication and has shown promising results. However, the potentials of fuzzy logic in wireless sensor networks still need to be explored. Optimization of wireless sensor networks involve various tradeoffs, for example, lower transmission power vs. longer transmission duration, multi-hop vs. direct communication, computation vs. communication etc. Fuzzy logic is well suited for application having conflicting requirements. Moreover, in WSN, as the energy metrics vary widely with the type of sensor node implementation platform, using fuzzy logic has the advantage of being easily adaptable to such changes.
Analysis on Fault Mapping of Reversible Gates with Extended Hardware Descript...VIT-AP University
Quantum-dot cellular automata is a modern computing paradigm, conceived in feature of nanometer
scale with high integration density, and significant low power. For the QCA technology, making these
high-density design means an increase in the complexity which in turn leads to growth in the number of faults. The defect model presented in this paper categorized into two types, which include single missing and additional cell considering for QCA fault. Proposed gates have been designed in the
QCA and verified. The proposed Fredkin gate design has been compared with an existing design,
and 43% and 70% improvement in cell count and area respectively are revealed. Also, the Toffoli
design in QCA which achieve some parameters such as cell complexity of 39, and the average fault tolerance of 53.5%. The polarization value for both single cells missing an addition cell missing has been studied to explain the logic signal strength effect physically. A QCA framework for the 3-input
Ex-OR, 2:1 multiplexer, Fredkin, and Toffoli gate for the fault problem in which reliability analysis based on Hardware description language for QCA devices (HDLQ) is discussed and verified on the fault pattern look-up table.
A Novel and Efficient Design for Squaring Units by Quantum-Dot Cellular AutomataVIT-AP University
Quantum cell automata (QCA) are the best possible alternative to the
conventional CMOS technology due to its low power consumption, less area and high-speed operation. This paper describes synthesizable QCA implementation of squaring. Vedic sutras used for squaring are defined over algorithm construction. Based on the concept of the Vedic sutra, this paper has carried out 2-bit square and
4-bit square, projective to affine logic gates construction. Importantly for miniaturization
of devices, the QCA based square is the operation on which the area of
circuits relies on. This means that significantly lower QCA parameters can be used in
the square than in other competitive square circuits such as Wallace, Dadda, serial parallel,
and Baugh-Wooley.
A Redundant Adder Architecture in Ternary Quantum-Dot Cellular AutomataVIT-AP University
Now researchers are moving toward emerging technologies to replace the
conventional CMOS technology. Quantum-dot cellular automata (QCA) are one of
them for high-performance computing circuits. Ternary QCA is one of the finest
research areas in this domain for replacement of binary logic. In this paper, we
proposed a new redundant adder architecture using Ternary QCA technology. Our proposed architecture has 233 numbers of cells with an area of 0.35 μm2. All the proposed ternary logic layouts are implemented in TQCA designer tool.
Implementation of Non-restoring Reversible Divider Using a Quantum-Dot Cellul...VIT-AP University
The CMOS-based integrated circuit may scale down to nanometer range. The primary challenge is to further downscale the device and high-energy dissipation. Reversible logic does not dissipate energy and no information loss. In this
way, the state-of-the-art technology such as QCA was forced toward high-speed
computing with negligible energy dissipation in the physical foreground. This work
targets the design of non-restoring reversible divider circuit and its implementation in QCA. We have utilized few 2 × 2 FG and 4 × 4 HNG gates as the block construction and also show the QCA implementation having cost-efficient approach. Further, the divider circuit has synthesized with FG and HNG gates
and QCA implementation. This divider circuit inherits many benefits such as fewer
garbage outputs, reduce quantum cost are achieved, and also reduced QCA primitives
can be improved by using efficient QCA layout scheme. Simulation investigations have been verified by QCA Designer. The proposed non-restoring divider also compares the reversible metrics results with some of other existing works.
An Explicit Cell-Based Nesting Robust Architecture and Analysis of Full AdderVIT-AP University
Moving towards micrometre scale to nanometre scale device shrinks down emerging nanometre technology such as quantum-dot cellular automata as a nesting
success. The introduced architecture is robust where the explicit design of full adder
and full subtraction uses for Ex-OR design. A new architecture of Ex-OR based on one majority gate is proposed, which its most optimized architecture and its placement of cells from the novel design. The analysis based on simulation showed that the
introduced Ex-OR and full adder makes only 11 and 46 cells count, respectively. In
proposed Ex-OR design, first output is received with no any latency which can be a
suitable design for implementation of the high-speed full adder design. In addition,
power estimation results are obtained after simulation of proposed designs in QCAPro
tool. Therefore, the novel designs improve the energy dissipation parameters such as mean leakage energy dissipation, mean switching energy dissipation and total energy dissipation 75, 11.28 and 82.19% in comparison with the most robust design in existing.
Concept and Algorithm of Quantum Computing During Pandemic Situation of COVID-19VIT-AP University
We are observing in this pandemic situation of COVID-19 the world in
very challenging and to solve this complex problem in quick time. Today, we are facing a difficult complex problem such as Coronavirus. This Coronavirus affects human life. Quantum computing is the only support that can give us quick results by processing the Coronavirus compound at high computation speed. Whatever present circuits in VLSI domain, we cannot perform the high-speed computation and not tackle the complex case as present COVID-19. In this article, we have been discussed about quantumcomputing era during the pandemic situation ofCOVID-19. Further, this paper presents fundamental about quantum properties such as superpo-
sition, entanglement, and quantum programming tools such as Qiskit (IBM), pyQuil
(Google), ProjectQ (ETH), Revkit, and RCvewier + . We have presented quantum
circuit and its decomposed circuit of such gates as Toffoli, Fredkin, Peres, and new
fault tolerance. In addition, we proposed algorithm as transforming cascade to the
quantumcircuitwhich is extended for verification based.All these concepts presented here will be very useful to researcher, academician, and industry person to tackle this
pandemic situation of COVID-19.
A Novel Parity Preserving Reversible Binary-to-BCD Code Converter with Testab...VIT-AP University
The reversible logic circuit is popular due to its quantum gates involved
where quantum gates are reversible and noted down feature of no information loss.
In this paper, parity preserving reversible binary-to-BCD code converter is
designed, and effect of reversible metrics is analyzed such as gate count, ancilla
input, garbage output, and quantum cost. This design can build blocks of basic
existing parity preserving reversible gates. The building blocks of the code converter
reversible circuit constructed on Toffoli gate based as well as elemental gate
based such as CNOT, C-V, and C-V+ gates. In addition, qubit transition analysis of
the quantum circuit in the regime of quantum computing has been presented. The heuristic approach has been developed in quantum circuit construction and the
optimized quantum cost for the circuit of binary-to-BCD code converter. Logic functions validate the development of quantum circuit. Moving the testability aim
are figured in the quantum logic circuit testing such as single missing gate and single missing control point fault.
Novel Robust Design for Reversible Code Converters and Binary Incrementer wit...VIT-AP University
This work, we employ computing around quantum-dot automata to
construct the architecture of the reversible code converters and binary incrementer. The code converter and binary incrementer are made up of Feynman gate and Peres
gate, respectively. We have presented the robust design of Ex-OR in QCA, which is used for the construction of code converters and binary incrementer. The layouts of proposed circuits were made using the primary elements such as majority gate, inverter, and binary wire. A novel binary-to-gray converter design offers 59% cell count reduction and 36% area reduction in primitives improvement from the
benchmark designs. Being pipeline of PG gate to construct the 1-bit, 2-bit, and 3-bit
binary incrementer, we can use this robust layout in the QCA implementation of binary incrementer. By the comparative result, it is visualized that the binary incrementer such as 1-bit, 2-bit, and 3-bit achieved 60.82, 60.72, and 64.79% improvement regarding cell count from the counterpart.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
For more technical information, visit our website https://intellaparts.com
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
COLLEGE BUS MANAGEMENT SYSTEM PROJECT REPORT.pdfKamal Acharya
The College Bus Management system is completely developed by Visual Basic .NET Version. The application is connect with most secured database language MS SQL Server. The application is develop by using best combination of front-end and back-end languages. The application is totally design like flat user interface. This flat user interface is more attractive user interface in 2017. The application is gives more important to the system functionality. The application is to manage the student’s details, driver’s details, bus details, bus route details, bus fees details and more. The application has only one unit for admin. The admin can manage the entire application. The admin can login into the application by using username and password of the admin. The application is develop for big and small colleges. It is more user friendly for non-computer person. Even they can easily learn how to manage the application within hours. The application is more secure by the admin. The system will give an effective output for the VB.Net and SQL Server given as input to the system. The compiled java program given as input to the system, after scanning the program will generate different reports. The application generates the report for users. The admin can view and download the report of the data. The application deliver the excel format reports. Because, excel formatted reports is very easy to understand the income and expense of the college bus. This application is mainly develop for windows operating system users. In 2017, 73% of people enterprises are using windows operating system. So the application will easily install for all the windows operating system users. The application-developed size is very low. The application consumes very low space in disk. Therefore, the user can allocate very minimum local disk space for this application.
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2. 2 N.K. Misra, B. Sen and S. Wairya
high-speed network, and NANO-Electronics. He has more than 22 years’ experience in teaching
and research. He has served as Scientist ‘B’ in Defense Research & Development Organization
(DRDO) and Graduate Engineer (Design Project) in Hindustan Aeronautical Limited (HAL),
Lucknow from 1994 to 1996.
1 Introduction
In recent years, low power becomes a primary factor due to
the advancement in an integrated circuit. In 1960, Landauer
proved that the energy dissipated due to loss of data bits is
related to the irreversible logic circuit (Landauer, 1961). It
has been also presented that the energy dissipated is exactly
(n*KTln2), where n = total sum of the data bits loss,
K = Boltzmann’s constant and T = temperature. Bennett
proves that the ideally zero energy dissipation can be
possible if the circuit is designed by the reversible gate
(Bennett, 1973). Reversible logic has become one of the
most popular techniques owing to the reduced energy
dissipation. Further, the quantum circuit, as the enormous
area (Wille, 2011), designs the reversible circuit. The nature
of quantum circuit is reversible (Sen et al., 2014). Thus,
computing using quantum circuit shows an attractive prospect
for next generation technology. A significant action in
reversible circuit design is the optimisation of parameters
such as garbage outputs, gate count, constant input, unit
delay, and quantum cost for efficient circuit design (Sen et al.,
2013; Misra et al., 2017a).
A popular area of nanoelectronics is a regime which is
not met by the MOS transistor technology due to its feature
size reduction (Nehru and Shanmugam, 2014; Pankaj et al.,
2016). In this way, quantum-dot cellular automata (QCA)
approach the practice of high computation speed, low
power, and high density (Mohammadyan et al., 2015). It is a
good vision to use QCA technology in digital logic circuit
design (Misra et al., 2016a).
Conservative logic based circuits can find the error by
matching the parity bits (Roohi et al., 2016; Misra et al.,
2017b). In data communication environment the data bits
are transmitted from the transmitter to the receiver over a
noisy medium. In the way, the Hamming code was proposed
by Richard W. Hamming in the 1940s (Misra et al., 2015).
Hamming code based error detection and correction are
still receiving more consideration for research as well as
industry. Its outstanding feature is to detect and correct the
error (Haghparast and Navi, 2011; Misra et al., 2016b). The
primary challenge of Hamming circuit is to develop low
reversible metrics on quantum computing framework (Misra
et al., 2016a). To the best of state-of-art review technology,
this is a first attempt in the literature that successfully
synthesises Hamming code circuit with the optimising
reversible metrics.
In nano-communication application, the main challenge
is to make error-free data communication (Jayanthy et al.,
2013; Gupta et al., 2015). In a more practical way, the
reversible circuit is more useful in nano-communication,
when we minimise reversible metrics. It is reviewed that
reversible circuit having include of conservative logic gates
is more demand (Chandra et al., 2015). In our work, we
minimise the reversible metrics in conservative reversible
logic based circuit, it is successfully achieved as reported
here.
This work concentrates on the error control circuits,
which is showing a Nano-communication framework. The
existing circuit in Thapliyal and Ranganathan (2010), Das
and De (2016), Haghparast and Navi (2011), Mustafa and
Beigh (2013), and Ahmad et al. (2015) motivates the circuit.
We design first category circuit like a conservative
reversible hamming code. The second category of
conservative reversible circuit such as parity generator and
parity checker. To optimise our designs, we propose two
novel conservative, reversible gates such as HG-PP
(HG = Hamming gate, PP = parity preserving), and NG-PP
(NG = new gate) gates for circuits synthesis and
optimisation. In addition, the quantum equivalent is
presented for all the proposed circuits. The error control
circuits like Hamming code, parity generator, and parity
checker provided full coverage of error control. The
justification of parity generator and parity checker logic
circuit are constructed by novel NG-PP gate, whereas
Hamming code circuit is based on novel HG-PP gate. The
QCA implementations of the novel gates are also presented
to justify the reliability of circuit in the physical foreground.
The proposed circuits are superior in terms of reversible
metrics such as quantum cost, unit delay, garbage output,
constant input, and gate count. In addition, the quantum
equivalent is presented to all the proposed error control
circuits. Moreover, we estimate the energy dissipation
related parameters of proposed gates by using the QCAPro
tool, to indicate the low power feature in the work.
Especially, this workaround in reversible error control
circuits can be highlighted as:
The proposed conservative reversible gates such as HG-
PP and NG-PP are taken into consideration for the
design of Hamming code, parity generator, and parity
checker.
An attempt has been made to design the quantum
equivalent circuits for error control circuit.
The workability of the proposed gates is justified by
QCADesigner, which shows the property under an
environment of majority gates, and inverter to meet the
physical foregrounds.
We use a few novel reversible gates to account for the
low-cost metrics in the circuit model of error control
circuits and compare the cost metrics to existing
counterparts. These comparative results lead to very
low reversible metrics reported here.
3. Novel conservative reversible error control circuits based on molecular QCA 3
We described the energy dissipation of proposed gates
such as HG-PP and NG-PP by designing a thermal
layout in QCAPro tool.
The work is organised as follows: Section 2 presents the QCA
fundamentals including the reversible logic. The state-of-the-art
section is framed in Section 3. Section 4 proposes two novel
reversible gates. Section 5 includes the proposed gates in QCA
framework. Section 6 contains energy dissipation analysis of
proposed gates. Section 7.1 shows synthesis approach of parity
generator and checker. Section 7.2 presents the proposed
circuits of Hamming generator and checker. Section 7.2.3
presents the observation and discussion. Finally, the conclusion
is presented in Section 8.
2 QCA fundamentals and reversible logic
In this section, we present the fundamentals of QCA including
reversible logic, conservative logic, and quantum cost.
2.1 QCA
A QCA cell contains four dots with two free electrons (Lent
et al., 1993). The two polarisation states (P = –1, P = +1) are
possible as per the electrons location in the cell (Figure 1a).
In QCA two fundamental structures are possible as an
inverter and the majority, as depicted in Figure 1b, 1c. QCA
clock has four clock zones (clock0, clock1, clock2 and
clock3) each clock phase shifted by 90°. Each clock zone
has four phases (Release, relax, switch and hold), as shown
in Figure 1d, 1e. The clock phase’s description as switch
phase: barrier is gradually high, hold phase: polarity
withholds, release: barrier is gradually lowered, relax:
release polarity, as shown in Figure 1f. The Coulombic
attraction between nearest electrons leads to synchronisation
of adjacent cells, so they affect the polarisation state of
another cell (Das et al., 2012). Thus, a repeated cell
arrangement in QCA forms a wire. The QCA complements
or un-complement signal of input are realised by the
alternate arrangement of cells by tapping off a normal wire
(Figure 1g).
2.2 Reversible logic
In reversible logic gate there is a bijective property (unique
correspondence) between the input and the output vectors in
function F (F has n x n type, where n = input and n = output)
then F is reversible. It is only the gate level designing
approach. The reversible gate is essential units of the
reversible logic circuit (Tabatabaii and Haghparast, 2016).
The delay is the maximum number of the gate in a path
from applying input to target output line. It is considered
that each gate executes computation in the one-time unit.
Figure 1 Basics of QCA (a) four-dot QCA cell (b) inverter (c)
majority gate (d) clock, four stages (e) clock phase
shifted (90°) (f) clocking concept (g) outputs, realisation
from inputs
0
45
0
90
0
90
2.3 Conservative reversible logic
A conservative gate is a reversible gate that regularly fixes
the parity between inputs and outputs. More appropriately, a
n x n conservative reversible gate preserves the parity as
well as the unique mapping between all sequences of inputs
and outputs (Misra et al., 2016c).
2.4 Quantum cost
The count of controlled-V, controlled-V+
, and Ex-OR, gates
gives the total quantum cost of the quantum circuit. The
representation of controlled-V is shown in Figure 2a. If the
control input A=0, qubit B will propagate through the A will
remain the same i.e., Q=B is synthesised. Another value of
controlled input A=1 then the unitary operation applies to
the other input B, that is Q = V (B). The other quantum gate
is controlled V+ gate is depicted in Figure 2b. If control
input A=0 means qubit B will propagate but a controlled
part, remain the same i.e., Q=B. Another value of A=1
means unitary operation V+
=V–
applies to the input B i.e.,
Q=V+
(B). The three types of quantum equivalent are
depicted in Figure 2c. The equivalent quantum cost of these
4. 4 N.K. Misra, B. Sen and S. Wairya
qubit gates is zero. The two other integrated qubit gate is
illustrated in Figure 2d. The basic properties V x V=NOT, V+
x
V =V x V+
=I, V+
x V+
=NOT were utilised for reversible
computing.
Figure 2 Basic quantum gates (a) square root of NOT (b)
Hermitian matrix of SRN (c) quantum wire (d)
integrated qubit
1
I
2
I 1
I )
I
(
V 2
2
I
1
I
V
1
I
2
I 1
I )
I
(
V 2
2
I
1
I
V
1
I
2
I
1
I
2
1 I
I
1
I
2
I
1
I
2
I
1
I
2
I
1
I
2
I
V
V
V
V
)
a
( )
b
(
1
Cost 0
Cost 0
Cost
1
Cost 1
Cost
)
c
(
)
d
(
Table 1 Previous works on reversible error control
Circuit Need Method Factor Surround
HGC in Haghparast
et al.
F2G R/C
More CC
and UD
Missing
HGC in Haghparast
et al.
F2G R/C
More QC
and GO
Missing
HGC, circuit #1in
James et al.
FG, HCG R
More GC
and QC
Missing
HGC, circuit #2 in
James et al.
FG, F2G R More CC Missing
HGC, circuit #3 in
James et al.
F2G,
PPHCG
R/C More CC Missing
HGC, circuit #4 in
James et al.
F2G R/C
More CC
and UD
Missing
HDC, circuit #5 in
James et al.
HCG, FG R More GO Missing
HDC, circuit #6 in
James et al.
F2G R/C
More CC
and UD
Missing
PGC in Mustafa
et al.
FG R
More QC
and GO
QCA
PGC in Ahmed
et al.
Logic
gates
NR
More
latency, CC
and area
QCA
Notes: HGC-Hamming generator circuit; HDC-Hamming
detector circuit; PGC-Parity generator circuit; R/C-
Reversible/Conservative; NR-Non-reversible; CC-Circuit
complexity; UD-Unit delay; QC-Quantum cost; GO-
Garbage outputs; GC-Gate count; QC-Quantum cost.
3 Related work
On the synthesis of error control circuits, less amount of
research works presented in the state-of-the-art work. The
design in Das and De (2016) has addressed reversible parity
generator and checker circuits using Feynman gate (FG) there
is a certain limitation. Firstly: circuits claim too much gate
count, garbage outputs, and quantum cost. Secondly: circuits
are non-conservative. The design in (James et al., 2007) has
discussed the Hamming code based approach to error control
in reversible circuits. The presented approach target both in
parity based gates and without parity based gates. The cost for
such without parity based Hamming-code generator was GC
of 6 gate and quantum cost of 8, the Hamming code detector
requires GC of 4 and QC of 9. The parity-based Hamming-
generator used GC of 6 and quantum cost of 12, Hamming-
checker requires GC of 5 and QC of 10. Most of the existing
designs focused only on the reversible circuits synthesise
without emphasis on the nanometric scale such as QCA
technology. We considered the most optimised Hamming error
control circuits in Haghparast and Navi (2011), James et al.
(2007) and parity generator and checker circuits in Das et al.
(2012) and compared it with our circuits, as an achievement in
both circuits were to reduce the reversible metrics.
4 The proposed reversible gates
For construction and optimisation of reversible circuits, we
have proposed few conservative reversible gates.
4.1 Conservative reversible HG-PP gate
A 5 x 5 conservative reversible logic gate named HG-PP is
drawn in Figure 3a.The truth table of HG-PP is drawn in
Figure 3c. It depicts the same count of 1’s in the output as
well as input, further maintain the bijective-mapping
property of the reversibility. Hence this gate is reversible as
well as conservative. The quantum equivalent and HG-
PP.tfc is depicted in Figure 3b. The QC of HG-PP gate is
only four, as shown in Figure 3b. This work designs HG-PP
because it can helpful for the design of hamming code.
The LC of HG-PP is calculated in this method. The R,
and T expressions have LC = 0. Then final LC can be
computed as:
LC (HG-PP) = 2α (P) + 1α (Q) + 0α (R) + 1α (S) + 0α (T)
= 4α.
The utility of the HG-PP gate as a reversible three input Ex-
OR, two input Ex-OR, and signal duplication, if applying
the inputs. This work design HG-PP because it can easily
construct the conservative reversible hamming generator
and checker circuit with utilising very less quantum cost and
gate count.
5. Novel conservative reversible error control circuits based on molecular QCA 5
4.2 Conservative reversible NG-PP gate
The NG-PP structure is utilised of 5-input and 5-output. The
schematic diagram and truth table is shown in Figures 4a,
4b. By seeing the truth table the input parity to output parity
is conserved. Hence this gate is a conservative gate. Further,
it holds the bijective mapping, it also the reversible gate.
The QE of NG-PP is shown in Figure 4c. This work designs
NG-PP because it can singly perform the logic operation of
parity generator and checker.
The LC of NG-PP is calculated in this method. The P,
Q, and R expressions have LC = 0.
The S expression (ABC) has LC =3α. Then we form
signal duplication to make (ABC) in T expression. Then
final LC can be computed as:
LC (NG-PP) = 0α (P) + 0α (Q) + 0α (R) + 1 α (for signal
duplication operation in T) + 3α (S) + 1α (T) = 5α.
Now we have presented the utility of NG-PP by setting
D=E=0, the same time realise the three input Ex-OR logic
function with only use of QC of 5, which are useful for the
construction of conservative reversible parity generator and
parity checker circuit.
Throughout the work we measure the quantum cost: It
is the number of elemental quantum gates involve in the
quantum circuit.
In all the schematic diagram in this work we consider
inputs are all on the left side, where the corresponding
outputs on the right side.
Throughout the work we include the *.tfc code to
synthesise the quantum equivalent as well as quantum
cost. Moreover, the manual manipulation of the
quantum cost is also done to ensure the correct value of
quantum cost.
Throughout the work we try to minimise the quantum
cost is beneficial for quantum computing paradigm.
5 Design of proposed gates in
QCA framework
The idea of the logic design of reversible computing in
QCA technology is based on the fact that the addition of
reversible circuits with QCA framework is equivalent to the
low power circuit. QCA technology is considered as the
following features such as high-speed computing, high
device density, and low energy dissipation. The QCA cells
are used for implementing the QCA circuit. The basic
building elements of the QCA circuit are the majority voter
gate, inverter, and wire.
Figure 3 The proposed conservative reversible HG-PP (a) schematic diagram (b) HG-PP. tfc code and QE (c) truth table
HG-PP
.v A,B,C,D,E
.i A,B,C,D,E
.o A,B,C,D,E
BEGIN
T2 C,A
T2 E,A
T2 C,B
T2 E,D
END
1 2 3 4
(a)
(b)
(c)
6. 6 N.K. Misra, B. Sen and S. Wairya
Figure 4 The proposed conservative reversible NG-PP (a) schematic diagram (b) NG-PP. tfc code and QE (c) truth table
NG-PP
.v A,B,C,D,E
.i A,B,C,D,E
.o A,B,C,D,E
BEGIN
T2 D,E
T2 B,D
T2 A,D
T2 C,D
T2 D,E
END
NG-PP.tfc code
(a)
(b)
(c)
The novel gates are tested in QCADesigner tool. The
simulating computer is provided with Intel(R) core(TM) i5-
6200U CPU 2.40GHz, 4GB RAM, and environment of
Window 10Home (64-bit). Addition, the simulation setting
(Bistable approximation) of QCADesigner have been adopted
with dot diameter, single cell area, adjacent cell distance,
radius of effect, and cell separation, which is settled to be
5nm, (18nm) x (18nm), 42nm, 65nm, and 2nm respectively.
The novel gates are designed with QCADesigner tool
for checking the workability and further the QCA primitives
are evaluated. The characteristics of QCA primitives like
cell complexity, area, and latency are also evaluated. The
workability has ensured the implementation in QCA show
the existence in the physical foreground.
5.1 Design of NG-PP gate in QCA
In order to check the workability of the proposed NG-PP in
QCADesigner. First, the layout of NG-PP is implemented in
QCA. The NG-PP cell layout, a block diagram with clock
zone and simulation result are depicted in Figures 5a, 5b,
and 5c. The simulation result ensures the correctness of the
gate. The simulation result is checked by comparing with
truth table as drawn in Figure 4c. The QCA layout of NG-
PP is implemented with majority voter gates of 9, inverters
of 6, and area of 45nm2
.
5.2 Design of HG-PP gate in QCA
The prominent application of reversible circuit in QCA
computing is a nanoscale based computing. The block
diagram, cell layout, and the simulation result of HG-PP are
shown in Figures 6a, 6b, and 6c. It is remarkable that the
latency of the design has been decreased by using the QCA
layout. In Figure 6c simulation result is verified. The
simulation result is justified by comparison with truth table
as drawn in Figure 3c. By the results analysis, it is noticed
that the proposed HG-PP layout achieved cell complexity of
175, area of 0.25 µm2
, and latency of 3.
5.3 The performance table of proposed gates
regarding QCA primitives
In summary, the QCA primitive’s results of proposed gates
in terms of majority voter (MV), latency, total area, cell area
and area usages are presented in Table 2. The QCA
primitive’s results are justified by the QCA layout. The area
of one QCA cell is expressed as: (18nm) x (18nm) = 324
nm2
. The approach of area usages and cell area calculation
are described below as:
Cell area = (Total cell) x (One cell area)
Area usage = (Cell area) / (Total area) = (Total cell) x
(One cell area) / Total area
Thus the area usages calculated of proposed gates are
calculated as:
1 Area usages of HG-PP = (173) x (324) / 241057 x 100
% = 23.25 %,
2 Area usages of NG-PP = (255) x (324) / 422254 x 100
% = 19.56 %.
7. Novel conservative reversible error control circuits based on molecular QCA 7
Figure 5 QCA implementation of NG-PP (a) block diagram (b) cell layout (c) simulation result
D3
D3
D0
D2
D1
D2
D1
D2
D1
D0
C
D2
D1
D2
D1
D3
D0
B D
A
D0 D0
D2
D1
-1
+1
D1
D1
-1
D2 D3
D0
-1
D2
D1 D3 D0 D2
E
D0
-1
D1
+1
T
S
D2
D1 D3
D3
D3
(a)
(b) (c)
Figure 6 QCA implementation of HG-PP (a) block diagram (b) cell layout (c) simulation result
D3
D3
D0
D2
D1
D2
D1
D2
D1
D0
D2
D1
D2
D1
D3
D2
D2
D3
D1
D0
D1
P
Q
+1
-1
D1
B
-1
A
D2
D2
D3
D1
D0
D1
S
+1
-1
D1
D
-1
D0
C
D0
D0
E
D0
8. 8 N.K. Misra, B. Sen and S. Wairya
Table 2 QCA primitive’s results of proposed gates
Gates
QCA Primitives
MV L CC TA (nm2
) CA (nm2
) AU %
HG-PP 8 3 173 241057 56052 23.25
NG-PP 9 4 255 422254 82620 19.56
Notes: MV: Majority voter gate, L: Latency (Clock
delay), CC: Cell count: TA: Total area, CA: Cell
area, AU: Area usage.
Thus the results of table ensure that the proposed gates QCA
layouts have met the demand of nanoscale QCA based
computing.
6 Energy dissipation analysis
Energy dissipation of QCA layout is important in the low
power paradigm. Reduced energy dissipation and improve
efficiency are important in nanoelectronics application.
Researcher in Srivastava et al. (2009) proposed an energy
estimation model to the QCA circuit based on kink energy.
This model shows the effect of kink energy on energy
dissipation on the sharp clock transitions.
The thermal layout and energy dissipation related
parameters are performed on the Intel (R) core(TM) i5-
6200U CPU 2.40GHz, 4GB RAM, and environment of
Linux (Ubuntu-12.04, 32bit). We have taken files such as *.
QCA file (create in QCADesigner version 1.4.0), majority
switching vector (only inputs), and majority vector set
(both inputs and outputs). These files are implemented in
QCAPro tool to find the energy dissipation related
parameters like switching energy dissipation, average
energy, maximum and minimum energy dissipation, and
thermal layout. The thermal layout has the unique design of
visualising the energy dissipation at each cell. The cells
have two colours. The darker cells have more the energy
dissipation and vice versa. Thus lighter cells have now
become dominate the thermal layout, whereas darker cell is
few numbers.
6.1 Energy dissipation estimation for
HG-PP and NG-PP
Towards estimation of energy dissipation, we first illustrate
the kink energy. The kink energy is affected the energy
dissipation. In fact, the two adjacent cells have opposite
polarisation the energy dissipation increase and the
increased energy is known as kink energy (always greater
than ground energy). In fact, minimum energy is termed
for same polarisation state and maximum for different
polarisation state. In this work, a model in Srivastava et al.
(2009) is adopted for the result of energy estimation.
The thermal layout map for energy dissipation in each
cell of NG-PP is shown in Figure 7a, which shows the
maximum number of cells is dissipated less energy (lighter
cells). The energy dissipated parameters for NG-PP is
visualised in Figure 7b. In the 0.5Ek, max. energy diss., min.
energy diss., avg. energy diss., avg. leakage, and avg.
switching energy diss. are 0.01837, 0.07365, 0.58932,
0.28173, 0.1362 respectively, likewise are 0.37631, 0.21735,
0.71635, 0.35672, 0.38965 respectively at 1Ek, and 0.47325,
0.36271, 0.97632, 0.31782, 0.76532 respectively at 1.5Ek.
This energy dissipation analysis and QCA primitive’s results
ensure the high demand of NG-PP gate in the nanoelectronics
paradigm.
The energy dissipated related results for HG-PP is
depicted in Figure 8b. This result shows the max. energy
diss., min. energy diss., avg. energy diss., avg. leakage, and
avg. switching energy diss. are 0.01307, 0.09844, 0.28008,
0.09934, 0.18074 respectively at 0.5Ek, likewise are
0.59504, 0.27176, 0.42273, 0.27404, 0.14869 respectively
at 1Ek, and 0.72997, 0.46136, 0.58710, 0.46430, 0.12280
respectively at 1.5Ek. By this result, the avg. energy diss. of
the HG-PP increase with the kink energy in a constant
manner. Figure 8a shows the thermal layout map for energy
dissipated in each cell of an HG-PP.
Figure 7 NG-PP (a) thermal layout map (b) energy dissipation
results
(a)
(b)
9. Novel conservative reversible error control circuits based on molecular QCA 9
7 The proposed conservative reversible
error control circuits
In this section, we present two nano-communication circuits
such as Hamming code, even parity generator and even
parity detector.
7.1 The proposed circuit of even parity generator
and even parity checker
In this section, we demonstrate synthesis of conservative
reversible circuits such as even parity generator and even
parity checker in quantum computing paradigm.
Figure 8 HG-PP (a) thermal layout map (b) energy dissipation results
(a) (b)
Figure 9 NG-PP based realisation of (a) parity generator (b) parity checker
NG-PP
NG-PP
Parity Generated bit
Parity checker bit
Even Parity Generator
Even Parity Checker
a
b
10. 10 N.K. Misra, B. Sen and S. Wairya
Figure 10 Complete schematic of parity generator and checker
NG-PP NG-PP
Transmission wire
No Error
Error Detection Circuit
a
b
7.1.1 Even parity generator
There is vast potential to control error when applying parity
generator and checker to a data communication system
(Mustafa and Beigh, 2013). Even parity generator is a
circuit that finds the input data bits, performs the Ex-OR
operation to all the input data bits then determine the even
number of 1’s, which is studied in Ahmad et al. (2015). The
parity generator (Pg) bit is 1 when the number of 1’s is
even, otherwise not.
This parity generator circuit contains one NG-PP gate.
The inputs contain three data bits (D0, D1, D2) and two
constant inputs, which is shown in Figure 9a. This circuit
can be programmed by applying data bits. The parity
generator bits are expanded as g 0 1 2
P D D D
. It is
clear from the Figure 9a the output bit is high when even
numbers of 1’s appear.
7.1.2 Even parity checker
The structure of proposed even parity checker is presented in
Figure 9b. This circuit contains one gate (NG-PP), it requires
five inputs and five outputs. The input contains four data bits
(D0, D1, D2), one parity generator bit (Pg), and one CI. This
circuit produces four outputs (D0, D1, D2, Pg) and one GO. In
addition, parity checker bit is synthesised by Ex-OR of inputs.
However, when the parity checker bit (PC) is low, the no error
condition occurs. If the case of checker bit (PC) is high, then
there occurs an error in receiving data bits. This circuit also
captures all the data bits (D0, D1, D2) on the output side, an
attractive technique for online testability of circuit.
The error detector circuit is synthesised by two gates (two
NG-PP), it requires six inputs and six outputs. The inputs
contain three data bits ((D0, D1, D2), and two CI. The circuit
produces four outputs: D0, D1, D2, which are recovered data
bits, and Pc which is indicated for an error condition. This
circuit has three CI, and two GO, as depicted in Figure 10b. In
this circuit construction, we report the algorithm 1.
Algorithm 1: Complete parity generator and checker
Input, Output: Inputs data bits (D0, D1, D2) in binary
form, Outputs Pc in binary form.
1: For i=0 to n-1 do
2: If i=1 then
(D0, D1, D2, 0, 0) → NG-PP // Assign inputs to
first NG-PP
NG-PP ← (D0, D1, D2, Pg) // Catch three
intermediate outputs
End if, Else
3: (D0, D1, D2, Pg) → NG-PP // Assign inputs to
second NG-PP
(Pc) ← NG-PP // Catch the one
outputs
End if, Else
4: If i = 3 then
Call desired output
(Pc) ← NG-PP // Desired output
End if, Else
5: If Pc=0 then
Comment: No Error
End if, Else
Comment: Error
NG-PP← (GO1), NG-PP← (GO2) // Remaining as GO
6: End if, end for,
7: Return Pc, End;
11. Novel conservative reversible error control circuits based on molecular QCA 11
Proposition 1. The LC of the complete even parity generator
and checker is LC (complete even parity generator) = 2LC
(NG-PP) = 2 x 5α = 10α.
Proposition 2. The QC of the complete even parity
generator and checker is QC (complete even parity
generator) = 2 QC (NG-PP) = 2 x 5 = 10.
In the state-of-the-art work, there are fewer circuits of
conservative reversible (CR), parity generator and checker.
The circuit proposed in Das and De (2016) shows the
optimised circuit of parity generator and checker but non-
conservative approach. Table 3 presents the performance of
our circuit versus counterpart works.
7.1.3 Simulation results for even parity
generator and checker
Lemma 1: The proposed 3-bit parity generator and 4-bit
parity checker are required 1.5 latency.
Proof: The 3-bit parity generator contains one NG-PP gate
(in Figure 9a). The inputs include three data-inputs (D0, D1,
D2) to various combinations of binary value, the generated
outcome (Pg) result is obtained after 1.5 cycle delay, as
shown in Figure 11. Hence a 3-bit parity generator is
required at least 1.5 latency.
A 4-bit parity checker circuit is shown in Figure 9b. The
inputs include four data-inputs (D0, D1, D2, Pg) and one
constant input as logic ‘0’. The circuit is utilised same as
QCA layout of NG-PP gate. The simulation outcomes is
shown in Figure 12. This outcome is justified by comparing
the truth table as drawn in Figure 9b. The required parity
checker is obtained after 1.5 clock cycle delay. Hence a
parity checker has required at least 1.5 latency.
7.2 The proposed circuit of hamming generator
and checker
In this section, we have illustrated our compact circuit for
hamming generator and checker using novel reversible gate
and few existing gates.
7.2.1 Hamming code generator
The prominent application of Hamming code in the area of data
communication. Hamming code is a logic circuit that finds the
double bit error detection (DBED) and single bit error
correction (SBEC). The decoding of data bits in Hamming
code is shown in Figure 14b. The Hamming code generator
(HCG) contain four gates (2xF2G, and 2xHG-PP), it involves
10 inputs and 10 outputs. The input includes four data inputs
(D0, D1, D2, and D3) and six constant inputs, as shown in
Figure 14a. This circuit produces seven outputs: H1, H2, H3,
H4, H5, H6, and H7. Whereas outputs: H1, H2, and H4 are
utilised for parity bits. All the parity bits are specified by the
equations 1, 2, and 3. The other three outputs are garbage
outputs. The quantum equivalent and HCD.tfc code of this
HCG is shown in Figure 14b. The construction of this
circuit requires QC of 12, which is marked by dotted box, as
shown in Figure 14c. The LC and QC for the HCG circuit
are calculated by the propositions 3 and 4.
1 0 1 3
P D D D
(1)
2 0 2 3
P D D D
(2)
3 1 2 3
P D D D
(3)
Proposition 3. The LC of HCG is 2 LC (F2G) + 2 LC
(HG-PP) = 2 x (2α) + 2 x (4α) = 12α.
Proposition 4. The QC of HCG is 2 QC (F2G) + 2 QC
(HG-PP) = 2 x (2) + 2 x (4) = 12.
Algorithm 2: Algorithm for the reversible HCG
Input: Take 7-bit data inputs Iv=Di (i=0 to 3)
Output: Hamming code generator (named as HCG)
outputs Pi (i=1 to 3) and Di (i=0 to 3)
1: Begin
2: For i=0 to n-1 then
3: If i = 1 then
(D3,0,0) →F2G //Assign input to first F2G
F2G ← (D3, D3) // Two intermediate output
F2G ← (H7) //Catch one target output
End if, Else
4: (D3,0,D2,0,D0) →HG-PP //Assign input to first
HG-PP
(D2) ← HG-PP // One intermediate output
(H2, H3, H6) ← HG-PP //Catch three target
output
End if, Else
5: If i = 3 then
(0, D2, D3, 0, D0) →HG-PP // Assign input to
second HG-PP
0 3 2 3
D D , D D
← HG-PP // Two
intermediate output
End if, Else
1 0 3 2 3
, D D , D D
D →F2G // Assign input to
second F2G
(H1, H4, H5) ←F2G // Catch three target output
HG-PP←(GO1, GO2, GO3) //Remaining as GO
6: End if, Else if, end for,
7: Return (Hi), End;
12. 12 N.K. Misra, B. Sen and S. Wairya
Table 3 Cost metrics statistics of parity generator and checker
Design GC GO UD QC QE C/R
Parity generator
Das et al (2016) 3 2 3 3 N N/Y
Novel 1 4 1 5 Y Y/Y
Improvement in % +66.66 –50 +66.66 –66.66
Parity checker
Das et al (2016) 6 3 4 6 N N/Y
Novel 1 4 1 5 Y Y/Y
Improvement +83.33 –33.33 +75 +16.66
Combined
Das et al (2016) 9 4 7 9 N N/Y
Novel 2 5 2 10 Y Y/Y
Improvement in % +77.77 –25 +71.42 –10
Notes: C: Conservative, R: Reversible, GC: Gate count, GO: Garbage output, UD: Unit delay, QC: Quantum cost, QE:
Quantum equivalent, Y: Yes, N: No
Figure 11 Simulation result of even parity generator using the only NG-PP
13. Novel conservative reversible error control circuits based on molecular QCA 13
Figure 12 Simulation result of even parity checker by using the only NG-PP gate
Figure 13 Decoding of parity bit
14. 14 N.K. Misra, B. Sen and S. Wairya
Figure 14 The proposed HCG (a) schematic diagram (b) Toffoli gate block and HCG.tfc code (c) snapshot of result
F2G
HG-PP
F2G
HG-PP
HCG
Cell
(a)
(b)
.v a,b,c,d,e,f,g,h,i,j
.i a,b,c,d,e,f,g,h,i,j
.o a,b,c,d,e,f,g,h,i,j
BEGIN
T2 a,b
T2 a,c
T2 e,a
T2 g,a
T2 e,d
T2 g,f
T2 c,h
T2 g,h
T2 c,d
T2 g,i
T2 j,h
T2 j,d
END
a
b
c
d
c
a
e
f
g
h
i
j
g
d
h
d
HCG.tfc code
F2G
F2G
HG-PP
HG-PP
(b)
(c)
Figure 15 The proposed HCD (a) schematic diagram (b) Toffoli gate block, HCD.ftc code, and a snapshot of the result
HG-PP
F2G F2G
F2G
HCD
Cell
(b)
.v a,b,c,d,e,f,g,h
.i a,b,c,d,e,f,g,h
.o a,b,c,d,e,f,g,h
BEGIN
T2 c,a
T2 e,a
T2 c,b
T2 e,d
T2 f,g
T2 f,h
T2 f,h
T2 f,a
T2 g,b
T2 g,d
END
HCD.tfc code
(a)
F2G
F2G
F2G
HG-PP
15. Novel conservative reversible error control circuits based on molecular QCA 15
Table 4 Cost metrics statistics of the hamming checker
Design Gate types GC CI GO UD QC QE
HC1
F2G 5 4 1 5 10 Y
HC2
(Circuit#1) FG, HCG 4 3 0 2 9 N
HC2
(Circuit#2) F2G, FG 6 3 0 4 8 N
HC2
(Circuit#3) F2G, PPHCG 5 8 5 2 14 N
HC2
(Circuit#4) F2G 6 7 4 4 12 N
Novel HG-PP, F2G 4 4 3 4 12 Y
% Improvement w.r.t
Haghparast et al.
+20 NI NI +20 +20
Notes: HC1
is designed in (Haghparast et al., 2011).
HC2
(Circuit#1) is designed in (James et al., 2007).
HC2
(Circuit#2) is designed in (James et al., 2007).
HC2
(Circuit#3) is designed in (James et al., 2007).
HC2
(Circuit#4) is designed in (James et al., 2007).
HC: Hamming checker.
Table 5 Cost metrics statistics of the hamming detector
Design Gate types GC CI GO UD QC QE
HD1
F2G 5 0 4 3 10 Y
HD2
(Circuit#5) HCG, FG 4 0 4 2 9 N
HD2
(Circuit#6) F2G 5 2 6 3 10 N
Novel HG-PP, F2G 4 1 5 2 10 Y
% Improvement w.r.t
Haghparast et al (2011)
+20 NI NI +33.33 NI
Notes: HD1
is designed in (Haghparast et al., 2011).
HD2
(Circuit#5) is designed in (James et al., 2007).
HD2
(Circuit#6) is designed in (James et al., 2007).
HD: Hamming detector, NI: No improvement.
GC: Gate count, CI: Constant input, GO: Garbage output, UD: Unit delay, QC: Quantum cost, QE: Quantum equivalent,
NI: No improvement, Y: Yes, N: No.
7.2.2 The Hamming code detector
The proposed Hamming code detector (HCD) is presented in
Figure 15a, which involves four gates (3xF2G, and 1xHG-
PP). The HCD is constructed herein using Algorithm 3. This
circuit involves Hamming input bits (H1, H2, H3, H4, H5, H6,
and H7) and only two constant inputs which are shown in
Figure 3. It produces three outputs (named as check bits): C1,
C2, and C3. All the check bits are specified by the equations 4,
5, and 6. In this circuit, QC of 10 which is marked by the
dotted black circuit in Figure 15b. In this circuit construction,
we report the algorithm 3.
Algorithm 3: Algorithm for the reversible HCD
Input: Take 7-bit data inputs Iv=Hi (i=1 to 7)
Output: Hamming code detector (named as HCD),
Outputs Ci (i=1 to 3)
1: Begin
2: Call (HCD)
3: Comment: Consider i=Input and o=Output
4: Begin
5: For i=0 to n-1 then
6: If i = 1 then
(H6, H7, 0) →F2G //Assign input to
first F2G
F2G ←
7 6 7 7
H ,H H ,H
// Three
intermediate output
End if, Else
7: (H1, H2, H3, H4, H5) →HG-PP
//Assign input to HG-PP
1 3 5 2 3 4 5
H H H ,H H ,H H
← HG-PP //
Three intermediate output
End if, Else
8: If i = 3 then
7 7 1 3 5
H ,H , H H H
→F2G // Assign input
to second F2G
1
C ← F2G // Catch one
output
End if, Else
16. 16 N.K. Misra, B. Sen and S. Wairya
6 7 2 3 4 5
H H , H H , H H
→F2G // Assign
input to third F2G
(C2, C3) ←F2G // Catch two
target output
HG-PP←(GO1, GO2), F2G←(GO3, GO4),
F2G←(GO5), //Remaining as GO
9: End if, Else if, end for,
10: Return (Hi) End;
1 1 3 5 7
WhereC H H H H
(4)
2 2 3 6 7
C H H H H
(5)
3 4 5 6 7
C H H H H
(6)
7.2.3 Observations and discussion
The circuit of HCD is required three check bits (C1, C2, C3).
In order to make the no error condition, three check bits
must be zero, otherwise, it shows error. The verification is
done by taking a certain condition when data bits are taken
as 1111. In this case, the parity bit computed as ‘111’ by
using equations (4), (5) and (6). Further, the check bits are
observed as ‘000’ by using equations (4), (5) and (6). This
ensures that the no-fault condition.
Cost metrics statistics for the proposed hamming
checker and hamming detector versus existing designs are
presented in Tables 4, and 5. Note that our circuit is
optimised with counterpart design and offers improved
reversible metrics.
8 Conclusions
The nanoscale devices are miniaturised, since there is a
challenge in the synthesis of correct outputs. The wrong
logic values in a complex circuit lead to the need for an
error detection and correction circuit. The work targets error
control circuits such as Hamming code, parity generator,
and parity checker, based on two novel reversible gates. In a
more general perspective, our proposed error control circuits
can be tackle in nano-communication problems such as
error control. Our constructed parity generator and parity
checker have achieved 83.3% and 66.6% improvement in
gate count respective as compared to counterpart designs.
On the other hand, Hamming generator and Hamming
checker circuit have achieved 33.33% and 66.66% gate
count respectively compared to the best counterpart designs.
Finally, the cost metrics results ensured the dominance of
our circuits over counterpart designs in consideration of
reversible metrics. QCADesigner tool is used to design and
verify the functionality of the proposed HG-PP and NG-PP
gates. QCAPro tool is used for energy dissipation analysis
of the HG-PP and NG-PP gates. Further, the proposed HG-
PP gate takes only cell count of 173, and 0.0993 meV
average leakage energy at 0.5Ek tunnelling energy level. In
the case of NG-PP gate requires only cell count of 255 and
0.2266 meV average leakage energy at 0.5Ek tunnelling
energy level. The presented circuits forms a valuable part in
building error control circuit for quantum-based computing.
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