The reversible logic circuit is popular due to its quantum gates involved where quantum gates are reversible and noted down feature of no information loss. In this paper, parity preserving reversible binary-to-BCD code converter is designed, and effect of reversible metrics is analyzed such as gate count, ancilla input, garbage output, and quantum cost. This design can build blocks of basic existing parity preserving reversible gates. The building blocks of the code converter reversible circuit constructed on Toffoli gate based as well as elemental gate based such as CNOT, C-V, and C-V+ gates. In addition, qubit transition analysis of the quantum circuit in the regime of quantum computing has been presented. The heuristic approach has been developed in quantum circuit construction and the optimized quantum cost for the circuit of binary-to-BCD code converter. Logic functions validate the development of quantum circuit. Moving the testability aim are figured in the quantum logic circuit testing such as single missing gate and single missing control point fault.

1. A Novel Parity Preserving Reversible
Binary-to-BCD Code Converter
with Testability of Building Blocks
in Quantum Circuit
Neeraj Kumar Misra, Bibhash Sen, Subodh Wairya and Bandan Bhoi
Abstract The reversible logic circuit is popular due to its quantum gates involved
where quantum gates are reversible and noted down feature of no information loss.
In this paper, parity preserving reversible binary-to-BCD code converter is
designed, and effect of reversible metrics is analyzed such as gate count, ancilla
input, garbage output, and quantum cost. This design can build blocks of basic
existing parity preserving reversible gates. The building blocks of the code con-
verter reversible circuit constructed on Toffoli gate based as well as elemental gate
based such as CNOT, C-V, and C-V+ gates. In addition, qubit transition analysis of
the quantum circuit in the regime of quantum computing has been presented. The
heuristic approach has been developed in quantum circuit construction and the
optimized quantum cost for the circuit of binary-to-BCD code converter. Logic
functions validate the development of quantum circuit. Moving the testability aim
are figured in the quantum logic circuit testing such as single missing gate and
single missing control point fault.
Keywords Reversible computation ⋅ Quantum circuit ⋅ Quantum Toffoli gate
Testability ⋅ Code converter
N. K. Misra (✉) ⋅ S. Wairya
Department of Electronics and Communication Engineering, Bharat Institute of Engineering
and Technology, Hyderabad 501510, India
e-mail: neeraj.mishra@ietlucknow.ac.in; neeraj.mishra3@gmail.com
B. Sen
Department of Computer Science and Technology, National Institute of Engineering
and Technology, Durgapur, India
B. Bhoi
Department of Electronics & Telecommunication, Veer Surendra Sai University
of Technology, Burla 768018, India
© Springer Nature Singapore Pte Ltd. 2018
V. Bhateja et al. (eds.), Proceedings of the Second International Conference
on Computational Intelligence and Informatics, Advances in Intelligent Systems
and Computing 712, https://doi.org/10.1007/978-981-10-8228-3_35
383

2. 1 Introduction
Over the last few decades, the reversible circuit has gained interest due to their low
energy dissipation [1]. The reversible circuit properties of recovered inputs and no
loss of information are a unique feature to look upon. In fact, the amount of heat
dissipation is related to information loss [2]. The noted down features of reversible
computing are recovered input states from output states, controllable inputs and
outputs, and zero energy dissipation [3]. The reversible technology in quantum
computation is expanded and becomes one of the prominent technologies in the
new era. Toffoli gates have found extensive building blocks in quantum circuit
construction. Increasing demand of the complex reversible circuit, it is a major
challenge to optimize the reversible parameters. To design a compact reversible
design, Toffoli gate blocks can be preferred [4]. The effort has been put to increase
the performance of the reversible circuit by optimizing the ancilla input, gate count,
garbage output, and quantum cost [5].
In this paper, we have proposed a parity preserving reversible binary-to-BCD
code converter. The quantum equivalent circuit is built from a standard library of
reversible gates such as NCT (NOT, CNOT, and Toffoli gates), MCT (multiple
control Toffoli gate), and NCV (NOT, CNOT, and the square root of NOT) [6].
Further, the high-level block of binary-to-BCD code converter to the respective
quantum equivalent circuit is framed successfully. The constructed circuit is opti-
mized regarding gate count, ancilla input, and quantum cost. The noted work of the
proposed circuit is the fault testing of the quantum circuit under a single missing
gate and single missing control point. To the best of our literature review on
reversible binary-to-BCD code converter circuit with the testability of quantum
circuit is not covered elsewhere.
The major pillars of this workaround quantum reversible code converter with
testability are highlighted as follows:
• In this work, a heuristic approach is used to synthesize the quantum circuit of
binary-to-BCD code converter. This approach depicts a promise to synthesize
the Toffoli gate-based quantum circuit and synthesis result, such as quantum
cost at a faster time in few seconds.
• A testability of quantum circuit is achieved by a single missing gate and single
control point-based fault detection. The target quantum reversible gates such as
FRG, F2G, NFT, RDC, and DFG gates are included with testability aspects.
This connection of paper is organized as follows. First, the essential background
of reversible and quantum computing is given. A term of the testing method base of
the quantum circuit is also covered as well. In Sect. 3, the previous work constraints
are provided. In Sect. 4, the synthesis of parity preserving reversible binary-to-BCD
code converter is presented. Section 5 provides an individual building block
testability methodology. The conclusion is discussed in Sect. 6.
384 N. K. Misra et al.

3. 2 Background of Reversible and Quantum Computing
We have discussed some terminologies such as reversible computing, quantum
computing, existing reversible gates implementation in Toffoli gate based, and
elemental quantum gates in this section.
2.1 Reversible and Quantum Computing
Definition 1 All reversible gate Boolean functions maintain the Bijective mapping
(onto and one-to-one).
Proof The reversible gate executes Bijective mapping in which a unique input
vector is mapped to unique output vectors and therefore an equal number of input
and output. Let us assume that reversible gate does not fulfill the criteria of
Bijective mapping, i.e., input is not equal to the output. The output is not recovered
the input and loss the reversibility. Hence, all reversible gates must hold the
Bijective mapping [7]. The feature of quantum gates is inherently reversible [8].
The quantum circuit construction with minimal quantum cost by using given
Boolean satisfiability (known as SAT) can be considered more effective in quantum
computing regime [4].
Multiple control Toffoli (MCT): The involvement of cascade MCT gates makes
reversible circuit compact. In MCT, gates are represented with ⊕ which is the
control gate and black dots means the control point. An n-input Toffoli gate is shown
as Yn (C, t) that map the reversible structure pattern as pi1, pi2, . . . . . . ..pik
ð Þ to
ðpi1, pi2, . . . . . . ..pk − 1, pk⊕pi1pi2 . . . . . . . . . . . . ..pk − 1pk + 1 . . . .pijÞ, where C = pi1,
ð
pi2, . . . . . . ..pikÞ, t = pi1
f g, C is denoted as control point, and t is donated as control
gate [9, 11]. CCNOT (TG) gate has three inputs and outputs. First two inputs (a, b)
are the control-bit, and the third input c is the target-bit (Fig. 1a). If the first
control-bit a is zero, it maps input CNOT (FG) gate (Fig. 1b). Again, if the first and
second control-bit a = b=0, it maps input NOT gate (Fig. 1c). In n-input Toffoli
gate, first n − 1
ð Þ input is noted as control-bit, and n-input is target-bit (Fig. 1d).
Control point
Target gate
a=0
(a) (b)
a=b=0
(c) (d)
Fig. 1 Multiple control Toffoli structures of a CCNOT, b CNOT, and c NOT d MCT
A Novel Parity Preserving Reversible Binary-to-BCD … 385

4. 2.2 Existing Parity Preserving Reversible Gates
Reversible decoder gate (RDC), and NFT gates: A 5 × 5 reversible decoder
(RDC) conserves parity at both inputs and outputs also known as parity preserving
reversible RDC gate [10]. The logical functions can be expressed as P = ab ⊕ a
⊕ c, q = ab ⊕ b ⊕ c, r = ab ⊕ c, s = ab ⊕ a ⊕ b ⊕ d, t = a ⊕ b ⊕ e. Figure 2a–c pre-
sents the Toffoli gate block and the quantum equivalent of FRG and RDC gates,
respectively.
The NFT gate executes the following three output functions: p = a ⊕ b, Q =
ac̄ ⊕ b̄c, r = ac̄ ⊕ bc, where a, b, and c are the inputs. Toffoli gate block and
elemental quantum gate-based structure of NFT have been shown in Fig. 2b.
Double Fredkin gate (DFG): The functional relationship between inputs and
outputs of DRG can be connected as p = a, q = āb ⊕ ac, r = āc ⊕ ab, s = ād ⊕ ae,
t = āe ⊕ ad. Figure 2d presents the Toffoli gate block and the quantum equivalent
of DFG gate. In all the quantum circuits in this work, we consider black dot as the
control point and the ⊕ (presented by exclusive OR) control gate.
3 Previous Work
In this section, we have reviewed the existing design of reversible binary-to-BCD
code converter. Researchers have worked on the various areas of reversible
binary-to-BCD code converters such as synthesis and optimization [12–15]. No any
previous research work on binary-to-BCD code converter such as testing of the
quantum logic circuit. However, the existing reversible code converter circuit still
suffers from difficulties such as more number of GC, GO, CI, and QC. Lower
values of reversible parameters are always preferred for circuit synthesis [16, 17]. In
existing work presented in [12] is reversible approach but not parity preserving
binary-to-BCD code converter. This design noted down parameters such as 17 GC,
(a) (b) (c) (d)
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6
1 2 3 4 5
Fig. 2 Reversible and quantum circuit of a FRG, b NFT, c RDC, and d DFG
386 N. K. Misra et al.

5. 12 GO, 13 CI, and 78 QC. Another existing work in [13] constructs the reversible
binary-to-BCD converter that takes GC of 7, GO of 2, and QC of 28. But this circuit
utilizes TG, which is non-parity preserving reversible gate. However existing
methodology is based on the quantum reversible circuit of binary-to-BCD converter
but not target the testing of quantum circuit. But here, lower value of gate count is
synthesized, and hence, the proposed binary-to-BCD code converter does not suffer
from the pitfalls discussed above of reversible design.
4 Synthesis of Proposed Binary-to-BCD Code Converter
The proposed binary-to-BCD code converter contains eight parity preserving
reversible gates the details of the utilizing gate such as one RDC, one DFG, one
F2G, two FRG, and three NFT; it has 19 inputs and 19 outputs.
Algorithm 1: Binary-to-BCD code converter
Input: I = (a, b, c, d) in binary, Output: Y = (Y0, Y1, Y2, Y3) in BCD.
1: For i=0 to n-1 do
2: If i=1 then
(c, d, 0, 1, 0) →1-RDC // Assign input to RDC gate
1-RDC← (a’1-RDC, b’1-RDC, c’1-RDC) // Three intermediate output
End if, Else
3: (b, d, c, 0, 0) →2-DFG // Assign input to 2-DFG
2-DFG← (a’2-DFG, c’2-DFG, e’2-DFG) // Three intermediate output to 2-DFG
End if, Else
4: If i=3 then
( a’2-DFG, 1, 0) →3-F2G // Assign input to 3-F2G
(b’3-F2G) ←3-F2G // One intermediate output of 3-F2G
End if, Else
5: (b’1-RDC, 0, b’3-F2G)→4-F2G // Assign input to 4-F2G
(Y4) ←4-F2G // Catch the one target output
6: If i=5 then
(c’2-DFG, 0, c) →5-FRG // Assign input to 5-FRG
(a’5-FRG, b’5-FRG) ←5-FRG // Two intermediate output of 5-FRG
End if, Else
(a’5-FRG, 0, c’1-RDC) →6-NFT // Assign input to 6-NFT
(Y3) ←6-NFT // Catch the one target output
6: If i=7 then
(e’ 2-DFG, 0, a’1-RDC) →7-NFT // Assign input to 7-NFT
(Y2) ←7-NFT // Catch the one target output
End if, Else
(b’ 5-FRG, 0, a’6-NFT) →8-NFT // Assign input to 8-NFT
(Y1) ←8-NFT // Catch the one target output
1-RDC← (g1, g2), 2-DFG←(g3, g4), 3-F2G←(g5, g6), 4-F2G←(g7, g8), 5-FRG←(g9),
6-NFT←(g10), 7-NFT←(g11, g12), 8-NFT←(g13, g14) // Remaining as garbage output
5: End if, end if, end for,
6: Return(Yi), End;
A Novel Parity Preserving Reversible Binary-to-BCD … 387

6. The inputs comprise four input information (a, b, c, d) in binary and 15 ancilla
inputs which are specified as constant 1 and 0. It produces four outputs such as
Y0 = a, Y1 = bcd + bd, Y2 = bc + cd ̄, Y3 = bd + cd, and Y4 = b̄c̄d. This circuit garbage
output is denoted by g. The functional diagram and quantum equivalent of
binary-to-BCD are presented in Figs. 3 and 4. In the quantum circuit construction,
we have used exact synthesis technique such as Boolean satisfactory (known as
SAT) to acquire compact circuit for reversible functions [18]. In this work, the
quantum circuit of proposed binary-to-BCD is achieved with Toffoli gate based.
However, the limitation of page dimensions is that we are not able to show the
quantum circuit of binary-to-BCD converter by elemental quantum gate based.
The QC of binary-to-BCD converter is 46. Algorithm 1 is shown for the synthesis
of this circuit. The QC (binary-to-BCD) is presented as 1QCRDC + 1 QCDEG +
2QCF2G + 1QCFRG + 3QCNFT = 9 + 10 + 2 × 2 + 5 + 3 × 6 = 46.
Fig. 4 The proposed quantum representation of the binary-to-BCD code converter
RDC
1
F2G
4
F2G
3
FRG
5
NFT
6
NFT
7
NFT
8
DFG
2
PP Reversible
Binary-to-BCD
converter
Ancilla
input
Garbage
output
(a) (b)
Fig. 3 The proposed binary-to-BCD code converter: a functional diagram and b cell diagram
388 N. K. Misra et al.

7. 5 Individual Building Block Testability Methodology
In the quantum circuit, the testing is essentially used to confirm a validate output. For
quantum circuit embedded to Toffoli gate, various faults were reviewed in
state-of-the-art [18]. In this paper, we have covered the single missing gate type fault
(SMGF) and single missing control type fault (SMCF). To test the fault in the
quantum circuit, two points should be considered: (i) if control gate is faulty, then the
information is unchanged in a quantum wire. (ii) In case of the CNOT gate, if a
control point is faulty, then the control gate changes the information in the quantum
wire [18]. Thus, these points must be remembered that the fault testing at the
quantum circuit. Therefore, we present the fault pattern structure of building blocks
used in binary-to-BCD. The building blocks are used in binary-to-BCD such as F2G,
FRG, NFT, RDC, and DFG. The procedure for fault patterns is generated in the
following description: First chose any test input vectors and found the target output
vectors. In the quantum circuit, faults are SMGF and SMCF. In SMGF change the bit
when the control gate is faulty as in the case of CNOT quantum logic structure.
In SMCF change the bit when the control point is faulty in the case of CNOT
quantum logic structure. The fault patterns of NFT, FRG, DFG, and RDC gates are
shown in Figs. 5, 6, 7, 8 and 9, respectively. The fault pattern lookup table for NFT,
FRG, DFG, and RDC gates is presented in Tables 1, 2, 3 and 4. By examining the
fault testing in the quantum circuit, it can be expected that control point and control
gate have played an important role in the synthesis of qubit transition in the quantum
circuit. The key feature of this work is integrated such as synthesis, optimisation, and
testing for a design flow of binary-to-BCD code converter.
According to Table 5, the proposed circuit provides a better result over the
counterpart circuits. The preliminary study reveals the significant improvement of
reversible parameters. The notations used in Table 5 are as follows: PP: Parity
preserving, QE: Quantum equivalent, GC: Gate count, CI: Constant input, GO:
Garbage output, QC: Quantum cost, -: Not mentioned, Y: Yes, and N: No.
[a,*]
[b,*] [b,c,*]
[b,a,*]
[b,*]
[c,*]
Fig. 5 Illustration of SMCF for NFT gate
[*,b] [*,a] [*,a,c]
[*,c] [*,b]
Fig. 6 Illustration of SMGF for NFT gate
A Novel Parity Preserving Reversible Binary-to-BCD … 389

8. [a,*]
[c,*,b] [c,a,*]
[b,*] [*,c] [*,a,b] [*,c]
(a) (b)
Fig. 7 Illustration of fault testing in FRG a SMCF and b SMGF
[*,a,b] [*,a,c] [*,a,b]
[*,d] [*,a,e] [*,d]
Fig. 8 Illustration of SMGF for DFG gate
[*,c] [*,a,b] [*,a] [*,e]
[*,c]
[*,b] [*,a]
[*,c]
Fig. 9 SMGF faults pattern in RDC gate
Table 1 Table for NFT gate with capture of both faulty and fault-free outputs
Design SMCF
Marking method Test in Target out Fault pattern
Figure 5 [a,*] 111 001 001
[b,*] 111 001 001
[b,c,*] 111 001 001
[b,a,*] 111 001 001
[b,*] 111 001 011 (Faulty)
[c,*] 111 001 001
SMGF
Figure 6 [*,b] 111 001 101 (Faulty)
[*,a] 111 001 001
[*,a,c] 111 001 001
[*,c] 111 001 010 (Faulty)
[*,b] 111 001 001
390 N. K. Misra et al.

9. Table 2 Table for FRG gate with the capture of both faulty and fault-free outputs
Design SMCF
Marking method Test in Target out Fault pattern
Figure 7 [a,*] 111 111 111
[c,*,b] 111 111 111
[c,a,*] 111 111 101 (Faulty)
[b,*] 111 111 101 (Faulty)
SMGF
[*,c] 111 111 110 (Faulty)
[*,a,b] 111 111 111
[*,c] 111 111 101 (Faulty)
Table 3 Table for DFG gate with the capture of both faulty and fault-free outputs
Design SMGF
Marking method Test in Target out Fault pattern
Figure 8 [*,a,b] 11111 11111 10111 (Faulty)
[*,a,c] 11111 11111 11111
[*,a,b] 11111 11111 11011 (Faulty)
[*,b] 11111 11111 11101 (Faulty)
[*,a,c] 11111 11111 11111
[*,d] 11111 11111 11110 (Faulty)
Table 4 Table for RDC gate with the capture of both faulty and fault-free outputs
Design SMGF
Marking method Test in Target out Fault pattern
Figure 9 [*,c] 11111 11001 10000 (Faulty)
[*,a,b] 11111 11001 00111 (Faulty)
[*,a] 11111 11001 10010 (Faulty)
[*,e] 11111 11001 11011 (Faulty)
[*,c] 11111 11001 11001
[*,b] 11111 11001 11001
[*,a] 11111 11001 10001 (Faulty)
[*,c] 11111 11001 11001 (Faulty)
Table 5 Comparison with counterpart designs and novel binary-to-BCD converter
Designs PP QE GC CI GO QC
Novel Y Y 8 12 14 46
[12] N N 17 13 12 78
[13] N N 7 – – 28
[14] N N 15 21 20 –
[15] N N 49 61 64 –
A Novel Parity Preserving Reversible Binary-to-BCD … 391

10. 6 Conclusions
In this paper, a quantum reversible circuit of binary-to-BCD code converter and the
testability of building blocks used in the circuit are proposed. The heuristic
approach is adopted for quantum circuit construction and gives better results with
optimizing quantum cost. The compact quantum circuit design is achieved when
Toffoli gate is embedded in the quantum circuit. The proposed circuit offers to
reduce the gate count, ancilla input, and quantum cost. In addition, we have
illustrated the individual quantum gates testability used in the schematic of
binary-to-BCD code converter by single missing control point fault and single
missing gate fault for it. An interesting future work would be to extend the data bits
in reversible binary-to-BCD code converter and fewer reversible parameters.
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