Nano Magnetic Logic (NML) has been attracting application in optical computing, nanodevice formation, and low power. In this paper nanoscale architecture such as the decoder, multiplexer, and comparator are implemented on perpendicular-nano magnetic logic (pNML) technology. All these architectures with the superiority of minimum complexity and minimum delay are pointed. The proposed architectures have been designed using pNML in MagCAD tool, simulated with modelsim platform and correctness shown by simulation waveform. The correctness of these designs can be verified easily when Verilog code is generated from MagCAD tool. The performance of the proposed comparator towards default parameters shows the area of 2.4336 μm2 and critical path of 1.5E-7 sec. As a higher order, the realization of a 4-to-1 multiplexer in NML has also been included in this work.
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Envi...VIT-AP University
Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
A novel vedic divider based crypto-hardware for nanocomputing paradigm: An ex...VIT-AP University
Restoring and non-restoring divider has become widely applicability in the era of digital computing application due to its computation speed. In this paper, we have proposed the design of divider of different architecture for the computation of Vedic sutra based. The design of divider in the Vedic mode results in
high computation throughput due to its replica architecture, where latency is minimized in each of the replica stages. The proposed novel divider based symmetric key crypto-hardware architecture for lightweight embedded devices and the results obtained for this architecture by the analysis using the QCADesigner tool. For the physical environment in QCA computing paradigm are achieved through optimization the
architecture of cell by using the robust design computing architecture. For the extended perspective of lower
divider to higher divider and to synthesize, target outcomes by using efficient architecture.
The document discusses reduced order modeling for transient analysis of carbon nanotube interconnects. It proposes using a half-T ladder network model and rational functions to develop a macromodel of a CNT interconnect from its per unit length parameters. The macromodel represents the interconnect admittance matrix using poles and residues, allowing for efficient transient analysis. Numerical results show the macromodel accurately captures the behavior of a CNT interconnect under various transient signals. An experimental setup is also developed to characterize CNT interconnects.
A New Approach for Solving Inverse Scattering Problems with Overset Grid Gene...TELKOMNIKA JOURNAL
This paper presents a new approach of Forward-Backward Time-Stepping (FBTS)
utilizing Finite-Difference Time-Domain (FDTD) method with Overset Grid Generation (OGG)
method to solve the inverse scattering problems for electromagnetic (EM) waves. The proposed
FDTD method is combined with OGG method to reduce the geometrically complex problem to a
simple set of grids. The grids can be modified easily without the need to regenerate the grid
system, thus, it provide an efficient approach to integrate with the FBTS technique. Here, the
characteristics of the EM waves are analyzed. For the research mentioned in this paper, the
‘measured’ signals are syntactic data generated by FDTD simulations. While the ‘simulated’
signals are the calculated data. The accuracy of the proposed approach is validated. Good
agreements are obtained between simulation data and measured data. The proposed approach
has the potential to provide useful quantitative information of the unknown object particularly for
shape reconstruction, object detection and others.
Master Thesis presentation.
Nanocomposite generator for energy harvesting from a bending movement.
Research: CNTs, Nanocomposites and Piezoelectric effect theoretical background.
Nanocomposite Generator modelling and practical experiment.
Results presentation.
New implementations for concurrent computing applications of 3D networks using corresponding nano and field-emission controlled-switching components are introduced. The developed implementations are performed within 3D lattice-based systems to perform the required concurrent computing. The introduced 3D systems utilize recent findings in field-emission and nano applications to implement the function of the basic 3D lattice networks using nano controlled-switching. This includes ternary lattice computing via carbon nanotubes and carbon field-emission techniques. The presented realization of lattice networks can be important for several reasons including the reduction of power consumption, which is an important specification for the system design in several future and emerging technologies, and in achieving high performance and reliability realizations. The introduced implementations for 3D lattice computations, with 2D lattice networks as a special case, are also important for the design within modern technologies that require optimal design specifications of high speed, high regularity and ease-of-manufacturability, such as in highly-reliable error-correcting signal processing applications.
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
Design High Performance Combinational Circuits Using Output Prediction Logic-...IOSRJECE
With the continuously increasing demand for low power & high speed VLSI circuits the brain storming among the scientists, inventors & researchers to find the techniques required to design such high performance circuits is also increasing day by day. In the answer to this search several design techniques have been found. Output prediction logic-OPL technique is one of such newly introduced techniques. OPL is a technique that can be applied to conventional CMOS logic families in order to obtain considerable speedups. Speedups of two to three times over static CMOS logic are demonstrated for a variety of combinational circuits. When applied to static CMOS the OPL retains the restoring nature of underlying logic family. In case of OPL applied to the pseudo NMOS & domino logic, the problem of excessive power dissipation is solved & speedups more than static CMOS logic is obtained
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Envi...VIT-AP University
Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
A novel vedic divider based crypto-hardware for nanocomputing paradigm: An ex...VIT-AP University
Restoring and non-restoring divider has become widely applicability in the era of digital computing application due to its computation speed. In this paper, we have proposed the design of divider of different architecture for the computation of Vedic sutra based. The design of divider in the Vedic mode results in
high computation throughput due to its replica architecture, where latency is minimized in each of the replica stages. The proposed novel divider based symmetric key crypto-hardware architecture for lightweight embedded devices and the results obtained for this architecture by the analysis using the QCADesigner tool. For the physical environment in QCA computing paradigm are achieved through optimization the
architecture of cell by using the robust design computing architecture. For the extended perspective of lower
divider to higher divider and to synthesize, target outcomes by using efficient architecture.
The document discusses reduced order modeling for transient analysis of carbon nanotube interconnects. It proposes using a half-T ladder network model and rational functions to develop a macromodel of a CNT interconnect from its per unit length parameters. The macromodel represents the interconnect admittance matrix using poles and residues, allowing for efficient transient analysis. Numerical results show the macromodel accurately captures the behavior of a CNT interconnect under various transient signals. An experimental setup is also developed to characterize CNT interconnects.
A New Approach for Solving Inverse Scattering Problems with Overset Grid Gene...TELKOMNIKA JOURNAL
This paper presents a new approach of Forward-Backward Time-Stepping (FBTS)
utilizing Finite-Difference Time-Domain (FDTD) method with Overset Grid Generation (OGG)
method to solve the inverse scattering problems for electromagnetic (EM) waves. The proposed
FDTD method is combined with OGG method to reduce the geometrically complex problem to a
simple set of grids. The grids can be modified easily without the need to regenerate the grid
system, thus, it provide an efficient approach to integrate with the FBTS technique. Here, the
characteristics of the EM waves are analyzed. For the research mentioned in this paper, the
‘measured’ signals are syntactic data generated by FDTD simulations. While the ‘simulated’
signals are the calculated data. The accuracy of the proposed approach is validated. Good
agreements are obtained between simulation data and measured data. The proposed approach
has the potential to provide useful quantitative information of the unknown object particularly for
shape reconstruction, object detection and others.
Master Thesis presentation.
Nanocomposite generator for energy harvesting from a bending movement.
Research: CNTs, Nanocomposites and Piezoelectric effect theoretical background.
Nanocomposite Generator modelling and practical experiment.
Results presentation.
New implementations for concurrent computing applications of 3D networks using corresponding nano and field-emission controlled-switching components are introduced. The developed implementations are performed within 3D lattice-based systems to perform the required concurrent computing. The introduced 3D systems utilize recent findings in field-emission and nano applications to implement the function of the basic 3D lattice networks using nano controlled-switching. This includes ternary lattice computing via carbon nanotubes and carbon field-emission techniques. The presented realization of lattice networks can be important for several reasons including the reduction of power consumption, which is an important specification for the system design in several future and emerging technologies, and in achieving high performance and reliability realizations. The introduced implementations for 3D lattice computations, with 2D lattice networks as a special case, are also important for the design within modern technologies that require optimal design specifications of high speed, high regularity and ease-of-manufacturability, such as in highly-reliable error-correcting signal processing applications.
Designing Conservative Reversible N-Bit Binary Comparator for Emerging Quantu...VIT-AP University
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This
work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a
conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative
reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new,
G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The
proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability
is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity,
and latency, which is found to be 0.52 m2, 387 and 1 respectively. In addition, the complete energy dissipation
analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average
energy dissipation v’s kink energy, maximum energy dissipation v’s kink energy, minimum energy dissipation
v’s kink energy and average output node polarization v’s temperature are provided in this paper. The proposed
comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage
outputs than its counterparts circuits, which ensure more scalable.
Design High Performance Combinational Circuits Using Output Prediction Logic-...IOSRJECE
With the continuously increasing demand for low power & high speed VLSI circuits the brain storming among the scientists, inventors & researchers to find the techniques required to design such high performance circuits is also increasing day by day. In the answer to this search several design techniques have been found. Output prediction logic-OPL technique is one of such newly introduced techniques. OPL is a technique that can be applied to conventional CMOS logic families in order to obtain considerable speedups. Speedups of two to three times over static CMOS logic are demonstrated for a variety of combinational circuits. When applied to static CMOS the OPL retains the restoring nature of underlying logic family. In case of OPL applied to the pseudo NMOS & domino logic, the problem of excessive power dissipation is solved & speedups more than static CMOS logic is obtained
Quantum-dot Cellular Automata (QCA) is an alternative innovation to the
Complementary Metal Oxide Semiconductor (CMOS) because CMOS has scaling
limitations that lead to high leakage power. QCA is structured on quantum cells, whose
sizes are on the nanoscale. This component causes faults in QCA circuits. Converting
a code into another that is programmed in logic arrays becomes important in the
physical realization of the circuits. There are many methods to resolve this problem in
circuits. A code converter is a solution to convert one code into another. In this paper,
QCA-based “4-bit binary-to-gray” and “4-bit gray-to-binary code converters” are
suggested. The offered layout prospects to a decrease in energy expenditure and can
be utilized in many fields for shielding data from outsiders and increasing information
flexibility. We executed a relative analysis of the suggested design with present earlier
designs and turned out that the suggested layout is productive on condition that
complexity, cell count, area intake, and clocking. This paper offers a streamlined design
and layout concerning code converters depending on QCA. These structures are
designed with the QCADesigner, simulator and the simulation results are examined.
IRJET- Design of Memristor based MultiplierIRJET Journal
This document describes the design of a 4-bit multiplier circuit using memristors. It begins with an introduction to memristors and their advantages over CMOS technology. It then discusses different window functions that can be used for memristor models and selects the Biolek window function. The document implements a 2-bit and 4-bit array multiplier circuit using memristor-CMOS hybrid logic gates. It analyzes the results in LTSpice and finds improvements in area and component count compared to traditional CMOS and other memristor-based designs. The document concludes memristors can help reduce area for multiplier circuits.
IMPLEMENTATION OF EFFICIENT ADDER USING MULTI VALUE LOGIC TECHNIQUEJournal For Research
1) The document presents the design of efficient quaternary half adders and full adders using multi-value logic techniques. It aims to minimize hardware, reduce power dissipation, and improve performance by designing the adders to operate directly on quaternary inputs and outputs without requiring conversion to or from binary.
2) The proposed quaternary half adder and full adder circuits are implemented using a voltage-mode approach in a 0.18um CMOS technology. Truth tables are provided to demonstrate the quaternary addition operations.
3) Prior work on arithmetic operations and adder implementations using multi-value logic are reviewed, identifying benefits such as reduced gate counts and interconnections compared to binary implementations
A simulation model of ieee 802.15.4 in om ne t++wissem hammouda
This document presents a simulation model of the IEEE 802.15.4 standard developed in OMNeT++. The model consists of PHY, MAC and traffic modules. The PHY module implements radio states, CCA and data rates according to the standard. The MAC module implements CSMA-CA, beaconing, data transmission modes and a simple energy model. The traffic module generates packets. The model supports star and cluster tree topologies and allows configuring parameters to evaluate IEEE 802.15.4 performance.
We present this work by two steps. In the first one, the new structure proposed of the FP-HEMTs device (Field plate High Electron Mobility Transistor) with a T-gate on an 4H-SIC substrate to optimize these electrical performances, multiple field-plates were used with aluminum oxide to split the single electric field peak into several smaller peaks, and as passivation works to reduce scaling leakage current. In the next, we include a modeling of a simulation in the Tcad-Silvaco Software for realizing the study of the influence of negative voltage applied to gate T-shaped in OFF state time and high power with ambient temperature, the performance differences between the 3FP and the SFP devices are discussed in detail.
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
This document discusses the design and implementation of a universal set of integrated circuit gates for multiple valued logic (MVL) circuits using CMOS 180nm technology. MVL circuits can reduce the number of interconnections needed compared to binary circuits. The document proposes a universal set of five CMOS gates - Maximum, Successor, and three extended AND operators - that can be used to synthesize any quaternary (base-4) MVL circuit. It describes implementing the gates in voltage mode by comparing input voltages to threshold voltages to discriminate the four logic levels, and using control switches to set the output levels. The goal is to prove the feasibility of these MVL gates for synthesizing combinational and sequential circuits using the proposed M
In this paper VLSI design have been introduce decrease the area and power CMOS 90 nm technology is used for designing nor gate. The power consumption and area of nor gate compared in this paper. The proposed design reduces the power consumption and area. The nor gate reduces power consumption by 46% and area by 67% .two design flow are implement, fully automatic and semicustom .the semicustom design better than fully automatic because in this design flow modification is done to minimize the power and area.
IRJET-Multiple Object Detection using Deep Neural NetworksIRJET Journal
The document describes a system for detecting multiple objects in videos using deep convolutional neural networks. The system first uses a Region Proposal Network to generate candidate object regions in each frame. It then applies a convolutional neural network to the full frame to extract features, and uses those features to classify and refine the bounding boxes for each proposed region. To improve detection across frames, the system also analyzes results from consecutive frames using a post-processing algorithm. The goal is to enhance confidence for consistently detected objects over time. Evaluation shows the approach effectively detects multiple objects in scenes from video frames.
logical effort based dual mode logic gates by mallikaMallika Naidu
Logic optimization and timing estimations are basic tasks for digital circuit designers. Dual Mode Logic (DML) allows operation in two modes such as static and dynamic modes. DML gates can be switched between these two modes on feature very low power dissipation in the static mode and high speed of operation in dynamic mode which is achieved at the expense of increased power dissipation. We introduce the logical effort (LE) methodology for the CMOS-based family. The proposed methodology allows path length, delay and power optimization for number of stages with load. Logical effort is the transistor sizing optimization methodology reduces the delay and power with number of stages with any static logic gate. The proposed optimization is shown for dual mode logic gates with logical effort using Digital Schematic Tool (DSCH).
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Implementing a neural network potential for exascale molecular dynamicsPFHub PFHub
The document discusses implementing a neural network potential for molecular dynamics simulations using the CabanaMD framework. Key points include:
- A neural network potential was implemented in CabanaMD using Kokkos/Cabana constructs, offering significant on-node scalability and the first GPU implementation of a neural network potential, showing up to 10x speedup over CPU.
- Data layout changes provided an additional 10% performance gain for the GPU implementation.
- For a nickel system, the GPU implementation achieved over 1 million atomsteps per second, vastly outperforming the water system.
- Future work includes exploring hierarchical parallelism and MPI scaling as well as applying machine learning techniques to other computational materials problems like phase
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
The document discusses efficient VLSI implementations of image encryption using minimal operations. It proposes using discrete cosine transform (DCT) for image compression and encryption simultaneously. For encryption, a linear feedback shift register generates random numbers added to some DCT outputs. The DCT algorithm and arithmetic operators are optimized to reduce operations and increase throughput. Simulation results show encryption in the frequency domain at 656 million samples per second on an 82 MHz clock.
HIGH SPEED REVERSE CONVERTER FOR HIGH DYNAMIC RANGE MODULI SETP singh
In this paper a new reverse converter architecture for the five moduli set {2n, 2n/2-1, 2n/2+1, 2n+1, 22n-1-1} is presented. The proposed converter is designed in two levels architecture by using of New Chinese Reminder Theorem-I (New CRT-I) and Mixed Radix Conversion (MRC). The proposed architecture has achieved significant improvement in terms of delay of the reverse converter compared to state-of-the-art reverse converters.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
TriBA(Triplet Based Architecture) is a Network on Chip processor(NoC) architecture which merges the
core philosophy of Object Oriented Design with the hardware design of multicore processors[1].We
present TriBASim in this paper, a NoC simulator specifically designed for TriBA.In TriBA ,nodes are
connected in recursive triplets .TriBA network topology performance analysis have been carried out from
different perspectives [2] and routing algorithms have been developed [3][4] but the architecture still lacks
a simulator that the researcher can use to run simple and fast behavioural analysis on the architecture
based on common parameters in the Network On Chip arena. TriBASim is introduced in this paper ,a
simulator for TriBA ,based on systemc[6] .TriBASim will lessen the burden on researchers on TriBA ,by
giving them something to just plug in desired parameters and have nodes and topology set up ready for
analysis.
Effect of Chirality and Oxide Thikness on the Performance of a Ballistic CNTF...IJECEIAES
Since the discovery of 1D nano-object, they are constantly revealing significant physical properties. In this regard, carbon nanotube (CNT) is considered as a promising candidate for application in future nanoelectronics devices like carbon nanotube field effect transistor (CNTFET). In this work, the impact of chirality and gate oxide thikness on the electrical characteristics of a CNTFET are studied. The chiralities used are (5, 0), (10, 0), (19, 0), (26, 0), and the gate oxide thikness varied from 1 to 5 nm. This work is based on a numerical simulation program based on surface potential model. CNTFET Modeling is useful for semiconductor industries for nano scale devices manufacturing. From our results we have observed that the output current increases with chirality increasing. We have also highlighted the importance of the gate oxide thickness on the drain current that increases when gate oxide is thin.
This document describes the design of different types of parallel multipliers using low power techniques on a 0.18um technology node. It discusses Braun multipliers, row-bypassing multipliers, and column-bypassing multipliers. The multipliers are implemented using both conventional methods and the Gate-Diffusion-Input (GDI) technique. Simulation results show that implementing the multipliers using GDI reduces transistor counts and power consumption compared to conventional implementations. The 4x4 Braun multiplier implemented with GDI uses 136 transistors and consumes 3mW of power, providing significant improvements over the conventional implementation.
Efficient architecture for arithmetic designs using perpendicular NanoMagneti...VIT-AP University
As the process of scaling down continues at a rapid pace, there is a growing need for an alternative semiconductor device to replace CMOS. One of the alternatives that attracted a lot of attention is called nanomagnetic logic (NML). This is because NML delivers a high device density in addition to a non-volatility of stored information, beyond-CMOS technologies, and device work at room temperature. It is necessary to lower the circuit density and increase the speed of circuits like adders. Using emerging NML logic, we created a full-adder, and ripple carry adder (RCA) with a minimum area. As a result, the invented multilayer-based decimal design makes use of RCA, and full-adder, for innovative 3D topology. We used an NML framework built with perpendicular nanomagnetic (pNML) layers to simulate the characteristics of these devices. With the adder designs that have been offered the latency values are relatively low while performing exhaustive testing. Using pNML technology, a decimal adder has been constructed for the first time in the literature. In addition, simulations are carried out with the help of the Modelsim simulator. During the process of nanomagnetic designing consideration is given to both of these aspects as latency and area. To create an NML circuit, the tool MagCAD is employed. Results are better using the pNML environment-based full adder, RCA and decimal adder.
Content Addressable Memory Design in 3D pNML for Energy-Aware Sustainable Com...VIT-AP University
As the semiconductor industry strives for downsizing and high speed, it is confronted with
increasing scaling uncertainty as devices decrease to the nanoscale. Nano-magnetic logic (NML) is an alternative approach to synthesize the digital logic circuits with high-density and lowpower
consumption. We introduced an optimal design of content addressable memory (CAM)
memory based on perpendicular nano-magnetic logic (pNML). The main aim of this implementation
is to synthesize CAM memory in terms of latency and other design parameters. The implementation of the design is a multilayer approach, which is optimal. The synthesis approach
and optimization are perfectly scalable across layout construction of designs. Here a new logic gate in pNML technology is designed which is mainly used for matching of two input numbers. According to insight, both memory unit and a matching unit in the pNML are introduced in the state-of-the-artwork for the ¯rst time to synthesize design in high-speed pNML application. MAGCAD tool is used for the design of all the proposed pNML layouts.
Study and Performance Analysis of MOS Technology and Nanocomputing QCAVIT-AP University
One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based
information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits
and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.
Quantum-dot Cellular Automata (QCA) is an alternative innovation to the
Complementary Metal Oxide Semiconductor (CMOS) because CMOS has scaling
limitations that lead to high leakage power. QCA is structured on quantum cells, whose
sizes are on the nanoscale. This component causes faults in QCA circuits. Converting
a code into another that is programmed in logic arrays becomes important in the
physical realization of the circuits. There are many methods to resolve this problem in
circuits. A code converter is a solution to convert one code into another. In this paper,
QCA-based “4-bit binary-to-gray” and “4-bit gray-to-binary code converters” are
suggested. The offered layout prospects to a decrease in energy expenditure and can
be utilized in many fields for shielding data from outsiders and increasing information
flexibility. We executed a relative analysis of the suggested design with present earlier
designs and turned out that the suggested layout is productive on condition that
complexity, cell count, area intake, and clocking. This paper offers a streamlined design
and layout concerning code converters depending on QCA. These structures are
designed with the QCADesigner, simulator and the simulation results are examined.
IRJET- Design of Memristor based MultiplierIRJET Journal
This document describes the design of a 4-bit multiplier circuit using memristors. It begins with an introduction to memristors and their advantages over CMOS technology. It then discusses different window functions that can be used for memristor models and selects the Biolek window function. The document implements a 2-bit and 4-bit array multiplier circuit using memristor-CMOS hybrid logic gates. It analyzes the results in LTSpice and finds improvements in area and component count compared to traditional CMOS and other memristor-based designs. The document concludes memristors can help reduce area for multiplier circuits.
IMPLEMENTATION OF EFFICIENT ADDER USING MULTI VALUE LOGIC TECHNIQUEJournal For Research
1) The document presents the design of efficient quaternary half adders and full adders using multi-value logic techniques. It aims to minimize hardware, reduce power dissipation, and improve performance by designing the adders to operate directly on quaternary inputs and outputs without requiring conversion to or from binary.
2) The proposed quaternary half adder and full adder circuits are implemented using a voltage-mode approach in a 0.18um CMOS technology. Truth tables are provided to demonstrate the quaternary addition operations.
3) Prior work on arithmetic operations and adder implementations using multi-value logic are reviewed, identifying benefits such as reduced gate counts and interconnections compared to binary implementations
A simulation model of ieee 802.15.4 in om ne t++wissem hammouda
This document presents a simulation model of the IEEE 802.15.4 standard developed in OMNeT++. The model consists of PHY, MAC and traffic modules. The PHY module implements radio states, CCA and data rates according to the standard. The MAC module implements CSMA-CA, beaconing, data transmission modes and a simple energy model. The traffic module generates packets. The model supports star and cluster tree topologies and allows configuring parameters to evaluate IEEE 802.15.4 performance.
We present this work by two steps. In the first one, the new structure proposed of the FP-HEMTs device (Field plate High Electron Mobility Transistor) with a T-gate on an 4H-SIC substrate to optimize these electrical performances, multiple field-plates were used with aluminum oxide to split the single electric field peak into several smaller peaks, and as passivation works to reduce scaling leakage current. In the next, we include a modeling of a simulation in the Tcad-Silvaco Software for realizing the study of the influence of negative voltage applied to gate T-shaped in OFF state time and high power with ambient temperature, the performance differences between the 3FP and the SFP devices are discussed in detail.
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
This document discusses the design and implementation of a universal set of integrated circuit gates for multiple valued logic (MVL) circuits using CMOS 180nm technology. MVL circuits can reduce the number of interconnections needed compared to binary circuits. The document proposes a universal set of five CMOS gates - Maximum, Successor, and three extended AND operators - that can be used to synthesize any quaternary (base-4) MVL circuit. It describes implementing the gates in voltage mode by comparing input voltages to threshold voltages to discriminate the four logic levels, and using control switches to set the output levels. The goal is to prove the feasibility of these MVL gates for synthesizing combinational and sequential circuits using the proposed M
In this paper VLSI design have been introduce decrease the area and power CMOS 90 nm technology is used for designing nor gate. The power consumption and area of nor gate compared in this paper. The proposed design reduces the power consumption and area. The nor gate reduces power consumption by 46% and area by 67% .two design flow are implement, fully automatic and semicustom .the semicustom design better than fully automatic because in this design flow modification is done to minimize the power and area.
IRJET-Multiple Object Detection using Deep Neural NetworksIRJET Journal
The document describes a system for detecting multiple objects in videos using deep convolutional neural networks. The system first uses a Region Proposal Network to generate candidate object regions in each frame. It then applies a convolutional neural network to the full frame to extract features, and uses those features to classify and refine the bounding boxes for each proposed region. To improve detection across frames, the system also analyzes results from consecutive frames using a post-processing algorithm. The goal is to enhance confidence for consistently detected objects over time. Evaluation shows the approach effectively detects multiple objects in scenes from video frames.
logical effort based dual mode logic gates by mallikaMallika Naidu
Logic optimization and timing estimations are basic tasks for digital circuit designers. Dual Mode Logic (DML) allows operation in two modes such as static and dynamic modes. DML gates can be switched between these two modes on feature very low power dissipation in the static mode and high speed of operation in dynamic mode which is achieved at the expense of increased power dissipation. We introduce the logical effort (LE) methodology for the CMOS-based family. The proposed methodology allows path length, delay and power optimization for number of stages with load. Logical effort is the transistor sizing optimization methodology reduces the delay and power with number of stages with any static logic gate. The proposed optimization is shown for dual mode logic gates with logical effort using Digital Schematic Tool (DSCH).
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Implementing a neural network potential for exascale molecular dynamicsPFHub PFHub
The document discusses implementing a neural network potential for molecular dynamics simulations using the CabanaMD framework. Key points include:
- A neural network potential was implemented in CabanaMD using Kokkos/Cabana constructs, offering significant on-node scalability and the first GPU implementation of a neural network potential, showing up to 10x speedup over CPU.
- Data layout changes provided an additional 10% performance gain for the GPU implementation.
- For a nickel system, the GPU implementation achieved over 1 million atomsteps per second, vastly outperforming the water system.
- Future work includes exploring hierarchical parallelism and MPI scaling as well as applying machine learning techniques to other computational materials problems like phase
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
The document discusses efficient VLSI implementations of image encryption using minimal operations. It proposes using discrete cosine transform (DCT) for image compression and encryption simultaneously. For encryption, a linear feedback shift register generates random numbers added to some DCT outputs. The DCT algorithm and arithmetic operators are optimized to reduce operations and increase throughput. Simulation results show encryption in the frequency domain at 656 million samples per second on an 82 MHz clock.
HIGH SPEED REVERSE CONVERTER FOR HIGH DYNAMIC RANGE MODULI SETP singh
In this paper a new reverse converter architecture for the five moduli set {2n, 2n/2-1, 2n/2+1, 2n+1, 22n-1-1} is presented. The proposed converter is designed in two levels architecture by using of New Chinese Reminder Theorem-I (New CRT-I) and Mixed Radix Conversion (MRC). The proposed architecture has achieved significant improvement in terms of delay of the reverse converter compared to state-of-the-art reverse converters.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
TriBA(Triplet Based Architecture) is a Network on Chip processor(NoC) architecture which merges the
core philosophy of Object Oriented Design with the hardware design of multicore processors[1].We
present TriBASim in this paper, a NoC simulator specifically designed for TriBA.In TriBA ,nodes are
connected in recursive triplets .TriBA network topology performance analysis have been carried out from
different perspectives [2] and routing algorithms have been developed [3][4] but the architecture still lacks
a simulator that the researcher can use to run simple and fast behavioural analysis on the architecture
based on common parameters in the Network On Chip arena. TriBASim is introduced in this paper ,a
simulator for TriBA ,based on systemc[6] .TriBASim will lessen the burden on researchers on TriBA ,by
giving them something to just plug in desired parameters and have nodes and topology set up ready for
analysis.
Effect of Chirality and Oxide Thikness on the Performance of a Ballistic CNTF...IJECEIAES
Since the discovery of 1D nano-object, they are constantly revealing significant physical properties. In this regard, carbon nanotube (CNT) is considered as a promising candidate for application in future nanoelectronics devices like carbon nanotube field effect transistor (CNTFET). In this work, the impact of chirality and gate oxide thikness on the electrical characteristics of a CNTFET are studied. The chiralities used are (5, 0), (10, 0), (19, 0), (26, 0), and the gate oxide thikness varied from 1 to 5 nm. This work is based on a numerical simulation program based on surface potential model. CNTFET Modeling is useful for semiconductor industries for nano scale devices manufacturing. From our results we have observed that the output current increases with chirality increasing. We have also highlighted the importance of the gate oxide thickness on the drain current that increases when gate oxide is thin.
This document describes the design of different types of parallel multipliers using low power techniques on a 0.18um technology node. It discusses Braun multipliers, row-bypassing multipliers, and column-bypassing multipliers. The multipliers are implemented using both conventional methods and the Gate-Diffusion-Input (GDI) technique. Simulation results show that implementing the multipliers using GDI reduces transistor counts and power consumption compared to conventional implementations. The 4x4 Braun multiplier implemented with GDI uses 136 transistors and consumes 3mW of power, providing significant improvements over the conventional implementation.
Efficient architecture for arithmetic designs using perpendicular NanoMagneti...VIT-AP University
As the process of scaling down continues at a rapid pace, there is a growing need for an alternative semiconductor device to replace CMOS. One of the alternatives that attracted a lot of attention is called nanomagnetic logic (NML). This is because NML delivers a high device density in addition to a non-volatility of stored information, beyond-CMOS technologies, and device work at room temperature. It is necessary to lower the circuit density and increase the speed of circuits like adders. Using emerging NML logic, we created a full-adder, and ripple carry adder (RCA) with a minimum area. As a result, the invented multilayer-based decimal design makes use of RCA, and full-adder, for innovative 3D topology. We used an NML framework built with perpendicular nanomagnetic (pNML) layers to simulate the characteristics of these devices. With the adder designs that have been offered the latency values are relatively low while performing exhaustive testing. Using pNML technology, a decimal adder has been constructed for the first time in the literature. In addition, simulations are carried out with the help of the Modelsim simulator. During the process of nanomagnetic designing consideration is given to both of these aspects as latency and area. To create an NML circuit, the tool MagCAD is employed. Results are better using the pNML environment-based full adder, RCA and decimal adder.
Content Addressable Memory Design in 3D pNML for Energy-Aware Sustainable Com...VIT-AP University
As the semiconductor industry strives for downsizing and high speed, it is confronted with
increasing scaling uncertainty as devices decrease to the nanoscale. Nano-magnetic logic (NML) is an alternative approach to synthesize the digital logic circuits with high-density and lowpower
consumption. We introduced an optimal design of content addressable memory (CAM)
memory based on perpendicular nano-magnetic logic (pNML). The main aim of this implementation
is to synthesize CAM memory in terms of latency and other design parameters. The implementation of the design is a multilayer approach, which is optimal. The synthesis approach
and optimization are perfectly scalable across layout construction of designs. Here a new logic gate in pNML technology is designed which is mainly used for matching of two input numbers. According to insight, both memory unit and a matching unit in the pNML are introduced in the state-of-the-artwork for the ¯rst time to synthesize design in high-speed pNML application. MAGCAD tool is used for the design of all the proposed pNML layouts.
Study and Performance Analysis of MOS Technology and Nanocomputing QCAVIT-AP University
One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based
information flow. This manuscript analysis and design a combinational digital circuits in an emerging QCA framework. The design is evaluated and formulated in terms of area, latency and power dissipation. QCA Designer tool has been taken for the design of quantum cell-based combinational circuits
and simulation purpose. Moreover, it is believed based on experimental analysis that the QCA based combination circuits will make a contribution to high computing speed and low power paradigm.
Performance evaluation of reversible logic based cntfet demultiplexer 2IAEME Publication
This document discusses the design and analysis of a reversible logic based carbon nanotube field effect transistor (CNTFET) demultiplexer. It presents the realization of 1:2 and 1:4 demultiplexers using reversible logic gates implemented with CNTFETs. Simulation results show the transient response and power consumption of the reversible logic CNTFET demultiplexers, with 0.8 and 1.6 nanowatts for the 1:2 and 1:4 designs respectively. This is compared to conventional CMOS demultiplexer designs, showing an improvement in power reduction achieved with the reversible logic CNTFET approach. Challenges in CNT fabrication that could impact robust circuits are also discussed.
Performance evaluation of reversible logic based cntfet demultiplexer 2IAEME Publication
This document discusses the design and analysis of a reversible logic based carbon nanotube field effect transistor (CNTFET) demultiplexer. It presents the realization of 1:2 and 1:4 demultiplexers using reversible logic gates implemented with CNTFETs. Simulation results show the transient response and power consumption of the reversible logic CNTFET demultiplexers, with 0.8 and 1.6 nanowatts for the 1:2 and 1:4 designs respectively. This is compared to conventional CMOS demultiplexer designs, showing an improvement in power reduction achieved with the reversible logic CNTFET approach. Challenges in fabricating robust CNT-based circuits are also discussed.
A modular approach for testable conservative reversible multiplexer circuit f...VIT-AP University
Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent
part of any system-level design. In this article, the significant module of a multiplexer, an extended to n:1 is framed with
prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm,
which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing
framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative
reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters
in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count,
quantum cost and unit delay are optimal.
Presentation of a fault tolerance algorithm for design of quantum-dot cellul...IJECEIAES
A novel algorithm for working out the Kink energy of quantum-dot cellular automata (QCA) circuits and their fault tolerability is introduced. In this algorithm at first with determining the input values on a specified design, the calculation between cells makes use of Kink physical relations will be managed. Therefore, the polarization of any cell and consequently output cell will be set. Then by determining missed cell(s) on the discussed circuit, the polarization of output cell will be obtained and by comparing it with safe state or software simulation, its fault tolerability will be proved. The proposed algorithm was implemented on a novel and advance fault tolerance full adder whose performance has been demonstrated. This algorithm could be implemented on any QCA circuit. Noticeably higher speed of the algorithm than simulation and traditional manual methods, expandability of this algorithm for variable circuits, beyond of four-dot square of QCA circuits, and the investigation of several damaged cells instead just one and special cell are the advantages of algorithmic action.
International Journal of Computer Science & Information Technology (IJCSIT) ijcsit
New implementations for concurrent computing applications of 3D networks using corresponding nano and field-emission controlled-switching components are introduced. The developed implementations are performed within 3D lattice-based systems to perform the required concurrent computing. The introduced 3D systems utilize recent findings in field-emission and nano applications to implement the function of the basic 3D lattice networks using nano controlled-switching. This includes ternary lattice computing via carbon nanotubes and carbon field-emission techniques. The presented realization of lattice networks can be important for several reasons including the reduction of power consumption, which is an important specification for the system design in several future and emerging technologies, and in achieving high performance and reliability realizations. The introduced implementations for 3D lattice computations, with 2D lattice networks as a special case, are also important for the design within modern technologies that require optimal design specifications of high speed, high regularity and ease-of-manufacturability, such as in highly-reliable error-correcting signal processing applications.
Implementation of Non-restoring Reversible Divider Using a Quantum-Dot Cellul...VIT-AP University
The document describes the design and implementation of a non-restoring reversible divider circuit using quantum-dot cellular automata (QCA). Key points:
1) A non-restoring divider circuit was designed using Feynman and Haghparast gates in a reversible logic approach to minimize quantum cost and garbage outputs.
2) The divider circuit was synthesized and implemented in QCADesigner, achieving a cell complexity of 269 and area of 0.54 μm2.
3) The proposed reversible divider design was shown to have lower quantum cost, fewer garbage outputs, and gates than previous non-reversible divider designs.
This document discusses applications of nanotechnology including nanocells, carbon nanotubes, and molecular electronics. Nanocells are self-assembled networks of metallic particles that act as programmable switches. Carbon nanotubes are rolled sheets of carbon that can be semiconductors or metals and are strong candidates for nanowires. Potential applications highlighted include using carbon nanotubes for transistors, fuel cells, and simulation. Other applications discussed are nanobridge devices, nanoscale transistors, components for quantum computers, nanophotonic devices, and nanobiochips for drug discovery.
Regular clocking scheme based design of cost-efficient comparator in QCAnooriasukmaningtyas
Quantum-dot cellular automata (QCA) gained a notable attraction in the emerging nanotechnology to get the better of power consumption, density, nano-scale design, the performance of the present CMOS technology. Many designs had been proposed in QCA for an arithmetic circuit like adder, divider, parity checker and comparator etc. Most of the designs have been facing the challenges of cost efficiency, power dissi-pation, device density etc. However, consideration of design automation, underlying clocking layout and integration of the sub modules are the most important which has a direct impact on the fabrication of the design. This work proposed a novel cost ef-fective and power aware comparator design, which is an essential segment in central processing unit (CPU). The noticeable novelty of the design was the use of underlying regular clocking scheme. A new scalable, regular clocking scheme has been utilized in the coplanar design of the comparator which enables regular or uniform cell layout of QCA circuit. It also exhibited the significant improvement over existing counterparts having irregular clocking in terms of area and latency. QCADesigner was used to test and verify the functionality of the circuit and by using QCAPro the power dissipation has been analyzed.
This paper investigates about the possibility to reduce power consumption in Neural Network using approximated computing techniques. Authors compare a traditional fixed-point neuron with an approximated neuron composed of approximated multipliers and adder. Experiments show that in the proposed case of study (a wine classifier) the approximated neuron allows to save up to the 43% of the area, a power consumption saving of 35% and an improvement in the maximum clock frequency of 20%.
PARALLEL BIJECTIVE PROCESSING OF REGULAR NANO SYSTOLIC GRIDS VIA CARBON FIELD...ijcsit
New implementations for parallel processing applications using reversible systolic networks and the
corresponding nano and field-emission controlled-switching components is introduced. The extensions of
implementations to many-valued field-emission systolic networks using the introduced reversible systolic
architectures are also presented. The developed implementations are performed in the reversible domain to
perform the required parallel computing. The introduced systolic systems utilize recent findings in field
emission and nano applications to implement the function of the basic reversible systolic network using
nano controlled-switching. This includes many-valued systolic computing via carbon nanotubes and carbon
field-emission techniques. The presented realization of reversible circuits can be important for several
reasons including the reduction of power consumption, which is an important specification for the system
design in several future and emerging technologies, and also achieving high performance realizations. The
introduced implementations for non-classical systolic computation are new and interesting for the design
within modern technologies that require optimal design specifications of high speed, minimum power and
minimum size, which includes applications in adiabatic low-power signal processing.
Novel conservative reversible error control circuits based on molecular QCAVIT-AP University
Quantum-dot cellular automata are a prominent part of the nanoscale regime. They
use a quantum cellular based architecture which enables rapid information process with high
device density. This paper targets the two kinds of novel error control circuits such as Hamming
code, parity generator and checker. To design the HG-PP (HG = Hamming gate, PP = parity
preserving), NG-PP (NG = new gate) are proposed for optimising the circuits. Based on the
proposed gates and a few existing gates, the Hamming code and parity generator and checker
circuits are constructed. The proposed gates have been framed and verified in QCA. The
simulation outcomes signify that their framed circuits are faultless. In addition to verification,
physical reversible is done. The reversible major metrics such as gate count, quantum cost, unit
delay, and garbage outputs, uses best optimisation results compared to counterparts. They can be utilised as a low power error control circuit applied in future communication systems.
Silicon Photonics and Photonic NoCs: A Surveydrv11291
This document summarizes a survey on silicon photonics and photonic Networks-on-Chip (NoCs). It discusses why photonic interconnects could replace metallic interconnects due to issues like RC delays and data transfer rates. It describes early work on the idea of silicon photonics and how photonic NoCs would affect router structures and architectures. The document summarizes several proposed photonic NoC architectures, routers, and simulation tools. It discusses tradeoffs between latency, throughput, and power for different architectures. While photonic NoCs show potential for improved performance, the document concludes that design and fabrication tools still need development before they can be considered practically viable for multi-core systems-on-chips.
IRJET- A Novel Design of Flip Flop and its Application in Up CounterIRJET Journal
1) The document proposes a novel design of flip flops and a 4-bit up counter using Quantum-Dot Cellular Automata (QCA) technology. QCA is an emerging nanotechnology that could overcome scaling limitations of CMOS.
2) In QCA, logic states are represented by the position of electrons in quantum dots rather than voltage as in CMOS. Basic logic gates like inverters and majority gates are constructed using QCA cells.
3) The document designs various flip flops like SR, JK, D, and T flip flops in QCA and uses them to build a 4-bit up counter. Power consumption is shown to be lower for the QCA designs compared to
This document describes the design and simulation of a parallel-coupled microstrip bandpass filter using space mapping techniques. The filter structure consists of a conductor on top of a dielectric substrate backed by a ground plane. An electromagnetic simulator is used to simulate the fine model, while a fast approximate model is used for optimization. Space mapping establishes a relationship between the two models to optimize the design while maintaining accuracy. The proposed 9-10 GHz bandpass filter was designed and simulated using ADS, demonstrating good compactness and low insertion loss.
CNTFET Based Analog and Digital Circuit Designing: A ReviewIJMERJOURNAL
ABSTRACT: Silicon has been a material of choice for the last many decades and more than 95% of electronics devices are from silicon. However, silicon has reached to its saturation level and extracting more and more performance is difficult and costly now. A new material which has a potential to replace Si and can extend the scalability of devices below 22 nm is the carbon nanotube (CNT). CNT is a wonderful material possesses unique properties that make it a promising future material. CNT based field effect transistor (Cntfet) is a promising basic building block to complement the existing silicon based MOSFET and can result in the extension of the validity of Moore's law further. CNTFT has been used extensively in realizing electronics circuits. This paper presents the state of the art literature related to carbon nanotubes, carbon nanotube field effect transistors and CNTFET based circuit designing. A review of Cntfet based analog and digital circuits has been presented. It has been observed that the use of CNTFET has improved the performance of both analog and digital circuits. The work will be very useful to the people working in the field of CNT based analog and digital circuit designing.
IRJET- An Evaluation of the Performance Parameters of CMOS and CNTFET based D...IRJET Journal
The document compares the performance parameters of CMOS and carbon nanotube field-effect transistor (CNTFET) based delay lines at a 32nm technology node. A simulation study found that CNTFET delay lines exhibited improved results over CMOS for parameters like propagation delay, leakage power, and leakage current. Specifically, leakage power decreased and average power consumption was lower in CNTFET delay lines. So CNTFETs showed better evaluation and performance metrics than CMOS for delay lines.
Modelling of next zen memory cell using low power consuming high speed nano d...eSAT Journals
Abstract Hybrid SET-CMOS circuits which syndicate the assets of both the SET [Single Electron Transistor] and CMOS depicts highest possibilities to be incorporated in practical implementation for future low power VLSI/ULSI configurations. The proposed work is an attempt based on SET-CMOS hybrid circuit to realize the next gen simple Memory Cell. The authors adhered to MIB model for SET and BSIM4 model for CMOS in realizing the complex cell. The maneuver of the proposed circuit is verified subsequently in standard environment. The outcomes are in good trade off with the conventional statistics of existing memory cell. Keywords: SET, SED, Hybrid CMOS-SET, MIB and Memory Cell
Similar to Design of magnetic dipole based 3D integration nano-circuits for future electronics application (20)
The impact of quantum computing has been widely recognised in the engineering domain. The age of quantum computing has arrived, and with it comes the ability to easily solve exponential problems. This book is written by me to meet current academic demands. The book is designed to address the most important aspects of the subject of Quantum Computing. The publication of the book "Quantum Computing" is the culmination of numerous years of research and teaching in academia. It is given in a way that is straightforward to comprehend. The undergraduates, and graduate students may all benefit from reading this book. We have given our very best effort to bring you accurate book material.
The book explains the fundamentals of this topic in simple, straightforward language. The most efficient approach to go through this book is to grasp the underlying fundamental as well as mathematical concepts. The chapters are meant to stand on their own. This book is not intended to be theoretical; rather, it will serve to familiarise you with the fundamental of quantum computing, like applications, multiple-qubit systems, quantum state transformations, quantum gates and quantum circuits, tools for quantum computing, bell states, quantum Parallelism, quantum Algorithms: Shor’s Algorithm, Grover’s Algorithm, Quantum Hardware and software, Quantum Cryptography and Security, Quantum Error Rates and Quantum Noise, Quantum Fourier Transform, Quantum Machine Learning and so on.
The model questions and multiple-choice questions that are provided at the end of the book have been chosen to improve readers' understanding, as well as their performance in exams and key employment.
We warmly welcome and would be very appreciative of any comments or recommendations, that will help us enhance the overall quality of the book.
Cost-effective architecture of decoder circuits and futuristic scope in the e...VIT-AP University
The goal of Very Large Scale Integration (VLSI) over the past several decades has been the miniaturisation of chip size, along with increased computing speed and decreased power consumption. Miniaturization of size, high computing speed, and low power consumption does not appear to be able to meet the demand of consumers at this time. Quantum dot cellular automata is a more promising methodology that has the potential to optimise power, speed, and area at the nano-computing scale. In the field of nanocomputing, combinational circuit design has seen a significant amount of research and development effort. This article presents a comprehensive review as well as a proposed design of a decoder that has an accurate clocking mechanism and the best design. In terms of cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost, the novel 2-to-4 decoder achieves values of 87, 0.10, 0.0281, 28.1, 2.5, 0.625, 0.25, which is better than the prior work. Comparing the 2-to-4 decoder design to a standard design, the improvement is 72.64 %, 80 %, 72.71 %, 28.1 %, 64.28 %, 97,44 and 92.85 % in cell count, total area, cell area, area coverage, latency, QCA cost, and Quantum cost, respectively.
Dr. Neeraj Kumar Misra is an Associate Professor who teaches Information Theory and Coding. Some of his qualifications and accomplishments include: a Ph.D from VIT-AP University under a TEQIP-II fellowship, a postgraduate diploma in artificial intelligence and machine learning from NIT Warangle, three granted international patents, over 9 years of teaching and industry experience, 14 publications in SCI journals, and 325 citations on Google Scholar with an h-index of 11. He is a professional member of several organizations and serves on the editorial boards of multiple journals.
An in-depth study of the electrical characterization of supercapacitors for r...VIT-AP University
The Energy Storage System (ESS) is geared toward sophisticated systems with increased operating time for a variety of real-time applications such as an electric vehicle, a WSN (Wireless Sensor Network), a Capa bus, and so
on. Its primary focus is on supplying these kinds of systems with additional capacity in recent development, and
this will continue to be its primary focus. Because of their exceptionally high specific power, rapid charging, and
low ESR (Effective Series Resistance), electric double-layer (EDLC) capacitors or supercapacitors are encouraged
for use because they can be integrated more easily with battery technology that can be used in electric vehicles
and other electronic devices. The supercapacitor calls for a precise and accurate characterization in order to
facilitate the development of improved applications and more effective energy storage devices and technologies.
In this article, we studied various supercapacitor electrode components, electrolytic solutions, analogous circuit
models, electrical energy storage properties, and some real-time supercapacitor applications in the automotive,
manufacturing, construction, and consumer electronics industries. In addition, we have discussed on hybrid
material that was just recently developed with the goal of enhancing the conductivity and effectiveness of supercapacitors. Aside from this, we have discussed about the behaviour of supercapacitors in terms of how their behaviour is dependent on current and voltage with detailed analysis.
Agenda
1. Algorithm of Reading Scientific Research Article
2. Importance of ORCID ID
3. Benefit of ORCiD
4. Process of Connecting Scopus database to ORCiD iD
5. Registration of ORCiD iD Account
6. Scopus Database connected to ORCiD iD
7. BibTeX Entry to add all the publication at the same time in ORCiD iD
8. Process of importing BibTex into ORCiD Database
9. Using Bibtex include all the research article in one time
How to Calculate the H-index and Effective Response of ReviewerVIT-AP University
The document provides information on calculating the H-index and responding effectively to reviewer comments. It discusses that the H-index measures both the productivity and citation impact of a scientist's publications. The H-index is based on the scientist's most cited papers and the number of citations they received. The document also provides common phrases to use in responding to reviewer comments and thanks the reviewers for their feedback to strengthen the manuscript. Useful research tools and links are also listed.
Dr. Neeraj Misra presented on the importance of obtaining an ORCID ID. An ORCID ID is a unique identifier that helps link researchers to their work activities and publications. It helps distinguish researchers from others with similar names and allows researchers to add all of their publications at once to their profile. Obtaining an ORCID ID only takes a few minutes and helps give proper attribution and credit for research works.
Writing and Good Abstract to Improve Your Article QualityVIT-AP University
This document provides an overview of a presentation on writing good abstracts to improve article quality. The presentation covers topics like journal ranking, using Mendeley software, how to structure an article, how editors review papers, calculating citation metrics like cite score and h-index, and maintaining research profiles and accounts. Useful research tools and links are also listed. The presentation aims to provide guidance on writing strong abstracts and improving the overall quality of research publications.
Fundamental of Electrical and Electronics Engineering.pdfVIT-AP University
The document provides an introduction to Dr. Neeraj Kumar Misra, an Associate Professor in the Department of SENSE at VIT-AP University. It lists his qualifications including a Ph.D, publications, awards, projects completed, and professional memberships. It also outlines the content to be covered in the course on Fundamentals of Electrical and Electronics Engineering including topics like electric current, Ohm's law, circuit theory, and component symbols.
Performance Evaluation & Design Methodologies for Automated 32 Bit CRC Checki...VIT-AP University
For design methodology of CRC or cyclic redundancy check is very used technique for error checking and shows the transmission reliability we are using the HDLC block. HDLC block is very useful in data communication these block operated in data link layer. For design methodology of CRC is to generate the CRC polynomial using XOR’s gate and shift register these polynomial are implement on software Xilinx Plan Ahead 13.1 and verify for simulation result for random testing of CRC bit on receiver side same result are obtained to show that it is more reliable.
Sensor Energy Optimization Using Fuzzy Logic in Wireless Sensor NetworkingVIT-AP University
Wireless sensor networks is challenging in that it requires an enormous breadth of knowledge from an enormous variety of disciplines. A lot of study has been done to minimize the energy used in routing and number of protocols has been developed. These protocols can be classified as - Hierarchical, data centric, location based and Network flow protocols. In this paper, we are particularly focusing on hierarchical protocols. In such types of protocols, the energy efficient clusters are formed with a hierarchy of cluster heads. Each cluster has its representative cluster head which is responsible for collecting and aggregating the data from its respective cluster and then transmitting this data to the Base Station either directly or through the hierarchy of other cluster heads. Fuzzy logic has been successfully applied in various areas including communication and has shown promising results. However, the potentials of fuzzy logic in wireless sensor networks still need to be explored. Optimization of wireless sensor networks involve various tradeoffs, for example, lower transmission power vs. longer transmission duration, multi-hop vs. direct communication, computation vs. communication etc. Fuzzy logic is well suited for application having conflicting requirements. Moreover, in WSN, as the energy metrics vary widely with the type of sensor node implementation platform, using fuzzy logic has the advantage of being easily adaptable to such changes.
Approach to design a high performance fault-tolerant reversible ALUVIT-AP University
In the digital circuit design, the primary factors are low power and a high packing density. The reversible logic circuit in quantum-dot cellular
automata (QCA) framework is hoped to be effective in addressing the factor of power consumption at nanoscale regime. Fault tolerant circuits are suited of interruption of errors at the outputs. This manuscript focuses the design of ALU in QCA-based and propose new parity preserving gate. It has been introduced that new reversible gate, namely, universal parity preserving gate (UPPG), to
optimise the ALU circuits. An algorithm and lemmas are shown in designing ALU. The ALU generates a number of arithmetic and logical function with using only less architectural complexity. Most importantly circuit design
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Analysis on Fault Mapping of Reversible Gates with Extended Hardware Descript...VIT-AP University
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Design of magnetic dipole based 3D integration nano-circuits for future electronics application
1. Int. J. Nano Dimens., 9 (4): 374-385, Autumn 2018
ORIGINAL ARTICLE
Design of magnetic dipole based 3D integration nano-circuits for
future electronics application
Bandan Kumar Bhoi 1
, Neeraj Kumar Misra 2 ,
*, Manoranjan Pradhan 1
1
Department of Electronics and Telecommunication, Veer Surendra Sai University of Technology,
Odisha, India
2
Department of Electronics and Communication Engineering, Bharat Institute of Engineering and
Technology, Hyderabad, India
Received 08 April 2018; revised 14 June 2018; accepted 19 June 2018; available online 20 June 2018
* Corresponding Author Email: neeraj.misra@ietlucknow.ac.in
How to cite this article
Bhoi BK, Misra NK, Pradhan M. Design of magnetic dipole based 3D integration nano-circuits for future electronics application.
Int. J. Nano Dimens., 2018; 9 (4): 374-385.
Abstract
Nano Magnetic Logic (NML) has been attracting application in optical computing, nanodevice formation,
and low power. In this paper nanoscale architecture such as the decoder, multiplexer, and comparator are
implemented on perpendicular-nano magnetic logic (pNML) technology. All these architectures with the
superiority of minimum complexity and minimum delay are pointed. The proposed architectures have
been designed using pNML in MagCAD tool, simulated with modelsim platform and correctness shown by
simulation waveform. The correctness of these designs can be verified easily when Verilog code is generated
from MagCAD tool. The performance of the proposed comparator towards default parameters shows the
area of 2.4336 µm2 and critical path of 1.5E-7 sec. As a higher order, the realization of a 4-to-1 multiplexer
in NML has also been included in this work.
Keywords: Comparator; Decoder; Latency; Multiplexer; NML; pNML; QCA.
This work is licensed under the Creative Commons Attribution 4.0 International License.
To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/.
INTRODUCTION
Nano Magnetic Logic (NML) is an emerging
technology, which has the ability to replace current
CMOS technology because of operating capability
in room temperature, high-density integration,
low power consumption, non-volatility and
absence of, interconnect wires [1]. It has also the
facility to integrate logic and memory functionality
into the same device, which denotes its great
potential for future technology. Perpendicular-
nano magnetic logic (pNML) also has the
advantages of enabling the fabrication of three-
dimensional (3-D) circuits. The fabrication of these
3-D circuits is not cost efficient in conventional
CMOS technology because of the presence of
vertical interconnections (vias). However, this
designing will be very much efficient in pNML
technology because of the presence of different
layers. To explore this technology simulation
tools are needed for designing architectures of
nano magnetic logic circuits. Different low-level
simulators such as NMAG [2], OOMMF [3] or
MUMAX [4] are present for simulating magnetic
circuits. But these simulators have limitations in
designing small circuits only. Recently researchers
have proposed CAD software tool for nano
magnetic logic circuits, i.e. Topolinano [5-6] and
MagCAD [7]. Both tools can analyse large and
complex circuits. In MagCAD tool both in-plane
NML (iNML) [8] and perpendicular NML (pNML)
[9] circuits can be designed, but in topolinano
only iNML circuits are supported. In pNML global
and perpendicular clock field is used, which
leads to the lower area and power consumption
[10]. Different three-dimensional pNML circuits
are demonstrated experimentally in [11-13] and
memory elements are shown in [14]. The most
important feature of pNML is the logic design in-
2. 375Int. J. Nano Dimens., 9 (4): 374-385, Autumn 2018
BK. Bhoi et al.
memory architecture, which is explained in [15-
16]. But till now digital circuits designing using
three-dimensional nano magnetic logic circuits
are not fully explored. Only exclusive-or gate, half
adder, 1-bit full adder, 4-bit ripple carry adder and
32-bit ripple carry adder circuits are designed in
[6, 17-21]. The ripple carry adders are designed
MagCAD tool by Turvani G et al. [6].
In this paper, we further explored digital
circuit’s architectures using this tool [6]. We
designed comparator, decoder and multiplexer
circuits using three-dimensional nano magnetic
logic circuits. In Section 2, background related to
perpendicular-nano magnetic logic circuits are
described. In section 3, a new 3-D architecture of
1-bit comparator, 2to4 size decoder, 2to1 and 4to1
size multiplexer’s structures are proposed. Finally,
in section 4 conclusion is present.
MATERIALS AND METHODS
Quantum-Dot Cellular Automata (QCA) is an
emerging technology which has the ability to
replace current CMOS technology [22]. It has
the beneficial features like higher device density,
scalability, higher speed of computation, robust
design, lower complexity etc. According to Physical
implementation QCA technology is divided to
four types (i.e. Metal-island QCA, Semiconductor
QCA, Molecular QCA and Magnetic QCA). The
sizes of metal-island QCA cell were demonstrated
as relatively large in micrometer dimensions.
The major disadvantage of this type of QCA
is that its operation temperature is extremely
low, which is in the range of milli-kelvin [23-24],
which prevents the construction of complex
QCA circuits running at room temperature.
Therefore, this technology is not suitable for
future electronics application. A semiconductor
QCA cell is composed of four quantum dots
manufactured from standard semiconductive
materials [25]. In semiconductor QCA, advanced
fabrication process is possible similar to existing
CMOS processes. However, current manufacturing
processes cannot provide mass production for
high performance and ultra-small semiconductor
QCA devices. To date, most QCA device prototypes
only have been demonstrated with semiconductor
implementations. In molecular QCA, a basic cell
is built upon only molecules. The molecules are
expected to be as small as 1 nm or even smaller.
Room-temperature operation of a molecular QCA
cell has been experimentally confirmed [26]. The
difficulty in realizing molecular QCA is due to the
high-resolution synthesis methods and positioning
of molecule devices. New construction methods
for molecular QCA, including self assembly on
DNA rafts, are under investigation [27]. However,
it is still very difficult to fabricate molecular QCA
systems with current technologies.
In magnetic QCA small magnetic dots are
present also known as nano-magnets having
different functionalities. These nano-magnets can
be referred both as a logic element and a memory
device, which are made of Co/Pt multilayer for
perpendicular NML [28]. Therefore magnetic
QCA is called as nano magnetic logic. Although
it’s operating frequency is low (around 100 MHz),
but it has the advantage of room-temperature
operation, extremely low power dissipation
and high thermal robustness. A simple majority
gate using this technology is already fabricated
[29]. The first large-scale QCA systems appear to
be possible with a magnetic QCA circuit, which
has fewer challenges during the manufacturing
process compared with other implementations
[22]. Because of fabrication advantages, magnetic
QCA technology is chosen in this work.
The NML technology is again split up into two
types depending upon the magnetic anisotropy.
Those are perpendicular NML (pNML) and in-plane
NML (iNML). When the magnetic orientation of
the nano magnets are in-plane; it is referred as
iNML and when the orientation is perpendicular
to the plane then it is referred as pNML. Both
bistable logic elements logic 0 and logic 1 of
iNML and pNML are shown in Fig. 1(a) and 1(b)
(a) (b)
Fig.1 Basic bistable logic elements (a) iNML (b) pNML
Fig.1 Basic bistable logic elements (a) iNML (b) pNML.
3. 376
BK. Bhoi et al.
Int. J. Nano Dimens., 9 (4): 374-385, Autumn 2018
respectively. The direction of Magnetization i.e.
whether it is magnetised in one direction or the
opposite, commonly referred to as “Up or Down”-
is used to represent the binary information. Such
as the nano magnet directed in upward direction
represents a logic ‘1’ and oriented in downward
direction represents a logic ‘0’.
Both pNML and iNML deal with nano magnets
that interact with anti-ferromagnetic behaviour.
The iNML has a complex clocking system which is
eliminated in pNML [5][7]. Along with it, the pNML
has various advantages over iNML such as less
power consumption and reduced area occupation.
In addition, it also allows the fabrication on three
dimensional (3-D) circuits and that too in a cost-
effective way as in CMOS technology 3-D circuits
comes with a huge fabrication complexity. The
pNML circuits start with a nucleation centre and
terminate with a pad magnet [7]. This condition
should be ensured for proper behaviour of circuit
parameters.
Basic Structures of pNML
pNML is the most efficient implementation of
the NML technology. In NML, the circuit complexity
is reduced due to the use of minority voter (i.e.
the minority gate). The minority voter and the
inverters are treated as the basic functional units
in pNML.
In Fig. 2(a) the pNML structure of an inverter
is shown where the input magnet surrounds the
output magnet. The output magnet structure [Fig.
2(b)] is called artificial nucleation centre (ANC).
Basically, when odd (minimum one and maximum
five) numbers of inputs are provided around
it, the total structure leads to a minority voter.
(a) (b)
(c) (d) (e)
(f) (g) (h)
(i) (j)
Figure 2: Basic pNML elements (a) inverter (b) nucleation centre (c) domain wall magnet (d)
corner magnet (e) Via magnet (f) T-connection (g) X-connection (h)Pad magnet (i) Fixed
‘0’Magnet (j) Fixed ‘1’ magnet
Fig. 2. Basic pNML elements (a) inverter (b) nucleation centre (c) domain wall
magnet (d) corner magnet (e) Via magnet (f) T-connection (g) X-connection (h)
Pad magnet (i) Fixed ‘0’Magnet (j) Fixed ‘1’ magnet.
4. 377Int. J. Nano Dimens., 9 (4): 374-385, Autumn 2018
BK. Bhoi et al.
Similarly, there are various magnetic elements in
pNML performing several functions. The structure
shown in Fig. 2(c) is a normal magnet (also known
as domain wall) which is the basic element of this
promising technology. It is mainly used to route
signals. The Fig. 2(d) shows the structure of a
corner magnet which is also a normal magnet but
with 900
rotation. In Fig. 2(e), there is a via magnet
which is used to connect to a nucleation centre
situated on another plane. So by use of this, we
can have one or two inter-layer outputs.
The T-connection magnet shown in Fig. 2(f)
is used to split the input into two different
directions. The cross-connection magnet shown
in Fig. 2(g) is also a simple magnet that splits the
input in three different directions. The Fig. 2(h)
shows a pad magnet which is mainly used as the
termination of a magnetic wire. Only a nucleation
centre can be used as its output. To implement
different functions in pNML we need to provide
certainly fixed inputs. The structures shown in Fig.
2(i) and Fig. 2(j) are the fixed ʽ0’ and fixed ʽ1’ input
magnets respectively.
A minority voter is shown in Fig. 3. Here there
are three numbers of inputs namely A, B and C. All
these inputs are connected to nucleation centres,
nucleation centres are connected to domain walls,
domain walls are connected to corner magnets
and corner magnets are connected to pad-
magnets. Here A, B and O outputs are in the same
layer, whereas C input is in a different layer. The
output expression is
Y= M(A, B, C) = 𝐴𝐴̅ 𝐵𝐵� + 𝐵𝐵� 𝐶𝐶̅ + 𝐴𝐴̅ 𝐶𝐶̅. (1)
Unlike molecular QCA, if any of its inputs are
fixed to 0 then it gives the NAND logic output and
if the input is fixed to 1 then it behaves as a NOR
gate. In the minority voter, it is necessary to have
equal geometry and distance of the three inputs
to the nucleation centre of the output for the
proper operation of the gate. In pNML for proper
propagation of the information within the circuit a
perpendicular clock field is applied and after every
clock cycle, the output of each building block is
placed in anti-parallel compared to the previous
input [27]. Because of this reversal mechanism,
the output of every building block can be used as
input for next block. So signal propagation takes
place in a step by step manner according to the
clocking field.
RESULTS AND DISCUSSIONS
The proposed works are based on pNML
technology. In pNML all the layout designs start
withanucleationcentrei.e.theinitialinputisgiven
to the nucleation centre. Here a 1-bit comparator,
a 2to4 decoder, a 2to1 multiplexer (MUX) and a
M
A
B
C
CACBBAY
(a) (b)
Figure 3. Minority voter (a) block diagram (b) 3-D Minority Voter
Fig. 3. Minority voter (a) block diagram (b) 3-D Minority Voter.
Table 1. Geometrical and Physical parameters
Parameters Value
Nanowire width 40nm
Grid size 120nm
Inter magnet space 150nm
Co thickness (Co=Cobalt) 3.2 nm
stack thickness 6.2nm
volume of ANC 1.68 ×10-23
m3
Clock field amplitude 560 Oe
Inverter coupling field strength 153Oe
Minority gate coupling field strength 48 Oe
Effective anisotropy 2.0 × 105
J/m3
Table 1. Geometrical and Physical parameters.
5. 378
BK. Bhoi et al.
Int. J. Nano Dimens., 9 (4): 374-385, Autumn 2018
4to1 multiplexer circuit’s layouts using pNML
concept is proposed. All the layouts are designed
using MagCAD tool [7]. After the formation of
layouts, VHDL netlist will be extracted. This netlist
file is the replication of the circuit behaviour, which
functionality is tested using ModelSim simulator,
with providing proper test bench. Geometrical and
physical parameters are provided in Table 1.
Comparator Design in pNML
The comparator is a digital electronic circuit that
compares two numbers. Here in this work the layout
of a 1-bit comparator using the pNML technology
has been proposed. In this circuit there are two 1-bit
inputs i.e. A and B and it produces three outputs (1-
bit) such as P for input A is less than input B (A<B), Q
for A equals to B (A=B) and R for A is greater than B
(A>B) which is shown in Fig. 4(a).
The minority gate schematic diagram is shown
in Fig. 4(b) and pNML layout is illustrated in Fig.
4(c). The expressions for comparator outputs are
derived in below equations using minority voters.
𝑃𝑃 = 𝑀𝑀1(1, 𝐵𝐵�, 𝐴𝐴) = 0 + 𝐵𝐵𝐴𝐴̅ + 0 = 𝐴𝐴̅ 𝐵𝐵 (2)
𝑄𝑄 = 𝑀𝑀6 ( 𝑀𝑀4(𝐴𝐴, 0, 𝑀𝑀3 (𝐴𝐴, 0, 𝐵𝐵)), 0, 𝑀𝑀5 (𝑀𝑀3 (𝐴𝐴, 0, 𝐵𝐵), 0, 𝐵𝐵))��������������������������������������������������������������������
= (𝑀𝑀6 ( 𝑀𝑀4(𝐴𝐴, 0, 𝐴𝐴𝐴𝐴����), 0, 𝑀𝑀5 ( 𝐴𝐴𝐴𝐴����, 0, 𝐵𝐵))�������������������������������������������������
= 𝑀𝑀6 ( 𝐴𝐴. 𝐴𝐴𝐴𝐴������������, 0, 𝐴𝐴𝐴𝐴����. 𝐵𝐵�������)
��������������������������
= 𝐴𝐴̅ 𝐵𝐵� + 𝐴𝐴𝐴𝐴
(3)
1-bit
Comparator
A
B
BA
BA
BA
A B
0 0
0 1
1 0
1 1
00
0 1
1 0
1
1
0
0
0 0
BA BA BA
(a)
(b)
(c)
Figure 4. 1-bit comparator (a) block diagram (b) schematic (c) 3-D pNML layout
Fig. 4. 1-bit comparator (a) block diagram (b) schematic (c) 3-D pNML layout.
6. 379Int. J. Nano Dimens., 9 (4): 374-385, Autumn 2018
BK. Bhoi et al.
R = 𝑀𝑀2 (𝐵𝐵, 𝐴𝐴̅, 1) = 𝐵𝐵� 𝐴𝐴 + 0 + 0 = 𝐴𝐴𝐵𝐵� (4)
The proposed design is a 3-D circuit because the
magnetic wires are in different layers. According
to the nano-magnetic phenomenon an input in a
particular layer is propagated in its inverted form
in another layer i.e. we can get the invert of an
input by just changing the layer.
Here both the inputs A and B are given to the
circuit layer ‘0’ initially. To get the P output, the
input A is applied to the minority voter directly in
layer ‘0’ but the input B is applied in layer ‘1’ so
as to provide its inverted form without using an
inverter circuit. Then a fixed ‘1’ input is given to
the other input terminal of the minority voter. The
basic concept of perpendicular-nano magnetic
logic states is that if any of the inputs of a minority
voter is being logic ‘0’ then it will function as a
NOR gate. Hence the minority voter produces the
required output P. Similarly to get the R output,
the input A is applied in the same layer ‘0’ to the
minority voter but input B is applied in layer ‘1’
to get the inverted B. Here also a fixed ‘1’ input is
given to the minority voter and then it produces
the output R which is high when input A is greater
than input B. To get the output Q, it requires four
numbers of minority voters along with an inverter
which in term forms an Ex-NOR gate.
The above Fig. 5 shows the simulation result
of the proposed layout of the 1-bit comparator.
The result clearly shows that the proposed design
successfully satisfies the truth table of the 1-bit
comparator. The total design occupies a bounding
box area of 2.4336 µm2
and it uses only six
numbers of minority voters and one inverter in the
total circuit. The circuit shows a critical path delay
of 0.15µs. It also exhibits different latencies for
different input combinations which are tabulated
below.
Decoder Design in pNML
Decoders are also called as function selector,
which converts n number of inputs to 2n
numbers
of outputs. So its standard size is n×2n
. Here a 2×4
decoder design is proposed, which is implemented
using the pNML concept. The block diagram is
shown in Fig. 6(a). The Fig. 6(b) and Fig. 6(c) shows
the minority gate schematic and proposed pNML
layout of the 2:4 decoder respectively. It is an
active high output decoder, i.e. only one output bit
is high at a time. In the pNML layout, four numbers
of minority voters and inverters are used. Here A
and B are the inputs to the decoder circuit. In the
layout of all minority voters fixed 0 inputs are used
which are behaving as NAND logic gates where
outputs are D0
=A’B’, D1
=A’B, D2
=AB’ and D3
=AB.
The boolean expressions for the decoder
outputs (Fig. 6(b)) using minority gates are shown
in below equations
𝐷𝐷0 = 𝑀𝑀1(𝐴𝐴̅, 𝐵𝐵�, 0)��������������� = 𝐴𝐴� 𝐵𝐵�������������
= 𝐴𝐴̅ 𝐵𝐵� (5)
𝐷𝐷1 = 𝑀𝑀4(𝑀𝑀2(𝐴𝐴, 0, 𝐵𝐵), 𝐵𝐵, 0)���������������������������
= 𝑀𝑀4 (𝐴𝐴𝐴𝐴���� , 𝐵𝐵, 0)������������������ = 𝐴𝐴𝐴𝐴����. 𝐵𝐵��������������
= 𝐴𝐴𝐴𝐴�����. 𝐵𝐵 = 𝐴𝐴̅ 𝐵𝐵 (6)
𝐷𝐷2 = 𝑀𝑀3�0, 𝐴𝐴, 𝑀𝑀2(𝐴𝐴, 0, 𝐵𝐵)�����������������������������
= 𝑀𝑀3 (0, 𝐴𝐴, 𝐴𝐴𝐴𝐴����)����������������� = 𝐴𝐴𝐴𝐴����. 𝐴𝐴��������������
= 𝐴𝐴𝐴𝐴�����. 𝐴𝐴 = 𝐴𝐴𝐵𝐵� (7)
𝐷𝐷3 = 𝑀𝑀2(𝐴𝐴, 0, 𝐵𝐵)��������������� = 𝐴𝐴𝐴𝐴�������� = 𝐴𝐴𝐴𝐴 (8)
The layout occupies a bounding box area of
1.0368µm2
. It has a critical path delay of 0.142µs.
Fig: 5 Simulation Result of the pNML layout of 1-bit ComparatorFig. 5. Simulation Result of the pNML layout of 1-bit Comparator.
7. 380
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Int. J. Nano Dimens., 9 (4): 374-385, Autumn 2018
2x4
Decoder
A
B
A B
0 0
0 1
1 0
1 1
00
0 1
10
1
1
0
0
0 0
0D
1D
2D
3D
0
0
0
0
0D 1D 2D 3D
(a)
2D
3D
1D
0DM1
M2
M3
M4
0
0
0
0
A
B
(b)
(c)
Figure 6 : Decoder of 2-to-4 size (a) block diagram (b) pNML schematic (c) 3-D pNML layout
Fig. 6. Decoder of 2-to-4 size (a) block diagram (b) pNML schematic (c) 3-D pNML layout.
The Fig. 7 shows the simulation result of the
proposed 2to4 decoder. Here there is a latency of
870 ns for D0
, 1620 ns for D1
, 860 ns for D2
and 850
ns for D3
outputs. The Table 3 below shows all the
features of the proposed design along with the
delays for several input combinations.
Multiplexers Design in pNML
The multiplexer is a universal circuit, which is
also known as Data Selector, Many to One, and
Parallel to Serial Converter. Here a 2to1 MUX has
been implemented using the perpendicular-nano
magnetic logic. The block diagram and minority-
gates schematic diagram are shown in Fig. 8(a)
and 8(b) respectively. The pNML layout of the
proposed MUX having two input lines namely
I0
and I1
, are applied to the circuit through the
nucleation centres. This is illustrated in Fig. 8(c).
The 2to1 MUX design proposed in this paper
comprises only three numbers of minority voters
without any inverter circuit.
In pNML, logic ‘0’ in a particular layer behaves as
logic ‘1’ in another layer. This property of pNML has
been exploited to design the proposed layout of the
MUX circuit. The selection input S is provided to the
initialtwominoritygatesintwodifferentlayers.Hence
one of the two minority voters is getting a direct input
S and the other is getting its inverted one i.e. S՚.
8. 381Int. J. Nano Dimens., 9 (4): 374-385, Autumn 2018
BK. Bhoi et al.
Figure 7: Simulation Result of Proposed Layout of 2:4 Decoder
Fig. 7. Simulation Result of Proposed Layout of 2:4 Decoder.
1In
Sel
2In
Out
(a)
M 1
M 2
M 3
S
1I
0
0I
0
0 Y
(b)
(c)
Figure 8: multiplexer of 2:1 size (a)block diagram (b)pNML schematic (c) 3-D pNML layout
Fig. 8. multiplexer of 2:1 size (a)block diagram (b)pNML schematic (c) 3-D pNML layout.
9. 382
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This design is based on NAND realization of
2to1 MUX. All the three minority voters in the
layout are having a fixed ‘0’ input along with other
two inputs; so that these minority voters behave
as NAND gates. Hence the circuit finally produces
an output as Y=I0
S+I1
S՚. The inputs are applied in
different layers rather than using any additional
inverting circuit which reduces the complexity
of the proposed circuit layout. The Boolean
expression for 2to1 MUX using minority gates is
given below.
𝑌𝑌 = 𝑀𝑀3�𝑀𝑀1(0, 𝐼𝐼0, 𝑆𝑆̅), 0, 𝑀𝑀2(𝑆𝑆, 0, 𝐼𝐼1)�
= 𝑀𝑀3�𝑆𝑆̅ . 𝐼𝐼0������, 0, 𝑆𝑆. 𝐼𝐼1�������
= 𝑆𝑆̅. 𝐼𝐼0������ . 𝑆𝑆. 𝐼𝐼1�������������������
= 𝑆𝑆̅. 𝐼𝐼0������������
+ 𝑆𝑆. 𝐼𝐼1������������ = 𝑆𝑆̅. 𝐼𝐼0 + 𝑆𝑆. 𝐼𝐼1
(9)
This design occupies a bounding box area of
0.8056µm2
. It exhibits a critical path delay of
0.14µs. The simulation result of the proposed
layout of 2to1 MUX is shown in Fig. 9 below. Here
from the waveform, it is shown that when the
selection line S is being 0, the circuit output Y is
equal to I0
value and when S is equal to 1, then the
circuit output will be I1
value. Here I0
is set as logic
‘1’ and I1
is set to logic ‘0’. For S=0 we are getting
Y=1 with a latency of 855 ns and for S=1, we are
getting Y=0 with a delay of 1000 ns. The same has
been tabulated below in Table 4.
In this paper, a novel 4to1 size multiplexer
pNML layout is also proposed which is formed by
the proper connection of three numbers of 2to1
multiplexers proposed earlier in this work. As each
2to1 MUX consists of three numbers of minority
voters, so a total of nine number of minority voters
are used to design the whole 4to1 MUX circuit.
The block diagram and pNML layout are
illustrated in Fig. 10 (a) and (b) respectively. This
design is also free from inverters. Here there are
four input lines i.e. I0
, I1
, I2
and I3
along with two
numbers of selection lines S0
and S1
. All the inputs
except I0
, are in layer ‘1’ and I0
is in layer ‘0’. The
layers of the inputs are changed in some cases
before applying it to the minority voters in order
to get its inverted form as per our requirement.
Fig. 11 shows the simulation result of the
proposed layout of 4to1 MUX. From this result, we
can conclude that the proposed layout completely
satisfies the truth table of 4to1 MUX. The proposed
circuit produces the expected output with some
delay which has been tabulated below in Table 5.
Here the input values are set as I0
=1, I1
=0, I2
=1
and I3
=0. From the simulation result it can be seen
thatwhentheselectioninputsS0
andS1
arebeing0,
the circuit produces the output Y as 1 (as I0
=1) with
a latency of 1144 ns. Similarly, for S1
=0 and S0
=1, we
are getting Y=0 with a latency of 1132ns, for S1
=1
and S0
=0, the circuit is producing the output Y=1
and for S1
=1 and S0
=1, Y is being 0 with a latency
of 1535ns. The total design occupies a bounding
box area of 2.9376µm2
and exhibits a critical path
delay of 0.159 µs. The below Table 6 shows the
comparison of the proposed NML circuits with
the existing CMOS technology. The comparative
performance results in Table 6, also proven that
the nano-magnetic based implementation of the
comparator, decoder and multiplexer has efficient
Table 2. Performance table of 1-bit Comparator
3-D Comparator (1-Bit)
Bounding Box Area = 2.4336 µm2
Critical path= 1.5E-7
sec
Inputs
A B
Outputs
P Q R
Latency
(in sec)
0 0
0 1
1 0
1 1
0 1 0
1 0 0
0 0 1
0 1 0
0.88E-6
0.79E-6
0.89E-6
0.99E-6
Table 3. Performance table Proposed of 2:4 Decoder
3-D Decoder(2:4)
Bounding Box Area= 1.0368µm2
Critical Path=1.42E-7
Inputs
A B
Outputs
D0 D1 D2 D3
Latency
(in sec)
0 0
0 1
1 0
1 1
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
0.87E-6
1.62E-6
0.86E-6
0.85E-6
Table 2. Performance table of 1-bit Comparator.
Table 3. Performance table Proposed of 2:4 Decoder.
Table 4. Performance Analysis of Proposed 3-D 2×1 MUX
3-D 2×1 MUX
Critical Path=1.4E-7
s
Bounding Box Area=0.8064µm2
Input pattern
S
Output pattern
Y
Latency
(in sec)
0
1
I0
I1
0.85E-6
0E-6
Table 5. Performance Analysis of Proposed 3-D 4×1 Multiplexer
3-D 4×1 MULTIPLEXER
Bounding Box Area= 2.9376µm2
Critical Path= 1.5E-7
sec
Inputs
S1 S0
Output
Y
Latency
(in sec)
0 0
0 1
1 0
1 1
I0(=1)
I1(=0)
I2(=1)
I3(=0)
1.1E-6
1.1E-6
1.5E-6
1.5E-6
Table 4. Performance Analysis of Proposed 3-D 2×1 MUX.
Table 5. Performance Analysis of Proposed 3-D 4×1 Multiplexer.
10. 383Int. J. Nano Dimens., 9 (4): 374-385, Autumn 2018
BK. Bhoi et al.
results in all the primitives as compared to the
existing CMOS implementation.
CONCLUSION
In the article, we have designed nano-
magnetic based computing in emerging devices
as a promising domain for high speed and
high-density integration. A new synthesis of
implementing magnetic dipole based comparator,
decoder and multiplexer are presented. These
proposed architectures produce less latency
which is easily verified by performance analysis
tables. The latency results depict that the fast
synchronization of inputs and outputs and shows
an efficient implementation in the physical
foreground. All the layouts proposed in this
paper are implemented on the MagCAD tool
using pNML technology. We have shown that
the nano magnetic logic offers superior results
with miniaturization of the area for proposed
designs as compared to existing 45nm CMOS
technology. The grid size and magnet width of
all the magnetic elements are set as 120nm
and 40nm respectively. MagCAD tool generates
VHDL file for the designed layout and to test the
functionality of the newly designed circuits. This
file functionality is later verified in the ModelSim
software. The miniaturisation of area properties
of the nano-magnetic based present designs has
afforded avenues for the miniaturizations and
implementation of future electronics applications.
Figure 9: Simulation Result of the Proposed 2×1 MUX Layout
Fig. 9. Simulation Result of the Proposed 2×1 MUX Layout.
Table 6. Comparison with existing CMOS technology.
Exiting CMOS 45nm Technology in (Area) Proposed pNML (Area)
1-bit Comparator 58.80 µm2
[30] 2.43 µm2
2:4 Decoder 22.4 µm2
[31] 1.03 µm2
2:1 Multiplexer 28.9 µm2
[32] 0.80 µm2
Table 6. Comparison with existing CMOS technology.
0I
1I
3I
2I
0S
1S
Y
2:1 Mux
2:1 Mux
2:1 Mux
(a)
(b)
Figure 10. Multiplexer of 4:1 size (a)Block Diagram (b) 3-D pNML Layout
0I
1I
3I
2I
0S
1S
Y
2:1 Mux
2:1 Mux
2:1 Mux
(a)
(b)
Figure 10. Multiplexer of 4:1 size (a)Block Diagram (b) 3-D pNML Layout
(a)
(b)
Fig. 10. Multiplexer of 4:1 size (a)Block Diagram (b) 3-D
pNML Layout.
11. 384
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Int. J. Nano Dimens., 9 (4): 374-385, Autumn 2018
Figure 11: Simulation result of the 3-D pNML Layout of 4×1 Multiplexer.
Fig. 11. Simulation result of the 3-D pNML Layout of 4×1 Multiplexer.
CONFLICT OF INTEREST
The authors declare that there are no conflicts
of interest regarding the publication of this
manuscript.
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