Ijciet 10 02_068

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International Journal of Civil Engineering and Technology (IJCIET)
Volume 10, Issue 02, February 2019, pp. 702-714, Article ID: IJCIET_10_02_068
Available online at http://www.iaeme.com/ijciet/issues.asp?JType=IJCIET&VType=10&IType=02
ISSN Print: 0976-6308 and ISSN Online: 0976-6316
© IAEME Publication Scopus Indexed
MINIMIZED ENERGY CONSUMPTION BASED
QCA REVERSIBLE ADDER
Jun-Cheol Jeon
Department of Computer Engineering, Kumoh National Institute of Technology,
Gumi, Gyeongbuk, South Korea.
ABSTRACT
Programmable reversible logic is growing for a potential logic design type
concerning execution around advanced nanotechnology as well as quantum computing
with minimum effect upon circuit temperature production. Current improvements in
reversible logic utilizing additionally quantum computer calculations permit enhanced
computer structure plus arithmetical logic unit layouts. Since reversible circuits
continue to be fairly unique, the most significant study effect is found on the synthesis
of these circuits. Quantum-dot cellular automata (QCA) can be a promising part of
investigating at reversible computing. QCA-based design of the reversible 1-bit full
adder is using the Toffoli and Feynman gates have been achieved in this study. We
develop an improved reversible full adder with overflow detection to enhance
reliability. This component promises to complete the fundamental mathematical
functions of addition, subtraction alongside overflow detection, comparison, along with
logic procedures such as significance. Thus our design is very efficient and versatile
alongside lower quantity of lines as well as quantum cost. This work understands and
nurtures the necessity of reversible full adder for future revolutionary computing
technologies. In this paper, a reversible 1-bit full adder is proposed and compared with
other reversible full adders. Proposed gate performs better than existing methods and
ensures maximum logical operations like the full adder, full with less quantum cost
where other existing gates are not viable.
Key words: Energy dissipation analysis, reversible, full adder, single layer circuit.
Cite this Article: Jun-Cheol Jeon, Minimized Energy Consumption Based Qca
Reversible Adder, International Journal of Civil Engineering and Technology, 10(02),
2019, pp. 702–714
http://www.iaeme.com/IJCIET/issues.asp?JType=IJCIET&VType=10&IType=02
1. INTRODUCTION
In the last generations, perfectly accomplishments have been manufactured in the improvement
of computing equipment’s. Nevertheless, because of to exponential development of transistor
thickness as well as in specific due to greatly growing energy expenditure, scientists anticipate

Jun-Cheol Jeon
that “Conventional Technologies” such as CMOS will get to their restrictions in nearby
upcoming. In order to even more fulfill the requirements for additional procedure energy,
performance; lower dimensions etc. options are necessary. Reversible computation is the
promising sphere plus approach of traditional techniques [1].
Moore’s law defines a long-term movement as part of the background of processing
equipment: the quantity regarding transistors that have been applied affordably during an
incorporated circuit increases about each couple of years. Subsequently the entire year 2020
and also 2030 might discover the circuits during an Integrated circuit assessed on an atomic
measure. As more and more logic components towards compact additionally smaller volumes
and delay these at higher and higher frequencies, additional temperature is going to be
dissipated. This produces a minimum of three issues: power prices funds, lightweight
techniques fatigue their particular power packs as well as techniques heat up. Whenever a
computational method removes a bit concerning data, it needs to disperse ln 2 × kT power,
whenever k is Boltzmann’s constant then T will be the heat [2].
Present technologies tend to be discovering it complicated to keep with the needed degree
of development. Renewable technologies are growing to take place so that the growth energy
can be proceeded. Reversible computing is one of the computing system in which new
generation computing system could be created. Due to the fact of its fundamental quality of
reversibility, it maintains the existing information as well as decreases dispersion of
temperature in its operation. This guarantee produces the technology as one of the potential
approach for upcoming.
These days computers eliminate a bit of articles whenever that they execute a logic
functioning. These kinds of logic functions are thus known as “irreversible”. This erasure is
complete extremely inefficiently, and also significantly more compared to kT is dissipated to
every single bit removed. As well as the logical following move will be to generate quantum
computers, which is will undoubtedly control the energy of atoms and molecules to execute
memory and operating activities. Quantum computers possess the prospective to undertake
specific computations considerably quicker compared to any silicon-based computer. A
quantum computer can be described as hardware to calculation that produces straight utilization
of quantum mechanical occurrences, including superposition as well as entanglement, to
execute functions on data. Quantum computers are wide and varied through digital computers
dependent on transistors. Although digital computers need data to obtain encoded towards
binary digits, quantum computation utilizes quantum attributes to describe information as well
as conduct procedures on these information. In this example, Reversible logic can play a
essential character in transforming classical computation techniques into Quantum
computation caused by its reversible attributes. Normally labeled as reversible logic process,
and furthermore theory they could scatter randomly minimal temperature. Because the power
dissipated each irreversible logic process concepts the essential restrict to ln 2 × kT, employing
reversible procedures most probably will come to be better appealing. Contained in this paper,
a unique 1-bit reversible logic full adder is proposed which exhibits less quantum cost and
garbage outputs for a high computation intensive process like Arithmetic and Logic Operations
[2-4].
To accomplish reversibility it's important to create logics in a way that recovered output
form the logics need to have adequate information to obtain back inputs. In computational
system we should have gates which have one to one mapping around input and output, that
computational system is known as reversible computation. Reversible logic cannot result into
destruction of information (bits) but it just map one state to other. To make this happen,
reversible logics were created alongside equivalent quantity of input and output. Reversible

Minimized Energy Consumption Based Qca Reversible Adder
gates are gates that makes use of reversible logics and start to become there is no loss of
information therefore reversible gates does not benefits into any heat dissipation. The
motivation behind reversible calculation arrives starting reduced energy dispersion as well as
near connection in order to quantum circuits, and, about the almost upcoming, might be turned
out to be a competition towards existing traditional circuits.
With this reason, we call the proposed gate as reversible 1-bit full adder and its important
benchmarks are compared and discussed. The invention of new gate is mainly towards
inventing new designs to optimize reversible circuits in a specific technology. Certain
preferable properties of the already known gates are extended by following standard synthesis
methods. Proposed gate is compared with the existing reversible 1-bit full adder using the
synthesis results obtained from the QCADesigner tool is the synthesis techniques followed in
this work to validate the proposed reversible adder.
Minimizing the quantity of garbage components and amount of QCA cells as well as
latency are the major concerns in reversible logic circuits and it is observed that proposed
reversible 1-bit full adder achieves minimum garbage output and trusted on extreme
performance additionally minimal energy reversible circuits. And the proposed full adder is
compared with recently proposed full reversible adder with regards to quantum cost, amount
of gates QCA cells. Another challenging direction in this domain is functionality to reversible
logic circuits. In this paper, we considered exact 1-bit full adder based reversible methods to
analyze the proposed circuit advantages on top of the current types.
The remainder of the paper is arranged that accepts. Section 2, the background of QCA
concept is presented. Section 3, summarizes the related work on reversible logic and gates.
Additionally, deals with the background knowledge about basic reversible full adders are
presented in this section. Section 4 presents the synthesis techniques considered in this work to
validate the proposed 1-bit reversible full adder with reversible Toffoli and Feynman gates.
Section 5 discusses the different synthesis results using QCAProo Tool and QCADesigner. Our
proposed QCA reversible 1-bit full adder is compared to available counterparts in the Section
6. Subsequently, Section 8 proves the paper.
2. QCA PRELIMINARIES
Given that a replacement for CMOS-VLSI, scientists have suggested a method to processing
among quantum dots, the quantum cellular automata (QCA). Beforehand suggested in 1994,
as opposed to traditional computers in which data is transmitted starting one destination to a
different through implies concerning power current, QCA exchanges data through propagating
a polarization condition [1, 6]. QCA is dependent on the encoding to binary data in the demand
arrangement inside quantum dot cells. Procedure energy is supplied because of the Coulombic
interaction around QCA cells. Absolutely no current moves around cells and no energy as well
as data is provided to specific inside cells. The localized interconnections around cells are
supplied because of the physical science of cell-to-cell interaction because of towards the
rearrangement to electron placements [2-5].
A quantum cell is main element of QCA. Each QCA cell composed of four quantum dots
with two free electrons. The positions of the electrons denote the logic state. There are two
position in QCA as cell polarization P = +1 and P = -1 shown in Figure 1(a). Resulting either
polarization P = +1 to introduce binary “1” and P = -1 to introduce binary “0”. When two cells
are getting nearly together, due to coulombic interaction the cells accept on the same
polarization [5]. Binary information is propagated using cell states [7].

Jun-Cheol Jeon
Quantum-dot
P =+1
( Binary “1”)
P =-1
( Binary “ ”)
Electron
Tunnel
junction
Quantum-dot
M(A,B,C)
A
B
C
(a) (b)
0
Figure 1 (a) QCA cells with two different polarizations, (b) QCA 3-input majority gate
(b)
Input=A Output=A`
(a)
State: 0
State: 0
State: 1
State: 1
(Y)
(X)
State: 1
State: 0
State: 1
State: 0
(Y)
(X)
Input=A
Output=A`
Figure 2 (a) Typical wire-crossing techniques coplanar and multilayer crossover, (b) QCA inverter
structures robust inverter and simple inverter.
Figure 3 Clocking scheme
The principle advantage of QCA is the high packing thickness gave by them. The
rearrangements of interconnections between any two cells are another preferred standpoint to
support them. No current stream is included. The nonattendance of current stream radically
lessens the power utilization and the related losses. Majority gate and inverter are essential
building parts of this technology. Three input majority gate is conventional majority gate and
its equation is M(A,B,C) = AB + AC + BC. The function of the majority gate is to generate
three inputs and eventually to get desired output. It is composed of five QCA cells: three input
cells (A, B and C), one output cell (M(A,B,C)) and one inside cell. It can be implemented by
five cells arranged in a cross as illustrated in Figure 1(b) [8, 13]. Any digital logic circuit is
represented by logic AND or OR operation. If one of the inputs is set to polarization minus
one, logic AND operation can be constructed in the majority gate. Similarly, one of the inputs

is set to polarization plus one, logic operation OR is constructed. Hence, any complex logic
circuits can be implemented from logic OR and logic AND gates respectively as:
A+B=M(A,B,1) (1)
AB=M(A,B,0) (2)
QCA wire is constructed with plural numbers of cells. By QCA wire information is transfer
cell by cell since electrostatic interaction. By placing cell with their edges contact sequentially,
simple QCA inverter is implemented. It is used to invert transferring signal from one form to
invers form, as shown in Figure 2(b). In this technology, wire crossing is complicated point in
the crossing two different wires. There are two types of wire crossing, such as coplanar wire
crossing technique and stereoscopic wire crossing, namely multilayer form, as illustrated in
Figure 2(a). For getting strong signal strength, multilayer wire crossing is more proper than
coplanar crossing which is composed of rotated cells [5, 6]. However, there is another efficient
form of coplanar wire crossing and it is based on QCA clocking technique [9-11].
QCA circuits use clock system for manage data transfer and synchronize. The main
advantage of QCA clock system is to provide the power to run the circuit because the quantum
cells are not exterior source for powering. QCA clock system makes use of four phases clocking
for regulating cells. It is realized by the steps: switch, hold, release and relax phases, as
demonstrated in Figure 3. As a mentioned before, QCA clocking can be utilized in the wire
crossing. QCA circuit is divided with four clock zones. The zero zone (zone-0) cannot meet
with zone two (zone-2), similarly, zone one (zone-1) cannot meet with zone three (zone-3). By
the concept, wire crossing can be realized in QCA circuit easily [12].
3. RELATED WORK
The research to be able to realize the calculation system furthermore their restrictions looks
previous which computers independently. Below, unfortunately we cannot presume from the
algorithmic limit although the restrictions being required because of the actual physical globe.
Most computers were located inside the physical world, hence the regulations concerning
physics, subsequently, furthermore implement towards computers incorporating their unique
circuits also memory. Scientists have suggested a method to avoid this problem with reversible
computing. Around 1973 with Bennett’s seminal paper [2], in which Bennet characterized
initial common reversible calculation system; Bennett restricted the traditional Turing
machines in order to establish the reversible Turing machines.
Reversible computing had been presented as a result of Bennett [2-4] as well as issues
(universal) calculation systems in which an outcome is not able to simply be calculated,
nevertheless additionally uncomputed. We furthermore determine such as systems being each
forward as well as backward deterministic. Although a reversible computation system does
compute every one of the injective computable features, infectivity is certainly not adequate in
order to define a reversible computing model; we ought to additionally need that every
computation stage is bijective. This significant necessity offers the association to conservation
to information that will be a key inspiration for analysis in reversible computing. A
determination which includes their basis in 1961 with a concept characterized by Landauer
[14]; a concept that has been experimentally confirmed really newly.
Reversible computing covers procedure systems which can be each forward as well as in
reverse deterministic. Such types provide purposes at system inversion as well as bidirectional
processing and tend to be additionally worthwhile as research to technical qualities. The
inspiration concerning reversible computing arrives, nevertheless, frequently coming from the
reality these types of models are information protecting. Designing reversible 1-bit full adder

Jun-Cheol Jeon
circuits on paper becomes really complicated, therefore We have created two unique design of
reversible gates specifically as Toffoli [15] and Feynman. By designing compact gates that can
streamline the execution procedure. These types of two reversible gates are often applied in a
garbage-free layout flow, in which circuits are characterized by the low-power energy
consumption.
The number of inputs and the number of outputs are equal to in reversible logic circuits
with the one-to-one mapping between them. A number of 1’s in the inputs is equal to the
number of 1’s in the outputs. If the output is given then it is possible to recover the input [3].
Therefore, it is called reverse logic. The first reversible logic gate is 3 3 Toffoli gate. Figure
1 illustrates the block diagram of the gate and its trust table, respectively. It is also called
Controlled-Controlled-NOT. Toffoli gate can be an illustration regarding two-through gates,
due to the fact two from the inputs become provided to the output. Likewise, the approach to
k-through gates is generally released, in addition to the approach of k k Toffoli Gates. Overall,
with a reversible gate among n inputs plus n outputs, the matrix is of size 2n 2n.
Feynman gate extensively applied notational system includes an inherent 1-dimensional
construction, in the same manner the gates exclusively manage vertically using computations
proceeding starting left to right. Such a 1-dimensional design a great definition regarding
various quantum architectures including reversible full adder structure. The Feynman gate is
2 2 reversible gates which routes one input to one output. Input vectors= (A, B) and output
vectors= (P, Q).
In this section, we present the work that’s being carried out as part of this paper. In
computing paradigm, the Full adder is one of the computing intensive building blocks of the
computer that performs arithmetic and logical operations. The addition is a basic and a
fundamental operation involved in any digital logic design or a control system design.
The performance of any digital system is characterized and heavily influenced by the
performance of the adders in that design. Various designs of fast adders have been proposed
by various authors in every possible technology starting from CMOS to nanoscale
implementations such as spin wave functions, QCA’s to name a few. In this work, we intend
to present an adder design based on the reversible computation which will be robust and power
efficient in comparison to the existing designs. Before we get into details of the proposed adder
and the metrics to be used for comparison, we will get an insight into the existing reversible
adder designs based on QCA.
Various reversible 1-bit full adder structures are proposed by researchers. One of new
example is suggested by Taherkhani et al [23] in 2017. This reversible gate includes 3 inputs
X1, X2, X3 as well as produces 3 outputs Y1, Y2 and Y3. “In this reversible 1-bit adder, an easy
along with thick two-input exclusive-OR (XOR) layout [16] is applied to recognition of the 3rd
output (Y3).

B
A
1.00
1.00 1.00
1.00
-1.00
-1.00
1.00
1.00
-1.00
-1.00
C
Cout
Bout
Gar
Sum/Diff
Figure 4 Reversible 1-bit full adder/subtarctor by E. Taherkhani et al. [23]
Furthermore, concerning wire crossing, the single layer technique operating various clock
zones is employed. Actually worth observing a Feynman gate at x as well as y inputs produces
x and x⊕y outputs [6]. During the suggested layout, the initial FG replicates the B input and
the second one is used to create a three-input XOR (A⊕B⊕C). Sum and Diff are the sum and
difference of the three inputs, respectively and Cout plus Bout is the output hold additionally
borrows, correspondingly.” Moreover, the fourth output (A⊕C) is a garbage output.
Concerning execution of reversible 1-bit adder circuit is necessary 228 QCA cell and 0.28 µm2
area. QCA implementation of Taherkhani et al [23] design is illustrated in Figure 4.
4. PROPOSED 1-BIT REVERSIBLE FULL ADDER
The suggested reversible 1-bit full adder is a three input reversible circuit. A,B,C are inputs. A,
A XOR B, SUM, Cout are outputs. This circuit demands three reversible gates named as Toffoli
gate and Feynman gate and also generates two garbage outputs. That layout involves the lower
quantity of QCA cells and low garbage outputs compared to [21-23] repeatedly. Within this
section, we're going to additionally demonstrate the advance of our recommended past
reversible full-adder circuit. We establish the reversible full-adder circuit using the support to
the unique design of Toffoli and Feynman gates was shown in Figure 5(a) and Figure 5(b),
respectively. Clocking based wire crossing is accomplished to cross the wire. The structure is
constructed of the regular cell. By the standard, all input cells are placed in one side, the outputs
are placed in another side. It helps to actualize the proposed design to combinational QCA
designs, such as arithmetic and logic unit architecture. The block diagram furthermore QCA
execution of proposed reversible 1-bit full adder is given in Figure 6. The proposed new design
of Toffoli gate composed of one 3-input majority and one XOR gate. This layout consists of
46 quantum cell and using 4 clock phases. The structure is occupied by 0.058 µm2
total area
with low complexity. In this design, single layer wire crossing which is based on QCA clocking
is used. It can lead to the compact circuit and realization of the design in complex circuit
architecture can be more proper.

Jun-Cheol Jeon
-1.00
R
-1.00
Q
PA
B
C
-1.00 Q
(a) (b)
A
B
P
Figure 5 Reversible gates: (a) Toffoli gate [15], (b)Feynman gate
Toffoli
gate
Toffoli
gate
Feynman
gate
Feynman
gate
A
B
0 C
A
SUM= A⊕⊕⊕⊕B⊕⊕⊕⊕C
A⊕⊕⊕⊕B
Cout= (A⊕⊕⊕⊕B)C⊕⊕⊕⊕AB
(a)
-1.00
-1.00
-1.00 -1.00
-1.00-1.00
-1.00
A
B
C
A
A⊕⊕⊕⊕B
SUM= A⊕⊕⊕⊕B⊕⊕⊕⊕C
Cout= (A⊕⊕⊕⊕B)C⊕⊕⊕⊕AB
(b)
Figure 6 Proposed reversible 1-bit full adder: (a) block diagram, (b) QCA implementation
Several prior works are discussed Toffoli gate in QCA technology. Some of them are
misalignment to the standard form of the reversible structure, such as less complexity design

[17] is used fewer cells in his design, but one of the outputs is placed inside of the structure. In
the design [17], all construction way is by the rule of reversible construction, but with more
cell count and bigger occupation area. The proposed layout maintains reached enhancements
with regards to used cell count, total area as well as with regular construction way.
Table 1 Truth table of reversible 1-bit full adder
Input Output
A B C Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
There are several Feynman gate structures are investigated by researchers. For getting an
efficient result, in all previously structures required many gates, area, and delay. Although, our
proposed circuit composed of only one XOR gate [18]. This layout consists of 17 quantum cell
and using 1 clock phases. The structure is occupied by 0.01 µm2
total area with low complexity.
In this design, single layer wire crossing which is based on QCA clocking is used. It can lead
to the compact circuit and realization of the design in complex circuit architecture can be more
proper. By this way, we get the optimal and efficient circuit to connect to other larger circuits.
Our proposed design can be more efficient for reversible designs and it is more complex than
the prior circuit.
The two new designs of reversible gates Toffoli and Feynman were suggested plus could
apply a reversible 1-bit full adder having a decreased quantum cost that will be equivalent
towards the quantity of QCA cells involved, lower propagation delay, as well as among
absolutely no overhead with regards to amount of ancilla inputs then the garbage outputs. The
recommended reversible 1-bit adder layout established on the Toffoli additionally Feynman
reversible gates tend to be reviewed as well as displayed to become improve compared to
another current design of reversible adder projected in the reversible field with regards to the
amount of QCA cells, delay, and the garbage outputs. It is composed of 129 cells with 0.13
µm2
areas, by realizing low-complexity XOR gate and one majority gate. The desired output
is generated after 1.75 clock phases. The new proposal reversible gate can be substantiated
regarding the number of gates which guarantees less propagation delay contrast with existing
gates. We have demonstrated the layout involving a reversible adder then executed this
utilizing just reversible logic gates. Whereas normally even compact circuits, using promote
improvement it ought to be conceivable to utilize comparative methodologies to actualize even
larger circuits. Most of the time, the arithmetic capacity itself should likewise be redefined,
with the end goal that it can be communicated reversibly. Our recent perform on reversible 1-
bit adder based on QCA is the undeniable illustration. Being mindful of this, we require
additional outline deal with low garbage output executions of reversible circuits.
The proposed reversible adder is going to be an essential element on the every QCA
reversible arithmetic logical unit (ALU) definitely a very important aspect in an extended range
of optical signal handling programs. Although maintaining over discussed variables in
thinking, we provide suggested streamlined reversible 1-bit adder layout techniques focusing

Jun-Cheol Jeon
on various promising nanotechnologies. The paper provides the subsequent benefits in
direction of the layout research additionally system of reversible circuits in promising features.
5. RESULTS AND DISCUSSION
The proposed reversible 1-bit adder and existing is synthesized using Toffoli and Feynman
gates. Quantum cost, and number of gates and input/output lines are considered as benchmarks
to evaluate the proposed reversible 1-bit adder with existing adders [21-23]. To achieve 1-bit
addition and logical operations using the existing reversible adders require more number of
QCA cells and consume more gate delay. Using proposed new design of reversible gates, all
possible arithmetic and logical operations with single gate is possible without any more gate
delays. Added to this, proposed reversible 1-bit full adder performs with less number of Taffoli
gate and Feynman gate, quantum cost and number of input/output lines using reversible
computation. Proposed design can be substantiated in terms of number of gates which ensures
less propagation delay compare to existing reversible adders.
In future, proposed reversible 1-bit full adder will be validated as a basic building logic of
a reversible logic circuit. Due to its technology limitations, presently, traditional computing
evolves by improving the parallelism. In future, certain emerging computing like QCA will
adopt reversible logic. After more validation of proposed design in larger circuits and
enhancements, it can be practically realized using QCA logical gates. Our projected circuit had
been functionally verified utilizing the QCADesigner tool [19] that is efficient simulation tool
for QCA circuit. Configuration of the tool is set to bistable approximation. The simulation
wave-form of the design is demonstrated in Figure 7 and it confirms that all functionality of
the presented gate works well with strong signal strength. In the simulation result, red rectangle
shows binary sequence of the truth table of the reversible 1-bit full adder and it matches
relatively with original one, as illustrated in Table 1.
Figure 7 Simulation result of proposed reversible 1-bit full adder
A detailed study in the suggested scheme along with the existing established scheme based
on the power consumption is presented in this section. We try to compute the energy dissipation
by QCAPro tool [20] (0.50Ek, 1.00Ek, 1.50 Ek) for proposed reversible 1-bit full adder and
compare the results for power efficiency. It is clearly seen by the Figure 8, our proposal design
is low-power consumption circuit.

Figure 8 Power dissipation map for the proposed reversible 1-bit full adder with 0.5 Ek
6. COMPARISION AND CONCLUSION
Different kinds of established QCA reversible layouts concerning 1-bit full adder during the
written material for instance the design in [21-23]. Therefore, we've been outlining the number
of QCA cells, delay, usage area, power consumption belonging to the different reversible 1-bit
adders employed for the established perform in Table 2 and Table 3 respectively. For
comparison we intend to compare our proposed designs with the existing QCA reversible 1-bit
adder that make use of both reversible gates in their design. The QCA representation of the two
existing adders which is used for comparison is as shown in Table 2.
Table 2 Comparison table of reversible 1-bit full adders
Circuits Cell count Area (μm )
Latency
(clock cycles)
Kianpour et al.[21] 399 0.50 2.00
Mohammadi et al.[22] 351 0.41 1.50
Taherkhani et al.[23] 228 0.28 1.75
Proposed 129 0.13 1.75
For our proposed reversible 1-bit adder the number of cells is 129 cells. QCA cells are
extremely area efficient for digital circuits. It typically has an area of 0.13 µm2
with a cell
dimension of 10 nm. Through Table 2 it is able to be observed about the suggested layout
belonging to the reversible 1-bit full adder attains the enhancement percentages extending 43
% compared to the best and recent circuit presented in design of [23] in terms of quantity of
QCA cell. The Table 3 demonstrates the assessment around the suggested design using the
established designs of power consumption, proposed in [22, 23]. From Table 3, it is visible
about the suggested layout of reversible 1-bit full adder attains the advance rates varying 45 %
with regards to power consumption contrasted with regard to the design provided in [23].

Jun-Cheol Jeon
Table 2 Comparison table of reversible 1-bit full adders
Circuits
Avg. leakage energy
dissipation (eV)
Avg. switching energy
dissipation (eV)
Total energy
consumption (eV)
0.5 Ek
1.00
Ek
1.50
Ek
0.5
Ek
1.00
Ek
1.50
Ek
0.5 Ek
1.00
Ek
1.50
Ek
[22] 0.094 0.271 0.486 0.354 0.309 0.275 0.448 0.579 0.761
[23] 0.068 0.209 0.376 0.269 0.236 0.203 0.337 0.445 0.579
Proposed 0.042 0.125 0.222 0.124 0.108 0.092 0.166 0.233 0.314
The goal of this work was to exploit the inbuilt reversible nature of QCAs and design energy
efficient circuits. The efficiency and the gains provided by the custom technique were
demonstrated with the help of new design of reversible gates based on the custom reversible
technique and compared with existing designs. There is additionally demonstrated the structure
of a reversible processing structure as well as applied it operating exclusively reversible logic
gates. Although, these are even simple techniques, alongside extra improvement it needs to be
available to work with alike techniques to make usage of still bigger models. A broad
conclusion that can be drawn from this work is that reversible 1-bit full adder does offer a lot
of savings in terms of power and area. Other particularly, there is produced unique low garbage
output circuits concerning addition furthermore were performing in direction of a standard
multiplication circuit. A novel design technique for low power computation based on
reversibility in QCA’s. Low quantum cost reversible circuits to build the emerging quantum
computing machine can use the proposed 1-bit full adder for better reversible performance.
From proposed design experience, we know that circuit rapidly ends up being challenging
whenever efficiency also amount of wires included were improved. Circuit that makes use of
both Laundeur and Bennett clocking scheme can be designed and tested for efficiency in terms
of power and performance.
ACKNOWLEDGEMENTS
This work was supported by the National Research Foundation of Korea (NRF) grant funded
by the Korea government (MSIP) (NO. NRF-2017R1D1A3B03034346).
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